Changes

Jump to navigation Jump to search
18,904 bytes added ,  19:06, 8 August 2020
More complete documentation
Line 19: Line 19:  
!  Width
 
!  Width
 
|-
 
|-
| TSEC_THI_INCR_SYNCPT
+
| [[#TSEC_THI_INCR_SYNCPT|TSEC_THI_INCR_SYNCPT]]
 
| 0x54500000
 
| 0x54500000
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_INCR_SYNCPT_CTRL
+
| [[#TSEC_THI_INCR_SYNCPT_CTRL|TSEC_THI_INCR_SYNCPT_CTRL]]
 
| 0x54500004
 
| 0x54500004
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_INCR_SYNCPT_ERR
+
| [[#TSEC_THI_INCR_SYNCPT_ERR|TSEC_THI_INCR_SYNCPT_ERR]]
 
| 0x54500008
 
| 0x54500008
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_CTXSW_INCR_SYNCPT
+
| [[#TSEC_THI_CTXSW_INCR_SYNCPT|TSEC_THI_CTXSW_INCR_SYNCPT]]
 
| 0x5450000C
 
| 0x5450000C
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_CTXSW
+
| [[#TSEC_THI_CTXSW|TSEC_THI_CTXSW]]
 
| 0x54500020
 
| 0x54500020
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_CTXSW_NEXT
+
| [[#TSEC_THI_CTXSW_NEXT|TSEC_THI_CTXSW_NEXT]]
 
| 0x54500024
 
| 0x54500024
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_CONT_SYNCPT_EOF
+
| [[#TSEC_THI_CONT_SYNCPT_EOF|TSEC_THI_CONT_SYNCPT_EOF]]
 
| 0x54500028
 
| 0x54500028
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_CONT_SYNCPT_L1
+
| [[#TSEC_THI_CONT_SYNCPT_L1|TSEC_THI_CONT_SYNCPT_L1]]
 
| 0x5450002C
 
| 0x5450002C
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_STREAMID0
+
| [[#TSEC_THI_STREAMID0|TSEC_THI_STREAMID0]]
 
| 0x54500030
 
| 0x54500030
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_STREAMID1
+
| [[#TSEC_THI_STREAMID1|TSEC_THI_STREAMID1]]
 
| 0x54500034
 
| 0x54500034
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_THI_SEC
+
| [[#TSEC_THI_THI_SEC|TSEC_THI_THI_SEC]]
 
| 0x54500038
 
| 0x54500038
 
| 0x04
 
| 0x04
Line 71: Line 71:  
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_CONTEXT_SWITCH
+
| [[#TSEC_THI_CONTEXT_SWITCH|TSEC_THI_CONTEXT_SWITCH]]
 
| 0x54500060
 
| 0x54500060
 
| 0x04
 
| 0x04
Line 83: Line 83:  
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_CONFIG0
+
| [[#TSEC_THI_CONFIG0|TSEC_THI_CONFIG0]]
 
| 0x54500080
 
| 0x54500080
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_DBG_MISC
+
| [[#TSEC_THI_DBG_MISC|TSEC_THI_DBG_MISC]]
 
| 0x54500084
 
| 0x54500084
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_SLCG_OVERRIDE_HIGH_A
+
| [[#TSEC_THI_SLCG_OVERRIDE_HIGH_A|TSEC_THI_SLCG_OVERRIDE_HIGH_A]]
 
| 0x54500088
 
| 0x54500088
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_SLCG_OVERRIDE_LOW_A
+
| [[#TSEC_THI_SLCG_OVERRIDE_LOW_A|TSEC_THI_SLCG_OVERRIDE_LOW_A]]
 
| 0x5450008C
 
| 0x5450008C
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_CLK_OVERRIDE
+
| [[#TSEC_THI_CLK_OVERRIDE|TSEC_THI_CLK_OVERRIDE]]
 
| 0x54500E00
 
| 0x54500E00
 
| 0x04
 
| 0x04
Line 135: Line 135:  
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_GPTMRINT
+
| [[#TSEC_FALCON_GPTMRINT|TSEC_FALCON_GPTMRINT]]
 
| 0x54501020
 
| 0x54501020
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_GPTMRVAL
+
| [[#TSEC_FALCON_GPTMRVAL|TSEC_FALCON_GPTMRVAL]]
 
| 0x54501024
 
| 0x54501024
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_GPTMRCTL
+
| [[#TSEC_FALCON_GPTMRCTL|TSEC_FALCON_GPTMRCTL]]
 
| 0x54501028
 
| 0x54501028
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_PTIMER0
+
| [[#TSEC_FALCON_PTIMER0|TSEC_FALCON_PTIMER0]]
 
| 0x5450102C
 
| 0x5450102C
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_PTIMER1
+
| [[#TSEC_FALCON_PTIMER1|TSEC_FALCON_PTIMER1]]
 
| 0x54501030
 
| 0x54501030
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_WDTMRVAL
+
| [[#TSEC_FALCON_WDTMRVAL|TSEC_FALCON_WDTMRVAL]]
 
| 0x54501034
 
| 0x54501034
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_WDTMRCTL
+
| [[#TSEC_FALCON_WDTMRCTL|TSEC_FALCON_WDTMRCTL]]
 
| 0x54501038
 
| 0x54501038
 
| 0x04
 
| 0x04
Line 183: Line 183:  
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_CURCTX
+
| [[#TSEC_FALCON_CURCTX|TSEC_FALCON_CURCTX]]
 
| 0x54501050
 
| 0x54501050
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_NXTCTX
+
| [[#TSEC_FALCON_NXTCTX|TSEC_FALCON_NXTCTX]]
 
| 0x54501054
 
| 0x54501054
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_CTXACK
+
| [[#TSEC_FALCON_CTXACK|TSEC_FALCON_CTXACK]]
 
| 0x54501058
 
| 0x54501058
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_FHSTATE
+
| [[#TSEC_FALCON_FHSTATE|TSEC_FALCON_FHSTATE]]
 
| 0x5450105C
 
| 0x5450105C
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_PRIVSTATE
+
| [[#TSEC_FALCON_PRIVSTATE|TSEC_FALCON_PRIVSTATE]]
 
| 0x54501060
 
| 0x54501060
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_MTHDDATA
+
| [[#TSEC_FALCON_MTHDDATA|TSEC_FALCON_MTHDDATA]]
 
| 0x54501064
 
| 0x54501064
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_MTHDID
+
| [[#TSEC_FALCON_MTHDID|TSEC_FALCON_MTHDID]]
 
| 0x54501068
 
| 0x54501068
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_MTHDWDAT
+
| [[#TSEC_FALCON_MTHDWDAT|TSEC_FALCON_MTHDWDAT]]
 
| 0x5450106C
 
| 0x5450106C
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_MTHDCOUNT
+
| [[#TSEC_FALCON_MTHDCOUNT|TSEC_FALCON_MTHDCOUNT]]
 
| 0x54501070
 
| 0x54501070
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_MTHDPOP
+
| [[#TSEC_FALCON_MTHDPOP|TSEC_FALCON_MTHDPOP]]
 
| 0x54501074
 
| 0x54501074
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_MTHDRAMSZ
+
| [[#TSEC_FALCON_MTHDRAMSZ|TSEC_FALCON_MTHDRAMSZ]]
 
| 0x54501078
 
| 0x54501078
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_SFTRESET
+
| [[#TSEC_FALCON_SFTRESET|TSEC_FALCON_SFTRESET]]
 
| 0x5450107C
 
| 0x5450107C
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_OS
+
| [[#TSEC_FALCON_OS|TSEC_FALCON_OS]]
 
| 0x54501080
 
| 0x54501080
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_RM
+
| [[#TSEC_FALCON_RM|TSEC_FALCON_RM]]
 
| 0x54501084
 
| 0x54501084
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_SOFT_PM
+
| [[#TSEC_FALCON_SOFT_PM|TSEC_FALCON_SOFT_PM]]
 
| 0x54501088
 
| 0x54501088
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_SOFT_MODE
+
| [[#TSEC_FALCON_SOFT_MODE|TSEC_FALCON_SOFT_MODE]]
 
| 0x5450108C
 
| 0x5450108C
 
| 0x04
 
| 0x04
Line 255: Line 255:  
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IBRKPT1
+
| [[#TSEC_FALCON_IBRKPT1|TSEC_FALCON_IBRKPT1]]
 
| 0x54501098
 
| 0x54501098
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IBRKPT2
+
| [[#TSEC_FALCON_IBRKPT2|TSEC_FALCON_IBRKPT2]]
 
| 0x5450109C
 
| 0x5450109C
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_CGCTL
+
| [[#TSEC_FALCON_CGCTL|TSEC_FALCON_CGCTL]]
 
| 0x545010A0
 
| 0x545010A0
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_ENGCTL
+
| [[#TSEC_FALCON_ENGCTL|TSEC_FALCON_ENGCTL]]
 
| 0x545010A4
 
| 0x545010A4
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_PMM
+
| [[#TSEC_FALCON_PMM|TSEC_FALCON_PMM]]
 
| 0x545010A8
 
| 0x545010A8
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_ADDR
+
| [[#TSEC_FALCON_ADDR|TSEC_FALCON_ADDR]]
 
| 0x545010AC
 
| 0x545010AC
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IBRKPT3
+
| [[#TSEC_FALCON_IBRKPT3|TSEC_FALCON_IBRKPT3]]
 
| 0x545010B0
 
| 0x545010B0
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IBRKPT4
+
| [[#TSEC_FALCON_IBRKPT4|TSEC_FALCON_IBRKPT4]]
 
| 0x545010B4
 
| 0x545010B4
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IBRKPT5
+
| [[#TSEC_FALCON_IBRKPT5|TSEC_FALCON_IBRKPT5]]
 
| 0x545010B8
 
| 0x545010B8
 
| 0x04
 
| 0x04
Line 349: Line 349:  
| [[#TSEC_FALCON_DMAPOLL_CP|TSEC_FALCON_DMAPOLL_CP]]
 
| [[#TSEC_FALCON_DMAPOLL_CP|TSEC_FALCON_DMAPOLL_CP]]
 
| 0x54501124
 
| 0x54501124
| 0x04
  −
|-
  −
| TSEC_FALCON_DBG_STATE
  −
| 0x54501128
   
| 0x04
 
| 0x04
 
|-
 
|-
Line 359: Line 355:  
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_CPUCTL_ALIAS
+
| [[#TSEC_FALCON_CPUCTL_ALIAS|TSEC_FALCON_CPUCTL_ALIAS]]
 
| 0x54501130
 
| 0x54501130
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_STACKCFG
+
| [[#TSEC_FALCON_STACKCFG|TSEC_FALCON_STACKCFG]]
 
| 0x54501138
 
| 0x54501138
 
| 0x04
 
| 0x04
Line 383: Line 379:  
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IMFILLRNG0
+
| [[#TSEC_FALCON_IMFILLRNG0|TSEC_FALCON_IMFILLRNG0]]
 
| 0x54501150
 
| 0x54501150
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IMFILLRNG1
+
| [[#TSEC_FALCON_IMFILLRNG1|TSEC_FALCON_IMFILLRNG1]]
 
| 0x54501154
 
| 0x54501154
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IMFILLCTL
+
| [[#TSEC_FALCON_IMFILLCTL|TSEC_FALCON_IMFILLCTL]]
 
| 0x54501158
 
| 0x54501158
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IMCTL_DEBUG
+
| [[#TSEC_FALCON_IMCTL_DEBUG|TSEC_FALCON_IMCTL_DEBUG]]
 
| 0x5450115C
 
| 0x5450115C
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_CMEMBASE
+
| [[#TSEC_FALCON_CMEMBASE|TSEC_FALCON_CMEMBASE]]
 
| 0x54501160
 
| 0x54501160
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMEMAPERT
+
| [[#TSEC_FALCON_DMEMAPERT|TSEC_FALCON_DMEMAPERT]]
 
| 0x54501164
 
| 0x54501164
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_EXTERRADDR
+
| [[#TSEC_FALCON_EXTERRADDR|TSEC_FALCON_EXTERRADDR]]
 
| 0x54501168
 
| 0x54501168
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_EXTERRSTAT
+
| [[#TSEC_FALCON_EXTERRSTAT|TSEC_FALCON_EXTERRSTAT]]
 
| 0x5450116C
 
| 0x5450116C
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_CG2
+
| [[#TSEC_FALCON_CG2|TSEC_FALCON_CG2]]
 
| 0x5450117C
 
| 0x5450117C
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_FALCON_IMEMC0|TSEC_FALCON_IMEMC0]]
+
| [[#TSEC_FALCON_IMEMC|TSEC_FALCON_IMEMC0]]
 
| 0x54501180
 
| 0x54501180
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_FALCON_IMEMD0|TSEC_FALCON_IMEMD0]]
+
| [[#TSEC_FALCON_IMEMD|TSEC_FALCON_IMEMD0]]
 
| 0x54501184
 
| 0x54501184
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_FALCON_IMEMT0|TSEC_FALCON_IMEMT0]]
+
| [[#TSEC_FALCON_IMEMT|TSEC_FALCON_IMEMT0]]
 
| 0x54501188
 
| 0x54501188
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IMEMC1
+
| [[#TSEC_FALCON_IMEMC|TSEC_FALCON_IMEMC1]]
 
| 0x54501190
 
| 0x54501190
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IMEMD1
+
| [[#TSEC_FALCON_IMEMD|TSEC_FALCON_IMEMD1]]
 
| 0x54501194
 
| 0x54501194
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IMEMT1
+
| [[#TSEC_FALCON_IMEMT|TSEC_FALCON_IMEMT1]]
 
| 0x54501198
 
| 0x54501198
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IMEMC2
+
| [[#TSEC_FALCON_IMEMC|TSEC_FALCON_IMEMC2]]
 
| 0x545011A0
 
| 0x545011A0
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IMEMD2
+
| [[#TSEC_FALCON_IMEMD|TSEC_FALCON_IMEMD2]]
 
| 0x545011A4
 
| 0x545011A4
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IMEMT2
+
| [[#TSEC_FALCON_IMEMT|TSEC_FALCON_IMEMT2]]
 
| 0x545011A8
 
| 0x545011A8
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IMEMC3
+
| [[#TSEC_FALCON_IMEMC|TSEC_FALCON_IMEMC3]]
 
| 0x545011B0
 
| 0x545011B0
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IMEMD3
+
| [[#TSEC_FALCON_IMEMD|TSEC_FALCON_IMEMD3]]
 
| 0x545011B4
 
| 0x545011B4
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_IMEMT3
+
| [[#TSEC_FALCON_IMEMT|TSEC_FALCON_IMEMT3]]
 
| 0x545011B8
 
| 0x545011B8
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_FALCON_DMEMC0|TSEC_FALCON_DMEMC0]]
+
| [[#TSEC_FALCON_DMEMC|TSEC_FALCON_DMEMC0]]
 
| 0x545011C0
 
| 0x545011C0
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_FALCON_DMEMD0|TSEC_FALCON_DMEMD0]]
+
| [[#TSEC_FALCON_DMEMD|TSEC_FALCON_DMEMD0]]
 
| 0x545011C4
 
| 0x545011C4
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMEMC1
+
| [[#TSEC_FALCON_DMEMC|TSEC_FALCON_DMEMC1]]
 
| 0x545011C8
 
| 0x545011C8
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMEMD1
+
| [[#TSEC_FALCON_DMEMD|TSEC_FALCON_DMEMD1]]
 
| 0x545011CC
 
| 0x545011CC
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMEMC2
+
| [[#TSEC_FALCON_DMEMC|TSEC_FALCON_DMEMC2]]
 
| 0x545011D0
 
| 0x545011D0
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMEMD2
+
| [[#TSEC_FALCON_DMEMD|TSEC_FALCON_DMEMD2]]
 
| 0x545011D4
 
| 0x545011D4
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMEMC3
+
| [[#TSEC_FALCON_DMEMC|TSEC_FALCON_DMEMC3]]
 
| 0x545011D8
 
| 0x545011D8
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMEMD3
+
| [[#TSEC_FALCON_DMEMD|TSEC_FALCON_DMEMD3]]
 
| 0x545011DC
 
| 0x545011DC
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMEMC4
+
| [[#TSEC_FALCON_DMEMC|TSEC_FALCON_DMEMC4]]
 
| 0x545011E0
 
| 0x545011E0
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMEMD4
+
| [[#TSEC_FALCON_DMEMD|TSEC_FALCON_DMEMD4]]
 
| 0x545011E4
 
| 0x545011E4
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMEMC5
+
| [[#TSEC_FALCON_DMEMC|TSEC_FALCON_DMEMC5]]
 
| 0x545011E8
 
| 0x545011E8
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMEMD5
+
| [[#TSEC_FALCON_DMEMD|TSEC_FALCON_DMEMD5]]
 
| 0x545011EC
 
| 0x545011EC
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMEMC6
+
| [[#TSEC_FALCON_DMEMC|TSEC_FALCON_DMEMC6]]
 
| 0x545011F0
 
| 0x545011F0
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMEMD6
+
| [[#TSEC_FALCON_DMEMD|TSEC_FALCON_DMEMD6]]
 
| 0x545011F4
 
| 0x545011F4
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMEMC7
+
| [[#TSEC_FALCON_DMEMC|TSEC_FALCON_DMEMC7]]
 
| 0x545011F8
 
| 0x545011F8
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMEMD7
+
| [[#TSEC_FALCON_DMEMD|TSEC_FALCON_DMEMD7]]
 
| 0x545011FC
 
| 0x545011FC
 
| 0x04
 
| 0x04
Line 595: Line 591:  
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW
+
| [[#TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW|TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW]]
 
| 0x545012C0
 
| 0x545012C0
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH
+
| [[#TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH|TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH]]
 
| 0x545012C4
 
| 0x545012C4
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW
+
| [[#TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW|TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW]]
 
| 0x545012C8
 
| 0x545012C8
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH
+
| [[#TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH|TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH]]
 
| 0x545012CC
 
| 0x545012CC
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW
+
| [[#TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW|TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW]]
 
| 0x545012D0
 
| 0x545012D0
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH
+
| [[#TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH|TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH]]
 
| 0x545012D4
 
| 0x545012D4
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW
+
| [[#TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW|TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW]]
 
| 0x545012D8
 
| 0x545012D8
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH
+
| [[#TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH|TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH]]
 
| 0x545012DC
 
| 0x545012DC
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_FALCON_DMAINFO_CTL
+
| [[#TSEC_FALCON_DMAINFO_CTL|TSEC_FALCON_DMAINFO_CTL]]
 
| 0x545012E0
 
| 0x545012E0
 
| 0x04
 
| 0x04
Line 783: Line 779:  
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TFBIF_DBG_STAT1
+
| [[#TSEC_TFBIF_DBG_STAT1|TSEC_TFBIF_DBG_STAT1]]
 
| 0x54501610
 
| 0x54501610
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TFBIF_DBG_RDCOUNT_LO
+
| [[#TSEC_TFBIF_DBG_RDCOUNT_LO|TSEC_TFBIF_DBG_RDCOUNT_LO]]
 
| 0x54501614
 
| 0x54501614
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TFBIF_DBG_RDCOUNT_HI
+
| [[#TSEC_TFBIF_DBG_RDCOUNT_HI|TSEC_TFBIF_DBG_RDCOUNT_HI]]
 
| 0x54501618
 
| 0x54501618
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TFBIF_DBG_WRCOUNT_LO
+
| [[#TSEC_TFBIF_DBG_WRCOUNT_LO|TSEC_TFBIF_DBG_WRCOUNT_LO]]
 
| 0x5450161C
 
| 0x5450161C
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TFBIF_DBG_WRCOUNT_HI
+
| [[#TSEC_TFBIF_DBG_WRCOUNT_HI|TSEC_TFBIF_DBG_WRCOUNT_HI]]
 
| 0x54501620
 
| 0x54501620
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TFBIF_DBG_R32COUNT
+
| [[#TSEC_TFBIF_DBG_R32COUNT|TSEC_TFBIF_DBG_R32COUNT]]
 
| 0x54501624
 
| 0x54501624
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TFBIF_DBG_R64COUNT
+
| [[#TSEC_TFBIF_DBG_R64COUNT|TSEC_TFBIF_DBG_R64COUNT]]
 
| 0x54501628
 
| 0x54501628
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TFBIF_DBG_R128COUNT
+
| [[#TSEC_TFBIF_DBG_R128COUNT|TSEC_TFBIF_DBG_R128COUNT]]
 
| 0x5450162C
 
| 0x5450162C
 
| 0x04
 
| 0x04
Line 823: Line 819:  
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TFBIF_WRR_RDP
+
| [[#TSEC_TFBIF_WRR_RDP|TSEC_TFBIF_WRR_RDP]]
 
| 0x54501638
 
| 0x54501638
 
| 0x04
 
| 0x04
Line 851: Line 847:  
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TFBIF_ACTMON_MCB_MASK
+
| [[#TSEC_TFBIF_ACTMON_MCB_MASK|TSEC_TFBIF_ACTMON_MCB_MASK]]
 
| 0x54501660
 
| 0x54501660
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TFBIF_ACTMON_MCB_BORPS
+
| [[#TSEC_TFBIF_ACTMON_MCB_BORPS|TSEC_TFBIF_ACTMON_MCB_BORPS]]
 
| 0x54501664
 
| 0x54501664
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TFBIF_ACTMON_MCB_WEIGHT
+
| [[#TSEC_TFBIF_ACTMON_MCB_WEIGHT|TSEC_TFBIF_ACTMON_MCB_WEIGHT]]
 
| 0x54501668
 
| 0x54501668
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TFBIF_THI_TRANSPROP
+
| [[#TSEC_TFBIF_THI_TRANSPROP|TSEC_TFBIF_THI_TRANSPROP]]
 
| 0x54501670
 
| 0x54501670
 
| 0x04
 
| 0x04
Line 887: Line 883:  
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TEGRA_FALCON_IP_VER
+
| TSEC_TEGRA_UNK_00
 
| 0x54501800
 
| 0x54501800
 
| 0x04
 
| 0x04
Line 948: Line 944:  
|}
 
|}
   −
=== TSEC_THI_METHOD0 ===
+
=== TSEC_THI_INCR_SYNCPT ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-11
+
| 0-9
| TSEC_THI_METHOD0_OFFSET
+
| TSEC_THI_INCR_SYNCPT_INDX
 +
|-
 +
| 10-17
 +
| TSEC_THI_INCR_SYNCPT_COND
 
|}
 
|}
   −
Used to encode and send a method's ID over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
+
=== TSEC_THI_INCR_SYNCPT_CTRL ===
 
  −
The following methods are available:
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
ID
+
Bits
Method
+
Description
 
|-
 
|-
| 0x100
+
| 0
| NOP
+
| TSEC_THI_INCR_SYNCPT_CTRL_SOFT_RESET
 
|-
 
|-
| 0x140
+
| 8
| PM_TRIGGER
+
| TSEC_THI_INCR_SYNCPT_CTRL_NO_STALL
 
|-
 
|-
| 0x200
+
| 16
| SET_APPLICATION_ID
+
| TSEC_THI_INCR_SYNCPT_CTRL_SOFT_RESET_0
 
|-
 
|-
| 0x204
+
| 17
| SET_WATCHDOG_TIMER
+
| TSEC_THI_INCR_SYNCPT_CTRL_NO_STALL_0
 
|-
 
|-
| 0x240
+
| 18
| SEMAPHORE_A
+
| TSEC_THI_INCR_SYNCPT_CTRL_SOFT_RESET_1
 
|-
 
|-
| 0x244
+
| 19
| SEMAPHORE_B
+
| TSEC_THI_INCR_SYNCPT_CTRL_NO_STALL_1
 
|-
 
|-
| 0x248
+
| 20
| SEMAPHORE_C
+
| TSEC_THI_INCR_SYNCPT_CTRL_SOFT_RESET_2
 
|-
 
|-
| 0x24C
+
| 21
|  
+
| TSEC_THI_INCR_SYNCPT_CTRL_NO_STALL_2
 
|-
 
|-
| 0x250
+
| 22
|  
+
| TSEC_THI_INCR_SYNCPT_CTRL_SOFT_RESET_3
 
|-
 
|-
| 0x300
+
| 23
| EXECUTE
+
| TSEC_THI_INCR_SYNCPT_CTRL_NO_STALL_3
 
|-
 
|-
| 0x304
+
| 24
| SEMAPHORE_D
+
| TSEC_THI_INCR_SYNCPT_CTRL_SOFT_RESET_4
 
|-
 
|-
| 0x500
+
| 25
| HDCP_INIT
+
| TSEC_THI_INCR_SYNCPT_CTRL_NO_STALL_4
 +
|}
 +
 
 +
=== TSEC_THI_INCR_SYNCPT_ERR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x504
+
| 0
| HDCP_CREATE_SESSION
+
| TSEC_THI_INCR_SYNCPT_ERR_COND_STS_IMM
 
|-
 
|-
| 0x508
+
| 1
| HDCP_VERIFY_CERT_RX
+
| TSEC_THI_INCR_SYNCPT_ERR_COND_STS_OPDONE
 
|-
 
|-
| 0x50C
+
| 2
| HDCP_GENERATE_EKM
+
| TSEC_THI_INCR_SYNCPT_ERR_COND_STS_RD_DONE
 
|-
 
|-
| 0x510
+
| 3
| HDCP_REVOCATION_CHECK
+
| TSEC_THI_INCR_SYNCPT_ERR_COND_STS_REG_WR_SAFE
 
|-
 
|-
| 0x514
+
| 4
| HDCP_VERIFY_HPRIME
+
| TSEC_THI_INCR_SYNCPT_ERR_COND_STS_ENGINE_IDLE
 +
|}
 +
 
 +
=== TSEC_THI_CTXSW_INCR_SYNCPT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x518
+
| 0-9
| HDCP_ENCRYPT_PAIRING_INFO
+
| TSEC_THI_CTXSW_INCR_SYNCPT_INDX
|-
+
|}
| 0x51C
+
 
| HDCP_DECRYPT_PAIRING_INFO
+
=== TSEC_THI_CTXSW ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x520
+
| 0-9
| HDCP_UPDATE_SESSION
+
| TSEC_THI_CTXSW_CURR_CLASS
 
|-
 
|-
| 0x524
+
| 10
| HDCP_GENERATE_LC_INIT
+
| TSEC_THI_CTXSW_AUTO_ACK
 
|-
 
|-
| 0x528
+
| 11-20
| HDCP_VERIFY_LPRIME
+
| TSEC_THI_CTXSW_CURR_CHANNEL
 +
|}
 +
 
 +
=== TSEC_THI_CTXSW_NEXT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x52C
+
| 0-9
| HDCP_GENERATE_SKE_INIT
+
| TSEC_THI_CTXSW_NEXT_NEXT_CLASS
 
|-
 
|-
| 0x530
+
| 10-19
| HDCP_VERIFY_VPRIME
+
| TSEC_THI_CTXSW_NEXT_NEXT_CHANNEL
 +
|}
 +
 
 +
=== TSEC_THI_CONT_SYNCPT_EOF ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x534
+
| 0-9
| HDCP_ENCRYPTION_RUN_CTRL
+
| TSEC_THI_CONT_SYNCPT_EOF_INDEX
 
|-
 
|-
| 0x538
+
| 10
| HDCP_SESSION_CTRL
+
| TSEC_THI_CONT_SYNCPT_EOF_COND
 +
|}
 +
 
 +
=== TSEC_THI_CONT_SYNCPT_L1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x53C
+
| 0-9
| HDCP_COMPUTE_SPRIME
+
| TSEC_THI_CONT_SYNCPT_L1_INDEX
 
|-
 
|-
| 0x540
+
| 10
| HDCP_GET_CERT_RX
+
| TSEC_THI_CONT_SYNCPT_L1_COND
 +
|}
 +
 
 +
=== TSEC_THI_STREAMID0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x544
+
| 0-6
| HDCP_EXCHANGE_INFO
+
| TSEC_THI_STREAMID0_ID
 +
|}
 +
 
 +
=== TSEC_THI_STREAMID1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x548
+
| 0-6
| HDCP_DECRYPT_KM
+
| TSEC_THI_STREAMID1_ID
 +
|}
 +
 
 +
=== TSEC_THI_THI_SEC ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x54C
+
| 0
| HDCP_GET_HPRIME
+
| TSEC_THI_THI_SEC_TZ_LOCK
 
|-
 
|-
| 0x550
+
| 4
| HDCP_GENERATE_EKH_KM
+
| TSEC_THI_THI_SEC_TZ_AUTH
 
|-
 
|-
| 0x554
+
| 8
| HDCP_VERIFY_RTT_CHALLENGE
+
| TSEC_THI_THI_SEC_CH_LOCK
 +
|}
 +
 
 +
=== TSEC_THI_METHOD0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x558
+
| 0-11
| HDCP_GET_LPRIME
+
| TSEC_THI_METHOD0_OFFSET
|-
+
|}
| 0x55C
+
 
| HDCP_DECRYPT_KS
+
Used to encode and send a method's ID over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
 +
 
 +
The following methods are available:
 +
{| class="wikitable" border="1"
 +
!  ID
 +
!  Method
 +
|-
 +
| 0x100
 +
| NOP
 
|-
 
|-
| 0x560
+
| 0x140
| HDCP_DECRYPT
+
| PM_TRIGGER
 
|-
 
|-
| 0x564
+
| 0x200
| HDCP_GET_RRX
+
| SET_APPLICATION_ID
 
|-
 
|-
| 0x568
+
| 0x204
| HDCP_DECRYPT_REENCRYPT
+
| SET_WATCHDOG_TIMER
 
|-
 
|-
| 0x56C
+
| 0x240
|  
+
| SEMAPHORE_A
 
|-
 
|-
| 0x570
+
| 0x244
|  
+
| SEMAPHORE_B
 
|-
 
|-
| 0x574
+
| 0x248
| HDCP_DECRYPT_STORED_KM
+
| SEMAPHORE_C
 
|-
 
|-
| 0x578
+
| 0x24C
 
|  
 
|  
 
|-
 
|-
| 0x57C
+
| 0x250
 
|  
 
|  
 
|-
 
|-
| 0x700
+
| 0x300
| HDCP_VALIDATE_SRM
+
| EXECUTE
 
|-
 
|-
| 0x704
+
| 0x304
| HDCP_VALIDATE_STREAM
+
| SEMAPHORE_D
 
|-
 
|-
| 0x708
+
| 0x500
| HDCP_TEST_SECURE_STATUS
+
| HDCP_INIT
 
|-
 
|-
| 0x70C
+
| 0x504
| HDCP_SET_DCP_KPUB
+
| HDCP_CREATE_SESSION
 
|-
 
|-
| 0x710
+
| 0x508
| HDCP_SET_RX_KPUB
+
| HDCP_VERIFY_CERT_RX
 
|-
 
|-
| 0x714
+
| 0x50C
| HDCP_SET_CERT_RX
+
| HDCP_GENERATE_EKM
 
|-
 
|-
| 0x718
+
| 0x510
| HDCP_SET_SCRATCH_BUFFER
+
| HDCP_REVOCATION_CHECK
 
|-
 
|-
| 0x71C
+
| 0x514
| HDCP_SET_SRM
+
| HDCP_VERIFY_HPRIME
 
|-
 
|-
| 0x720
+
| 0x518
| HDCP_SET_RECEIVER_ID_LIST
+
| HDCP_ENCRYPT_PAIRING_INFO
 
|-
 
|-
| 0x724
+
| 0x51C
| HDCP_SET_SPRIME
+
| HDCP_DECRYPT_PAIRING_INFO
 
|-
 
|-
| 0x728
+
| 0x520
| HDCP_SET_ENC_INPUT_BUFFER
+
| HDCP_UPDATE_SESSION
 
|-
 
|-
| 0x72C
+
| 0x524
| HDCP_SET_ENC_OUTPUT_BUFFER
+
| HDCP_GENERATE_LC_INIT
 
|-
 
|-
| 0x730
+
| 0x528
| HDCP_GET_RTT_CHALLENGE
+
| HDCP_VERIFY_LPRIME
 
|-
 
|-
| 0x734
+
| 0x52C
| HDCP_STREAM_MANAGE
+
| HDCP_GENERATE_SKE_INIT
 
|-
 
|-
| 0x738
+
| 0x530
| HDCP_READ_CAPS
+
| HDCP_VERIFY_VPRIME
 
|-
 
|-
| 0x73C
+
| 0x534
| HDCP_ENCRYPT
+
| HDCP_ENCRYPTION_RUN_CTRL
 
|-
 
|-
| 0x740
+
| 0x538
| [6.0.0+] HDCP_GET_CURRENT_NONCE
+
| HDCP_SESSION_CTRL
 
|-
 
|-
| 0x1114
+
| 0x53C
| PM_TRIGGER_END
+
| HDCP_COMPUTE_SPRIME
|}
  −
 
  −
=== TSEC_THI_METHOD1 ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
| 0-31
+
| 0x540
| TSEC_THI_METHOD1_DATA
+
| HDCP_GET_CERT_RX
|}
  −
 
  −
Used to encode and send a method's data over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
  −
 
  −
=== TSEC_THI_INT_STATUS ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
| 0
+
| 0x544
| TSEC_THI_INT_STATUS_FALCON_INT
+
| HDCP_EXCHANGE_INFO
|}
  −
 
  −
=== TSEC_THI_INT_MASK ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
| 0
+
| 0x548
| TSEC_THI_INT_MASK_FALCON_INT
+
| HDCP_DECRYPT_KM
|}
  −
 
  −
=== TSEC_FALCON_IRQSSET ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
| 0
+
| 0x54C
| TSEC_FALCON_IRQSSET_GPTMR
+
| HDCP_GET_HPRIME
 
|-
 
|-
| 1
+
| 0x550
| TSEC_FALCON_IRQSSET_WDTMR
+
| HDCP_GENERATE_EKH_KM
 
|-
 
|-
| 2
+
| 0x554
| TSEC_FALCON_IRQSSET_MTHD
+
| HDCP_VERIFY_RTT_CHALLENGE
 
|-
 
|-
| 3
+
| 0x558
| TSEC_FALCON_IRQSSET_CTXSW
+
| HDCP_GET_LPRIME
 
|-
 
|-
| 4
+
| 0x55C
| TSEC_FALCON_IRQSSET_HALT
+
| HDCP_DECRYPT_KS
 
|-
 
|-
| 5
+
| 0x560
| TSEC_FALCON_IRQSSET_EXTERR
+
| HDCP_DECRYPT
 
|-
 
|-
| 6
+
| 0x564
| TSEC_FALCON_IRQSSET_SWGEN0
+
| HDCP_GET_RRX
 
|-
 
|-
| 7
+
| 0x568
| TSEC_FALCON_IRQSSET_SWGEN1
+
| HDCP_DECRYPT_REENCRYPT
 
|-
 
|-
| 8-15
+
| 0x56C
| TSEC_FALCON_IRQSSET_EXT
+
|  
 
|-
 
|-
| 16
+
| 0x570
| TSEC_FALCON_IRQSSET_DMA
+
|  
|}
  −
 
  −
Used for setting Falcon's IRQs.
  −
 
  −
=== TSEC_FALCON_IRQSCLR ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
| 0
+
| 0x574
| TSEC_FALCON_IRQSCLR_GPTMR
+
| HDCP_DECRYPT_STORED_KM
 +
|-
 +
| 0x578
 +
|  
 
|-
 
|-
| 1
+
| 0x57C
| TSEC_FALCON_IRQSCLR_WDTMR
+
|  
 
|-
 
|-
| 2
+
| 0x700
| TSEC_FALCON_IRQSCLR_MTHD
+
| HDCP_VALIDATE_SRM
 
|-
 
|-
| 3
+
| 0x704
| TSEC_FALCON_IRQSCLR_CTXSW
+
| HDCP_VALIDATE_STREAM
 
|-
 
|-
| 4
+
| 0x708
| TSEC_FALCON_IRQSCLR_HALT
+
| HDCP_TEST_SECURE_STATUS
 
|-
 
|-
| 5
+
| 0x70C
| TSEC_FALCON_IRQSCLR_EXTERR
+
| HDCP_SET_DCP_KPUB
 
|-
 
|-
| 6
+
| 0x710
| TSEC_FALCON_IRQSCLR_SWGEN0
+
| HDCP_SET_RX_KPUB
 
|-
 
|-
| 7
+
| 0x714
| TSEC_FALCON_IRQSCLR_SWGEN1
+
| HDCP_SET_CERT_RX
 
|-
 
|-
| 8-15
+
| 0x718
| TSEC_FALCON_IRQSCLR_EXT
+
| HDCP_SET_SCRATCH_BUFFER
 
|-
 
|-
| 16
+
| 0x71C
| TSEC_FALCON_IRQSCLR_DMA
+
| HDCP_SET_SRM
|}
  −
 
  −
Used for clearing Falcon's IRQs.
  −
 
  −
=== TSEC_FALCON_IRQSTAT ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
| 0
+
| 0x720
| TSEC_FALCON_IRQSTAT_GPTMR
+
| HDCP_SET_RECEIVER_ID_LIST
 
|-
 
|-
| 1
+
| 0x724
| TSEC_FALCON_IRQSTAT_WDTMR
+
| HDCP_SET_SPRIME
 
|-
 
|-
| 2
+
| 0x728
| TSEC_FALCON_IRQSTAT_MTHD
+
| HDCP_SET_ENC_INPUT_BUFFER
 
|-
 
|-
| 3
+
| 0x72C
| TSEC_FALCON_IRQSTAT_CTXSW
+
| HDCP_SET_ENC_OUTPUT_BUFFER
 
|-
 
|-
| 4
+
| 0x730
| TSEC_FALCON_IRQSTAT_HALT
+
| HDCP_GET_RTT_CHALLENGE
 
|-
 
|-
| 5
+
| 0x734
| TSEC_FALCON_IRQSTAT_EXTERR
+
| HDCP_STREAM_MANAGE
 
|-
 
|-
| 6
+
| 0x738
| TSEC_FALCON_IRQSTAT_SWGEN0
+
| HDCP_READ_CAPS
 
|-
 
|-
| 7
+
| 0x73C
| TSEC_FALCON_IRQSTAT_SWGEN1
+
| HDCP_ENCRYPT
 +
|-
 +
| 0x740
 +
| [6.0.0+] HDCP_GET_CURRENT_NONCE
 
|-
 
|-
| 8-15
+
| 0x1114
| TSEC_FALCON_IRQSTAT_EXT
+
| PM_TRIGGER_END
 +
|}
 +
 
 +
=== TSEC_THI_METHOD1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 16
+
| 0-31
| TSEC_FALCON_IRQSTAT_DMA
+
| TSEC_THI_METHOD1_DATA
 
|}
 
|}
   −
Used for getting the status of Falcon's IRQs.
+
Used to encode and send a method's data over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
   −
=== TSEC_FALCON_IRQMODE ===
+
=== TSEC_THI_CONTEXT_SWITCH ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-27
| TSEC_FALCON_IRQMODE_LVL_GPTMR
+
| TSEC_THI_CONTEXT_SWITCH_PTR
 
|-
 
|-
| 1
+
| 30-31
| TSEC_FALCON_IRQMODE_LVL_WDTMR
+
| TSEC_THI_CONTEXT_SWITCH_TARGET
 +
|}
 +
 
 +
=== TSEC_THI_INT_STATUS ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 2
+
| 0
| TSEC_FALCON_IRQMODE_LVL_MTHD
+
| TSEC_THI_INT_STATUS_FALCON_INT
 +
|}
 +
 
 +
=== TSEC_THI_INT_MASK ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_THI_INT_MASK_FALCON_INT
 +
|}
 +
 
 +
=== TSEC_THI_CONFIG0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 3
+
| 0
| TSEC_FALCON_IRQMODE_LVL_CTXSW
+
| TSEC_THI_CONFIG0_RETURN_SYNCPT_ON_ERR
 
|-
 
|-
 
| 4
 
| 4
| TSEC_FALCON_IRQMODE_LVL_HALT
+
| TSEC_THI_CONFIG0_IDLE_SYNCPT_INC_ENG
|-
  −
| 5
  −
| TSEC_FALCON_IRQMODE_LVL_EXTERR
  −
|-
  −
| 6
  −
| TSEC_FALCON_IRQMODE_LVL_SWGEN0
  −
|-
  −
| 7
  −
| TSEC_FALCON_IRQMODE_LVL_SWGEN1
  −
|-
  −
| 8-15
  −
| TSEC_FALCON_IRQMODE_LVL_EXT
  −
|-
  −
| 16
  −
| TSEC_FALCON_IRQMODE_LVL_DMA
   
|}
 
|}
   −
Used for changing the mode Falcon's IRQs. A value of 1 means level triggered while a value of 0 means edge triggered.
+
=== TSEC_THI_DBG_MISC ===
 
  −
=== TSEC_FALCON_IRQMSET ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,335: Line 1,371:  
|-
 
|-
 
| 0
 
| 0
| TSEC_FALCON_IRQMSET_GPTMR
+
| TSEC_THI_DBG_MISC_CLIENT_IDLE_STATUS
 
|-
 
|-
 
| 1
 
| 1
| TSEC_FALCON_IRQMSET_WDTMR
+
| TSEC_THI_DBG_MISC_THI_IDLE_STATUS
 
|-
 
|-
 
| 2
 
| 2
| TSEC_FALCON_IRQMSET_MTHD
+
| TSEC_THI_DBG_MISC_THI_SYNCPT_PENDING_STATUS
 
|-
 
|-
 
| 3
 
| 3
| TSEC_FALCON_IRQMSET_CTXSW
+
| TSEC_THI_DBG_MISC_THI_IDLE_EN
|-
+
|}
| 4
+
 
| TSEC_FALCON_IRQMSET_HALT
+
=== TSEC_THI_SLCG_OVERRIDE_HIGH_A ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 5
+
| 0-7
| TSEC_FALCON_IRQMSET_EXTERR
+
| TSEC_THI_SLCG_OVERRIDE_HIGH_A_REG
 +
|}
 +
 
 +
=== TSEC_THI_SLCG_OVERRIDE_LOW_A ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 6
+
| 0-31
| TSEC_FALCON_IRQMSET_SWGEN0
+
| TSEC_THI_SLCG_OVERRIDE_LOW_A_REG
 +
|}
 +
 
 +
=== TSEC_THI_CLK_OVERRIDE ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 7
+
| 0-31
| TSEC_FALCON_IRQMSET_SWGEN1
+
| TSEC_THI_CLK_OVERRIDE_CYA
|-
  −
| 8-15
  −
| TSEC_FALCON_IRQMSET_EXT
  −
|-
  −
| 16
  −
| TSEC_FALCON_IRQMSET_DMA
   
|}
 
|}
   −
Used for setting the mask for Falcon's IRQs.
+
=== TSEC_FALCON_IRQSSET ===
 
  −
=== TSEC_FALCON_IRQMCLR ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,373: Line 1,416:  
|-
 
|-
 
| 0
 
| 0
| TSEC_FALCON_IRQMCLR_GPTMR
+
| TSEC_FALCON_IRQSSET_GPTMR
 
|-
 
|-
 
| 1
 
| 1
| TSEC_FALCON_IRQMCLR_WDTMR
+
| TSEC_FALCON_IRQSSET_WDTMR
 
|-
 
|-
 
| 2
 
| 2
| TSEC_FALCON_IRQMCLR_MTHD
+
| TSEC_FALCON_IRQSSET_MTHD
 
|-
 
|-
 
| 3
 
| 3
| TSEC_FALCON_IRQMCLR_CTXSW
+
| TSEC_FALCON_IRQSSET_CTXSW
 
|-
 
|-
 
| 4
 
| 4
| TSEC_FALCON_IRQMCLR_HALT
+
| TSEC_FALCON_IRQSSET_HALT
 
|-
 
|-
 
| 5
 
| 5
| TSEC_FALCON_IRQMCLR_EXTERR
+
| TSEC_FALCON_IRQSSET_EXTERR
 
|-
 
|-
 
| 6
 
| 6
| TSEC_FALCON_IRQMCLR_SWGEN0
+
| TSEC_FALCON_IRQSSET_SWGEN0
 
|-
 
|-
 
| 7
 
| 7
| TSEC_FALCON_IRQMCLR_SWGEN1
+
| TSEC_FALCON_IRQSSET_SWGEN1
 
|-
 
|-
 
| 8-15
 
| 8-15
| TSEC_FALCON_IRQMCLR_EXT
+
| TSEC_FALCON_IRQSSET_EXT
 
|-
 
|-
 
| 16
 
| 16
| TSEC_FALCON_IRQMCLR_DMA
+
| TSEC_FALCON_IRQSSET_DMA
 
|}
 
|}
   −
Used for clearing the mask for Falcon's IRQs.
+
Used for setting Falcon's IRQs.
   −
=== TSEC_FALCON_IRQMASK ===
+
=== TSEC_FALCON_IRQSCLR ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,411: Line 1,454:  
|-
 
|-
 
| 0
 
| 0
| TSEC_FALCON_IRQMASK_GPTMR
+
| TSEC_FALCON_IRQSCLR_GPTMR
 
|-
 
|-
 
| 1
 
| 1
| TSEC_FALCON_IRQMASK_WDTMR
+
| TSEC_FALCON_IRQSCLR_WDTMR
 
|-
 
|-
 
| 2
 
| 2
| TSEC_FALCON_IRQMASK_MTHD
+
| TSEC_FALCON_IRQSCLR_MTHD
 
|-
 
|-
 
| 3
 
| 3
| TSEC_FALCON_IRQMASK_CTXSW
+
| TSEC_FALCON_IRQSCLR_CTXSW
 
|-
 
|-
 
| 4
 
| 4
| TSEC_FALCON_IRQMASK_HALT
+
| TSEC_FALCON_IRQSCLR_HALT
 
|-
 
|-
 
| 5
 
| 5
| TSEC_FALCON_IRQMASK_EXTERR
+
| TSEC_FALCON_IRQSCLR_EXTERR
 
|-
 
|-
 
| 6
 
| 6
| TSEC_FALCON_IRQMASK_SWGEN0
+
| TSEC_FALCON_IRQSCLR_SWGEN0
 
|-
 
|-
 
| 7
 
| 7
| TSEC_FALCON_IRQMASK_SWGEN1
+
| TSEC_FALCON_IRQSCLR_SWGEN1
 
|-
 
|-
 
| 8-15
 
| 8-15
| TSEC_FALCON_IRQMASK_EXT
+
| TSEC_FALCON_IRQSCLR_EXT
 
|-
 
|-
 
| 16
 
| 16
| TSEC_FALCON_IRQMASK_DMA
+
| TSEC_FALCON_IRQSCLR_DMA
 
|}
 
|}
   −
Used for getting the value of the mask for Falcon's IRQs.
+
Used for clearing Falcon's IRQs.
   −
=== TSEC_FALCON_IRQDEST ===
+
=== TSEC_FALCON_IRQSTAT ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,449: Line 1,492:  
|-
 
|-
 
| 0
 
| 0
| TSEC_FALCON_IRQDEST_HOST_GPTMR
+
| TSEC_FALCON_IRQSTAT_GPTMR
 
|-
 
|-
 
| 1
 
| 1
| TSEC_FALCON_IRQDEST_HOST_WDTMR
+
| TSEC_FALCON_IRQSTAT_WDTMR
 
|-
 
|-
 
| 2
 
| 2
| TSEC_FALCON_IRQDEST_HOST_MTHD
+
| TSEC_FALCON_IRQSTAT_MTHD
 
|-
 
|-
 
| 3
 
| 3
| TSEC_FALCON_IRQDEST_HOST_CTXSW
+
| TSEC_FALCON_IRQSTAT_CTXSW
 
|-
 
|-
 
| 4
 
| 4
| TSEC_FALCON_IRQDEST_HOST_HALT
+
| TSEC_FALCON_IRQSTAT_HALT
 
|-
 
|-
 
| 5
 
| 5
| TSEC_FALCON_IRQDEST_HOST_EXTERR
+
| TSEC_FALCON_IRQSTAT_EXTERR
 
|-
 
|-
 
| 6
 
| 6
| TSEC_FALCON_IRQDEST_HOST_SWGEN0
+
| TSEC_FALCON_IRQSTAT_SWGEN0
 
|-
 
|-
 
| 7
 
| 7
| TSEC_FALCON_IRQDEST_HOST_SWGEN1
+
| TSEC_FALCON_IRQSTAT_SWGEN1
 
|-
 
|-
 
| 8-15
 
| 8-15
| TSEC_FALCON_IRQDEST_HOST_EXT
+
| TSEC_FALCON_IRQSTAT_EXT
 
|-
 
|-
 
| 16
 
| 16
| TSEC_FALCON_IRQDEST_TARGET_GPTMR
+
| TSEC_FALCON_IRQSTAT_DMA
 +
|}
 +
 
 +
Used for getting the status of Falcon's IRQs.
 +
 
 +
=== TSEC_FALCON_IRQMODE ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 17
+
| 0
| TSEC_FALCON_IRQDEST_TARGET_WDTMR
+
| TSEC_FALCON_IRQMODE_LVL_GPTMR
 
|-
 
|-
| 18
+
| 1
| TSEC_FALCON_IRQDEST_TARGET_MTHD
+
| TSEC_FALCON_IRQMODE_LVL_WDTMR
 
|-
 
|-
| 19
+
| 2
| TSEC_FALCON_IRQDEST_TARGET_CTXSW
+
| TSEC_FALCON_IRQMODE_LVL_MTHD
 
|-
 
|-
| 20
+
| 3
| TSEC_FALCON_IRQDEST_TARGET_HALT
+
| TSEC_FALCON_IRQMODE_LVL_CTXSW
 
|-
 
|-
| 21
+
| 4
| TSEC_FALCON_IRQDEST_TARGET_EXTERR
+
| TSEC_FALCON_IRQMODE_LVL_HALT
 
|-
 
|-
| 22
+
| 5
| TSEC_FALCON_IRQDEST_TARGET_SWGEN0
+
| TSEC_FALCON_IRQMODE_LVL_EXTERR
 
|-
 
|-
| 23
+
| 6
| TSEC_FALCON_IRQDEST_TARGET_SWGEN1
+
| TSEC_FALCON_IRQMODE_LVL_SWGEN0
 
|-
 
|-
| 24-31
+
| 7
| TSEC_FALCON_IRQDEST_TARGET_EXT
+
| TSEC_FALCON_IRQMODE_LVL_SWGEN1
|}
  −
 
  −
Used for routing Falcon's IRQs.
  −
 
  −
=== TSEC_FALCON_IRQDEST2 ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
| 0
+
| 8-15
| TSEC_FALCON_IRQDEST2_HOST_DMA
+
| TSEC_FALCON_IRQMODE_LVL_EXT
 
|-
 
|-
 
| 16
 
| 16
| TSEC_FALCON_IRQDEST2_TARGET_DMA
+
| TSEC_FALCON_IRQMODE_LVL_DMA
 
|}
 
|}
   −
Used for routing Falcon's IRQs.
+
Used for changing the mode Falcon's IRQs. A value of 1 means level triggered while a value of 0 means edge triggered.
   −
=== TSEC_FALCON_MAILBOX0 ===
+
=== TSEC_FALCON_IRQMSET ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-31
+
| 0
| TSEC_FALCON_MAILBOX0_DATA
+
| TSEC_FALCON_IRQMSET_GPTMR
 +
|-
 +
| 1
 +
| TSEC_FALCON_IRQMSET_WDTMR
 +
|-
 +
| 2
 +
| TSEC_FALCON_IRQMSET_MTHD
 +
|-
 +
| 3
 +
| TSEC_FALCON_IRQMSET_CTXSW
 +
|-
 +
| 4
 +
| TSEC_FALCON_IRQMSET_HALT
 +
|-
 +
| 5
 +
| TSEC_FALCON_IRQMSET_EXTERR
 +
|-
 +
| 6
 +
| TSEC_FALCON_IRQMSET_SWGEN0
 +
|-
 +
| 7
 +
| TSEC_FALCON_IRQMSET_SWGEN1
 +
|-
 +
| 8-15
 +
| TSEC_FALCON_IRQMSET_EXT
 +
|-
 +
| 16
 +
| TSEC_FALCON_IRQMSET_DMA
 
|}
 
|}
   −
Scratch register for reading/writing data to Falcon.
+
Used for setting the mask for Falcon's IRQs.
   −
=== TSEC_FALCON_MAILBOX1 ===
+
=== TSEC_FALCON_IRQMCLR ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-31
+
| 0
| TSEC_FALCON_MAILBOX1_DATA
+
| TSEC_FALCON_IRQMCLR_GPTMR
|}
+
|-
 
+
| 1
Scratch register for reading/writing data to Falcon.
+
| TSEC_FALCON_IRQMCLR_WDTMR
 
+
|-
=== TSEC_FALCON_ITFEN ===
+
| 2
{| class="wikitable" border="1"
+
| TSEC_FALCON_IRQMCLR_MTHD
!  Bits
+
|-
!  Description
+
| 3
 +
| TSEC_FALCON_IRQMCLR_CTXSW
 +
|-
 +
| 4
 +
| TSEC_FALCON_IRQMCLR_HALT
 +
|-
 +
| 5
 +
| TSEC_FALCON_IRQMCLR_EXTERR
 +
|-
 +
| 6
 +
| TSEC_FALCON_IRQMCLR_SWGEN0
 +
|-
 +
| 7
 +
| TSEC_FALCON_IRQMCLR_SWGEN1
 
|-
 
|-
| 0
+
| 8-15
| TSEC_FALCON_ITFEN_CTXEN
+
| TSEC_FALCON_IRQMCLR_EXT
 
|-
 
|-
| 1
+
| 16
| TSEC_FALCON_ITFEN_MTHDEN
+
| TSEC_FALCON_IRQMCLR_DMA
 
|}
 
|}
   −
Used for enabling/disabling Falcon interfaces.
+
Used for clearing the mask for Falcon's IRQs.
   −
=== TSEC_FALCON_IDLESTATE ===
+
=== TSEC_FALCON_IRQMASK ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,561: Line 1,644:  
|-
 
|-
 
| 0
 
| 0
| TSEC_FALCON_IDLESTATE_FALCON_BUSY
+
| TSEC_FALCON_IRQMASK_GPTMR
 +
|-
 +
| 1
 +
| TSEC_FALCON_IRQMASK_WDTMR
 +
|-
 +
| 2
 +
| TSEC_FALCON_IRQMASK_MTHD
 +
|-
 +
| 3
 +
| TSEC_FALCON_IRQMASK_CTXSW
 +
|-
 +
| 4
 +
| TSEC_FALCON_IRQMASK_HALT
 +
|-
 +
| 5
 +
| TSEC_FALCON_IRQMASK_EXTERR
 +
|-
 +
| 6
 +
| TSEC_FALCON_IRQMASK_SWGEN0
 +
|-
 +
| 7
 +
| TSEC_FALCON_IRQMASK_SWGEN1
 +
|-
 +
| 8-15
 +
| TSEC_FALCON_IRQMASK_EXT
 
|-
 
|-
| 1-15
+
| 16
| TSEC_FALCON_IDLESTATE_EXT_BUSY
+
| TSEC_FALCON_IRQMASK_DMA
 
|}
 
|}
   −
Used for detecting if Falcon is busy or not.
+
Used for getting the value of the mask for Falcon's IRQs.
   −
=== TSEC_FALCON_DEBUG1 ===
+
=== TSEC_FALCON_IRQDEST ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-15
+
| 0
| TSEC_FALCON_DEBUG1_MTHD_DRAIN_TIME
+
| TSEC_FALCON_IRQDEST_HOST_GPTMR
 
|-
 
|-
| 16
+
| 1
| TSEC_FALCON_DEBUG1_CTXSW_MODE
+
| TSEC_FALCON_IRQDEST_HOST_WDTMR
 +
|-
 +
| 2
 +
| TSEC_FALCON_IRQDEST_HOST_MTHD
 +
|-
 +
| 3
 +
| TSEC_FALCON_IRQDEST_HOST_CTXSW
 
|-
 
|-
| 17
+
| 4
| TSEC_FALCON_DEBUG1_TRACE_FORMAT
+
| TSEC_FALCON_IRQDEST_HOST_HALT
|}
  −
 
  −
=== TSEC_FALCON_DEBUGINFO ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
| 0-31
+
| 5
| TSEC_FALCON_DEBUGINFO_DATA
+
| TSEC_FALCON_IRQDEST_HOST_EXTERR
|}
  −
 
  −
Used for UCODE self revocation. This register takes the base address of the GSC carveout shifted right by 8.
  −
 
  −
[6.0.0+] [[NV_services|nvservices]] sets this to 0x8005FF00 >> 8 (physical DRAM address inside the GPU UCODE carveout) before starting the nvhost_tsec firmware.
  −
 
  −
=== TSEC_FALCON_EXCI ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
| 0-19
+
| 6
| TSEC_FALCON_EXCI_EXPC
+
| TSEC_FALCON_IRQDEST_HOST_SWGEN0
 
|-
 
|-
| 20-23
+
| 7
| TSEC_FALCON_EXCI_EXCAUSE
+
| TSEC_FALCON_IRQDEST_HOST_SWGEN1
0x00: TRAP0
  −
0x01: TRAP1
  −
0x02: TRAP2
  −
0x03: TRAP3
  −
0x08: ILL_INS (invalid opcode)
  −
0x09: INV_INS (authentication entry)
  −
0x0A: MISS_INS (page miss)
  −
0x0B: DHIT_INS (page multiple hit)
  −
0x0F: BRKPT_INS (breakpoint hit)
  −
|}
  −
 
  −
Contains information about raised exceptions.
  −
 
  −
=== TSEC_FALCON_SVEC_SPR ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
| 18
+
| 8-15
| TSEC_FALCON_SVEC_SPR_SIGPASS
+
| TSEC_FALCON_IRQDEST_HOST_EXT
|}
  −
 
  −
=== TSEC_FALCON_RSTAT0 ===
  −
Mirror of the [[#TSEC_FALCON_ICD_RDATA|ICD status register 0]].
  −
 
  −
=== TSEC_FALCON_RSTAT3 ===
  −
Mirror of the [[#TSEC_FALCON_ICD_RDATA|ICD status register 3]].
  −
 
  −
=== TSEC_FALCON_CPUCTL ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
| 0
+
| 16
| TSEC_FALCON_CPUCTL_IINVAL
+
| TSEC_FALCON_IRQDEST_TARGET_GPTMR
 
|-
 
|-
| 1
+
| 17
| TSEC_FALCON_CPUCTL_STARTCPU
+
| TSEC_FALCON_IRQDEST_TARGET_WDTMR
 
|-
 
|-
| 2
+
| 18
| TSEC_FALCON_CPUCTL_SRESET
+
| TSEC_FALCON_IRQDEST_TARGET_MTHD
 +
|-
 +
| 19
 +
| TSEC_FALCON_IRQDEST_TARGET_CTXSW
 +
|-
 +
| 20
 +
| TSEC_FALCON_IRQDEST_TARGET_HALT
 
|-
 
|-
| 3
+
| 21
| TSEC_FALCON_CPUCTL_HRESET
+
| TSEC_FALCON_IRQDEST_TARGET_EXTERR
 
|-
 
|-
| 4
+
| 22
| TSEC_FALCON_CPUCTL_HALTED
+
| TSEC_FALCON_IRQDEST_TARGET_SWGEN0
 
|-
 
|-
| 5
+
| 23
| TSEC_FALCON_CPUCTL_STOPPED
+
| TSEC_FALCON_IRQDEST_TARGET_SWGEN1
 
|-
 
|-
| 6
+
| 24-31
| TSEC_FALCON_CPUCTL_ALIAS_EN
+
| TSEC_FALCON_IRQDEST_TARGET_EXT
 
|}
 
|}
   −
Used for signaling the Falcon CPU.
+
Used for routing Falcon's IRQs.
   −
=== TSEC_FALCON_BOOTVEC ===
+
=== TSEC_FALCON_GPTMRINT ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,670: Line 1,744:  
|-
 
|-
 
| 0-31
 
| 0-31
| TSEC_FALCON_BOOTVEC_VEC
+
| TSEC_FALCON_GPTMRINT_VAL
 
|}
 
|}
   −
Takes the Falcon's boot vector address.
+
=== TSEC_FALCON_GPTMRVAL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_FALCON_GPTMRVAL_VAL
 +
|}
   −
=== TSEC_FALCON_HWCFG ===
+
=== TSEC_FALCON_GPTMRCTL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-8
+
| 0
| TSEC_FALCON_HWCFG_IMEM_SIZE
+
| TSEC_FALCON_GPTMRCTL_GPTMREN
|-
  −
| 9-17
  −
| TSEC_FALCON_HWCFG_DMEM_SIZE
  −
|-
  −
| 18-26
  −
| TSEC_FALCON_HWCFG_METHODFIFO_DEPTH
  −
|-
  −
| 27-31
  −
| TSEC_FALCON_HWCFG_DMAQUEUE_DEPTH
   
|}
 
|}
   −
=== TSEC_FALCON_DMACTL ===
+
=== TSEC_FALCON_PTIMER0 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-31
| TSEC_FALCON_DMACTL_REQUIRE_CTX
+
| TSEC_FALCON_PTIMER0_VAL
|-
  −
| 1
  −
| TSEC_FALCON_DMACTL_DMEM_SCRUBBING
  −
|-
  −
| 2
  −
| TSEC_FALCON_DMACTL_IMEM_SCRUBBING
  −
|-
  −
| 3-6
  −
| TSEC_FALCON_DMACTL_DMAQ_NUM
  −
|-
  −
| 7
  −
| TSEC_FALCON_DMACTL_SECURE_STAT
   
|}
 
|}
   −
Used for configuring the Falcon's DMA engine.
+
=== TSEC_FALCON_PTIMER1 ===
 
  −
=== TSEC_FALCON_DMATRFBASE ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,722: Line 1,780:  
|-
 
|-
 
| 0-31
 
| 0-31
| TSEC_FALCON_DMATRFBASE_BASE
+
| TSEC_FALCON_PTIMER1_VAL
 
|}
 
|}
   −
Base address of the external memory buffer, shifted right by 8.
+
=== TSEC_FALCON_WDTMRVAL ===
 
  −
The current transfer address is calculated by adding [[#TSEC_FALCON_DMATRFFBOFFS|TSEC_FALCON_DMATRFFBOFFS]] to the base.
  −
 
  −
=== TSEC_FALCON_DMATRFMOFFS ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-15
+
| 0-31
| TSEC_FALCON_DMATRFMOFFS_OFFS
+
| TSEC_FALCON_WDTMRVAL_VAL
 
|}
 
|}
   −
For transfers to DMEM: the destination address.
+
=== TSEC_FALCON_WDTMRCTL ===
For transfers to IMEM: the destination virtual IMEM page.
+
{| class="wikitable" border="1"
 
  −
=== TSEC_FALCON_DMATRFCMD ===
  −
{| class="wikitable" border="1"
   
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
 
| 0
 
| 0
| TSEC_FALCON_DMATRFCMD_FULL
+
| TSEC_FALCON_WDTMRCTL_WDTMREN
|-
  −
| 1
  −
| TSEC_FALCON_DMATRFCMD_IDLE
  −
|-
  −
| 2-3
  −
| TSEC_FALCON_DMATRFCMD_SEC
  −
|-
  −
| 4
  −
| TSEC_FALCON_DMATRFCMD_IMEM
  −
|-
  −
| 5
  −
| TSEC_FALCON_DMATRFCMD_WRITE
  −
|-
  −
| 8-10
  −
| TSEC_FALCON_DMATRFCMD_SIZE
  −
|-
  −
| 12-14
  −
| TSEC_FALCON_DMATRFCMD_CTXDMA
   
|}
 
|}
   −
Used for configuring DMA transfers.
+
=== TSEC_FALCON_IRQDEST2 ===
 
  −
=== TSEC_FALCON_DMATRFFBOFFS ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-15
+
| 0
| TSEC_FALCON_DMATRFFBOFFS_OFFS
+
| TSEC_FALCON_IRQDEST2_HOST_DMA
 +
|-
 +
| 16
 +
| TSEC_FALCON_IRQDEST2_TARGET_DMA
 
|}
 
|}
   −
For transfers to IMEM: the destination physical IMEM page.
+
Used for routing Falcon's IRQs.
   −
=== TSEC_FALCON_DMAPOLL_FB ===
+
=== TSEC_FALCON_MAILBOX0 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-31
| TSEC_FALCON_DMAPOLL_FB_FENCE_ACTIVE
+
| TSEC_FALCON_MAILBOX0_DATA
 +
|}
 +
 
 +
Scratch register for reading/writing data to Falcon.
 +
 
 +
=== TSEC_FALCON_MAILBOX1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 1
+
| 0-31
| TSEC_FALCON_DMAPOLL_FB_DMA_ACTIVE
+
| TSEC_FALCON_MAILBOX1_DATA
|-
  −
| 4
  −
| TSEC_FALCON_DMAPOLL_FB_CFG_R_FENCE
  −
|-
  −
| 5
  −
| TSEC_FALCON_DMAPOLL_FB_CFG_W_FENCE
  −
|-
  −
| 16-23
  −
| TSEC_FALCON_DMAPOLL_FB_WCOUNT
  −
|-
  −
| 24-31
  −
| TSEC_FALCON_DMAPOLL_FB_RCOUNT
   
|}
 
|}
   −
Contains the status of a DMA transfer between the Falcon and external memory.
+
Scratch register for reading/writing data to Falcon.
   −
=== TSEC_FALCON_DMAPOLL_CP ===
+
=== TSEC_FALCON_ITFEN ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,813: Line 1,843:  
|-
 
|-
 
| 0
 
| 0
| TSEC_FALCON_DMAPOLL_CP_FENCE_ACTIVE
+
| TSEC_FALCON_ITFEN_CTXEN
 
|-
 
|-
 
| 1
 
| 1
| TSEC_FALCON_DMAPOLL_CP_DMA_ACTIVE
+
| TSEC_FALCON_ITFEN_MTHDEN
|-
+
|}
| 4
+
 
| TSEC_FALCON_DMAPOLL_CP_CFG_R_FENCE
+
Used for enabling/disabling Falcon interfaces.
 +
 
 +
=== TSEC_FALCON_IDLESTATE ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 5
+
| 0
| TSEC_FALCON_DMAPOLL_CP_CFG_W_FENCE
+
| TSEC_FALCON_IDLESTATE_FALCON_BUSY
 
|-
 
|-
| 16-23
+
| 1-15
| TSEC_FALCON_DMAPOLL_CP_WCOUNT
+
| TSEC_FALCON_IDLESTATE_EXT_BUSY
|-
  −
| 24-31
  −
| TSEC_FALCON_DMAPOLL_CP_RCOUNT
   
|}
 
|}
   −
Contains the status of a DMA transfer between the Falcon and the SCP.
+
Used for detecting if Falcon is busy or not.
   −
=== TSEC_FALCON_HWCFG1 ===
+
=== TSEC_FALCON_CURCTX ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-27
| TSEC_FALCON_HWCFG1_CORE_REV
+
| TSEC_FALCON_CURCTX_CTXPTR
 
|-
 
|-
| 4-5
+
| 28-29
| TSEC_FALCON_HWCFG1_SECURITY_MODEL
+
| TSEC_FALCON_CURCTX_CTXTGT
 
|-
 
|-
| 6-7
+
| 30
| TSEC_FALCON_HWCFG1_CORE_REV_SUBVERSION
+
| TSEC_FALCON_CURCTX_CTXVLD
 +
|}
 +
 
 +
=== TSEC_FALCON_NXTCTX ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 8-11
+
| 0-27
| TSEC_FALCON_HWCFG1_IMEM_PORTS
+
| TSEC_FALCON_NXTCTX_CTXPTR
 
|-
 
|-
| 12-15
+
| 28-29
| TSEC_FALCON_HWCFG1_DMEM_PORTS
+
| TSEC_FALCON_NXTCTX_CTXTGT
 
|-
 
|-
| 16-20
+
| 30
| TSEC_FALCON_HWCFG1_TAG_WIDTH
+
| TSEC_FALCON_NXTCTX_CTXVLD
 +
|}
 +
 
 +
=== TSEC_FALCON_CTXACK ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_FALCON_CTXACK_SAVE_ACK
 
|-
 
|-
| 27
+
| 1
| TSEC_FALCON_HWCFG1_DBG_PRIV_BUS
+
| TSEC_FALCON_CTXACK_REST_ACK
 +
|}
 +
 
 +
=== TSEC_FALCON_FHSTATE ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 28
+
| 0
| TSEC_FALCON_HWCFG1_CSB_SIZE_16M
+
| TSEC_FALCON_FHSTATE_FALCON_HALTED
 
|-
 
|-
| 29
+
| 1-15
| TSEC_FALCON_HWCFG1_PRIV_DIRECT
+
| TSEC_FALCON_FHSTATE_EXT_HALTED
 
|-
 
|-
| 30
+
| 16
| TSEC_FALCON_HWCFG1_DMEM_APERTURES
+
| TSEC_FALCON_FHSTATE_ENGINE_FAULTED
 
|-
 
|-
| 31
+
| 17
| TSEC_FALCON_HWCFG1_IMEM_AUTOFILL
+
| TSEC_FALCON_FHSTATE_STALL_REQ
 
|}
 
|}
   −
=== TSEC_FALCON_IMCTL ===
+
=== TSEC_FALCON_PRIVSTATE ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-23
+
| 0
| TSEC_FALCON_IMCTL_ADDR_BLK
+
| TSEC_FALCON_PRIVSTATE_PRIV
|-
  −
| 24-26
  −
| TSEC_FALCON_IMCTL_CMD
  −
0x00: NOP
  −
0x01: IMINV (ITLB)
  −
0x02: IMBLK (PTLB)
  −
0x03: IMTAG (VTLB)
  −
0x04: IMTAG_SETVLD
   
|}
 
|}
   −
Controls the Falcon TLB.
+
=== TSEC_FALCON_MTHDDATA ===
 
  −
=== TSEC_FALCON_IMSTAT ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,897: Line 1,940:  
|-
 
|-
 
| 0-31
 
| 0-31
| TSEC_FALCON_IMSTAT_VAL
+
| TSEC_FALCON_MTHDDATA_DATA
 
|}
 
|}
   −
Returns the result of the last command from [[#TSEC_FALCON_IMCTL|TSEC_FALCON_IMCTL]].
+
=== TSEC_FALCON_MTHDID ===
 
  −
=== TSEC_FALCON_TRACEIDX ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-7
+
| 0-11
| TSEC_FALCON_TRACEIDX_IDX
+
| TSEC_FALCON_MTHDID_ID
 +
|-
 +
| 12-14
 +
| TSEC_FALCON_MTHDID_SUBCH
 
|-
 
|-
| 16-23
+
| 15
| TSEC_FALCON_TRACEIDX_MAXIDX
+
| TSEC_FALCON_MTHDID_PRIV
 
|-
 
|-
| 24-31
+
| 16
| TSEC_FALCON_TRACEIDX_CNT
+
| TSEC_FALCON_MTHDID_WPEND
 
|}
 
|}
   −
Controls the index for tracing with [[#TSEC_FALCON_TRACEPC|TSEC_FALCON_TRACEPC]].
+
=== TSEC_FALCON_MTHDWDAT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_FALCON_MTHDWDAT_DATA
 +
|}
   −
=== TSEC_FALCON_TRACEPC ===
+
=== TSEC_FALCON_MTHDCOUNT ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-23
+
| 0-15
| TSEC_FALCON_TRACEPC_PC
+
| TSEC_FALCON_MTHDCOUNT_COUNT
 
|}
 
|}
   −
Returns the PC of the last call or branch executed.
+
=== TSEC_FALCON_MTHDPOP ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_FALCON_MTHDPOP_POP
 +
|}
   −
=== TSEC_FALCON_IMEMC0 ===
+
=== TSEC_FALCON_MTHDRAMSZ ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 2-7
+
| 0-15
| TSEC_FALCON_IMEMC_OFFS
+
| TSEC_FALCON_MTHDRAMSZ_RAMSZ
|-
+
|}
| 8-15
+
 
| TSEC_FALCON_IMEMC_BLK
+
=== TSEC_FALCON_SFTRESET ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 24
+
| 0
| TSEC_FALCON_IMEMC_AINCW
+
| TSEC_FALCON_SFTRESET_EXT
|-
  −
| 25
  −
| TSEC_FALCON_IMEMC_AINCR
  −
|-
  −
| 28
  −
| TSEC_FALCON_IMEMC_SECURE
  −
|-
  −
| 29
  −
| TSEC_FALCON_IMEMC_SEC_ATOMIC
  −
|-
  −
| 30
  −
| TSEC_FALCON_IMEMC_SEC_WR_VIO
  −
|-
  −
| 31
  −
| TSEC_FALCON_IMEMC_SEC_LOCK
   
|}
 
|}
   −
Used for configuring access to Falcon's IMEM.
+
=== TSEC_FALCON_OS ===
 
  −
=== TSEC_FALCON_IMEMD0 ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,968: Line 2,012:  
|-
 
|-
 
| 0-31
 
| 0-31
| TSEC_FALCON_IMEMD_DATA
+
| TSEC_FALCON_OS_VERSION
 
|}
 
|}
   −
Returns or takes the value for an IMEM read/write operation.
+
=== TSEC_FALCON_RM ===
 
  −
=== TSEC_FALCON_IMEMT0 ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-15
+
| 0-31
| TSEC_FALCON_IMEMT_TAG
+
| TSEC_FALCON_RM_CONFIG
 
|}
 
|}
   −
Returns or takes the virtual page index for an IMEM read/write operation.
+
=== TSEC_FALCON_SOFT_PM ===
 
  −
=== TSEC_FALCON_DMEMC0 ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 2-7
+
| 0-5
| TSEC_FALCON_DMEMC_OFFS
+
| TSEC_FALCON_SOFT_PM_PROBE
 
|-
 
|-
| 8-15
+
| 16
| TSEC_FALCON_DMEMC_BLK
+
| TSEC_FALCON_SOFT_PM_TRIGGER_END
 
|-
 
|-
| 24
+
| 17
| TSEC_FALCON_DMEMC_AINCW
+
| TSEC_FALCON_SOFT_PM_TRIGGER_START
 +
|}
 +
 
 +
=== TSEC_FALCON_SOFT_MODE ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 25
+
| 0-5
| TSEC_FALCON_DMEMC_AINCR
+
| TSEC_FALCON_SOFT_MODE_PROBE
 
|}
 
|}
   −
Used for configuring access to Falcon's DMEM.
+
=== TSEC_FALCON_DEBUG1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-15
 +
| TSEC_FALCON_DEBUG1_MTHD_DRAIN_TIME
 +
|-
 +
| 16
 +
| TSEC_FALCON_DEBUG1_CTXSW_MODE
 +
|-
 +
| 17
 +
| TSEC_FALCON_DEBUG1_TRACE_FORMAT
 +
|}
   −
=== TSEC_FALCON_DMEMD0 ===
+
=== TSEC_FALCON_DEBUGINFO ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 2,010: Line 2,069:  
|-
 
|-
 
| 0-31
 
| 0-31
| TSEC_FALCON_DMEMD_DATA
+
| TSEC_FALCON_DEBUGINFO_DATA
 
|}
 
|}
   −
Returns or takes the value for a DMEM read/write operation.
+
Used for UCODE self revocation. This register takes the base address of the GSC carveout shifted right by 8.
 +
 
 +
[6.0.0+] [[NV_services|nvservices]] sets this to 0x8005FF00 >> 8 (physical DRAM address inside the GPU UCODE carveout) before starting the nvhost_tsec firmware.
   −
=== TSEC_FALCON_ICD_CMD ===
+
=== TSEC_FALCON_IBRKPT1 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-23
| TSEC_FALCON_ICD_CMD_OPC
+
| TSEC_FALCON_IBRKPT1_PC
0x00: STOP
+
|-
0x01: RUN (run from PC)
+
| 29
0x02: JRUN (run from address)
+
| TSEC_FALCON_IBRKPT1_SUPPRESS
0x03: RUNB (run from PC)
+
|-
0x04: JRUNB (run from address)
+
| 30
0x05: STEP (step from PC)
+
| TSEC_FALCON_IBRKPT1_SKIP
0x06: JSTEP (step from address)
+
|-
0x07: EMASK (set exception mask)
+
| 31
0x08: RREG (read register)
+
| TSEC_FALCON_IBRKPT1_EN
0x09: WREG (write register)
+
|}
0x0A: RDM (read data memory)
+
 
0x0B: WDM (write data memory)
+
=== TSEC_FALCON_IBRKPT2 ===
0x0C: RCM (read MMIO/configuration memory)
+
{| class="wikitable" border="1"
0x0D: WCM (write MMIO/configuration memory)
+
! Bits
  0x0E: RSTAT (read status)
+
! Description
  0x0F: SBU
   
|-
 
|-
| 6-7
+
| 0-23
| TSEC_FALCON_ICD_CMD_SZ
+
| TSEC_FALCON_IBRKPT2_PC
0x00: B (byte)
  −
0x01: HW (half word)
  −
0x02: W (word)
   
|-
 
|-
| 8-12
+
| 29
| TSEC_FALCON_ICD_CMD_IDX
+
| TSEC_FALCON_IBRKPT2_SUPPRESS
0x00: REG0 | RSTAT0 | WB0
  −
0x01: REG1 | RSTAT1 | WB1
  −
0x02: REG2 | RSTAT2 | WB2
  −
0x03: REG3 | RSTAT3 | WB3
  −
0x04: REG4 | RSTAT4
  −
0x05: REG5 | RSTAT5
  −
0x06: REG6
  −
0x07: REG7
  −
0x08: REG8
  −
0x09: REG9
  −
0x0A: REG10
  −
0x0B: REG11
  −
0x0C: REG12
  −
0x0D: REG13
  −
0x0E: REG14
  −
0x0F: REG15
  −
0x10: IV0
  −
0x11: IV1
  −
0x12: UNDEFINED
  −
0x13: EV
  −
0x14: SP
  −
0x15: PC
  −
0x16: IMB
  −
0x17: DMB
  −
0x18: CSW
  −
0x19: CCR
  −
0x1A: SEC
  −
0x1B: CTX
  −
0x1C: EXCI
  −
0x1D: SEC1
  −
0x1E: IMB1
  −
0x1F: DMB1
   
|-
 
|-
| 14
+
| 30
| TSEC_FALCON_ICD_CMD_ERROR
+
| TSEC_FALCON_IBRKPT2_SKIP
 
|-
 
|-
| 15
+
| 31
| TSEC_FALCON_ICD_CMD_RDVLD
+
| TSEC_FALCON_IBRKPT2_EN
 +
|}
 +
 
 +
=== TSEC_FALCON_CGCTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 16-31
+
| 0
| TSEC_FALCON_ICD_CMD_PARM
+
| TSEC_FALCON_CGCTL_CG_OVERRIDE
0x0001: EMASK_TRAP0
+
|}
0x0002: EMASK_TRAP1
  −
0x0004: EMASK_TRAP2
  −
0x0008: EMASK_TRAP3
  −
0x0010: EMASK_EXC_UNIMP
  −
0x0020: EMASK_EXC_IMISS
  −
0x0040: EMASK_EXC_IMHIT
  −
0x0080: EMASK_EXC_IBREAK
  −
0x0100: EMASK_IV0
  −
0x0200: EMASK_IV1
  −
0x0400: EMASK_IV2
  −
0x0800: EMASK_EXT0
  −
0x1000: EMASK_EXT1
  −
0x2000: EMASK_EXT2
  −
0x4000: EMASK_EXT3
  −
0x8000: EMASK_EXT4
  −
|}
     −
Used for sending commands to the Falcon's in-chip debugger.
+
=== TSEC_FALCON_ENGCTL ===
 
  −
=== TSEC_FALCON_ICD_ADDR ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-31
+
| 0
| TSEC_FALCON_ICD_ADDR_ADDR
+
| TSEC_FALCON_ENGCTL_INV_CONTEXT
 +
|-
 +
| 1
 +
| TSEC_FALCON_ENGCTL_SET_STALLREQ
 +
|-
 +
| 2
 +
| TSEC_FALCON_ENGCTL_CLR_STALLREQ
 +
|-
 +
| 3
 +
| TSEC_FALCON_ENGCTL_SWITCH_CONTEXT
 +
|-
 +
| 8
 +
| TSEC_FALCON_ENGCTL_STALLREQ
 +
|-
 +
| 9
 +
| TSEC_FALCON_ENGCTL_STALLACK
 
|}
 
|}
   −
Takes the target address for the Falcon's in-chip debugger.
+
=== TSEC_FALCON_PMM ===
 
  −
=== TSEC_FALCON_ICD_WDATA ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-31
+
| 0-4
| TSEC_FALCON_ICD_WDATA_DATA
+
| TSEC_FALCON_PMM_FALCON_STALL_SEL
 +
|-
 +
| 5-7
 +
| TSEC_FALCON_PMM_FALCON_IDLE_SEL
 +
|-
 +
| 8-11
 +
| TSEC_FALCON_PMM_FALCON_SOFTPM0_SEL
 +
|-
 +
| 12-15
 +
| TSEC_FALCON_PMM_FALCON_SOFTPM1_SEL
 +
|-
 +
| 17-19
 +
| TSEC_FALCON_PMM_TFBIF_DSTAT_SEL
 +
|-
 +
| 20-23
 +
| TSEC_FALCON_PMM_TFBIF_STALL0_SEL
 +
|-
 +
| 24-27
 +
| TSEC_FALCON_PMM_TFBIF_STALL1_SEL
 +
|-
 +
| 28-31
 +
| TSEC_FALCON_PMM_TFBIF_STALL2_SEL
 
|}
 
|}
   −
Takes the data for writing using the Falcon's in-chip debugger.
+
=== TSEC_FALCON_ADDR ===
 
  −
=== TSEC_FALCON_ICD_RDATA ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-31
+
| 0-5
| TSEC_FALCON_ICD_RDATA_DATA
+
| TSEC_FALCON_ADDR_LSB
 +
|-
 +
| 6-11
 +
| TSEC_FALCON_ADDR_MSB
 
|}
 
|}
   −
Returns the data read using the Falcon's in-chip debugger.
+
=== TSEC_FALCON_IBRKPT3 ===
 
  −
When reading from an internal status register (STAT), the following applies:
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-23
| RSTAT0_MEM_STALL
+
| TSEC_FALCON_IBRKPT3_PC
 
|-
 
|-
| 1
+
| 29
| RSTAT0_DMA_STALL
+
| TSEC_FALCON_IBRKPT3_SUPPRESS
 
|-
 
|-
| 2
+
| 30
| RSTAT0_FENCE_STALL
+
| TSEC_FALCON_IBRKPT3_SKIP
 
|-
 
|-
| 3
+
| 31
| RSTAT0_DIV_STALL
+
| TSEC_FALCON_IBRKPT3_EN
 +
|}
 +
 
 +
=== TSEC_FALCON_IBRKPT4 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 4
+
| 0-23
| RSTAT0_DMA_STALL_DMAQ
+
| TSEC_FALCON_IBRKPT4_PC
 
|-
 
|-
| 5
+
| 29
| RSTAT0_DMA_STALL_DMWAITING
+
| TSEC_FALCON_IBRKPT4_SUPPRESS
 
|-
 
|-
| 6
+
| 30
| RSTAT0_DMA_STALL_IMWAITING
+
| TSEC_FALCON_IBRKPT4_SKIP
 
|-
 
|-
| 7
+
| 31
| RSTAT0_ANY_STALL
+
| TSEC_FALCON_IBRKPT4_EN
 +
|}
 +
 
 +
=== TSEC_FALCON_IBRKPT5 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 8
+
| 0-23
| RSTAT0_SBFULL_STALL
+
| TSEC_FALCON_IBRKPT5_PC
 
|-
 
|-
| 9
+
| 29
| RSTAT0_SBHIT_STALL
+
| TSEC_FALCON_IBRKPT5_SUPPRESS
 
|-
 
|-
| 10
+
| 30
| RSTAT0_FLOW_STALL
+
| TSEC_FALCON_IBRKPT5_SKIP
 
|-
 
|-
| 11
+
| 31
| RSTAT0_SP_STALL
+
| TSEC_FALCON_IBRKPT5_EN
 +
|}
 +
 
 +
=== TSEC_FALCON_EXCI ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 12
+
| 0-19
| RSTAT0_BL_STALL
+
| TSEC_FALCON_EXCI_EXPC
 
|-
 
|-
| 13
+
| 20-23
| RSTAT0_IPND_STALL
+
| TSEC_FALCON_EXCI_EXCAUSE
 +
0x00: TRAP0
 +
0x01: TRAP1
 +
0x02: TRAP2
 +
0x03: TRAP3
 +
0x08: ILL_INS (invalid opcode)
 +
0x09: INV_INS (authentication entry)
 +
0x0A: MISS_INS (page miss)
 +
0x0B: DHIT_INS (page multiple hit)
 +
0x0F: BRKPT_INS (breakpoint hit)
 +
|}
 +
 
 +
Contains information about raised exceptions.
 +
 
 +
=== TSEC_FALCON_SVEC_SPR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 14
+
| 18
| RSTAT0_LDSTQ_STALL
+
| TSEC_FALCON_SVEC_SPR_SIGPASS
 +
|}
 +
 
 +
=== TSEC_FALCON_RSTAT0 ===
 +
Mirror of the [[#TSEC_FALCON_ICD_RDATA|ICD status register 0]].
 +
 
 +
=== TSEC_FALCON_RSTAT3 ===
 +
Mirror of the [[#TSEC_FALCON_ICD_RDATA|ICD status register 3]].
 +
 
 +
=== TSEC_FALCON_CPUCTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 16
+
| 0
| RSTAT0_NOINSTR_STALL
+
| TSEC_FALCON_CPUCTL_IINVAL
 
|-
 
|-
| 20
+
| 1
| RSTAT0_HALTSTOP_FLUSH
+
| TSEC_FALCON_CPUCTL_STARTCPU
 
|-
 
|-
| 21
+
| 2
| RSTAT0_AFILL_FLUSH
+
| TSEC_FALCON_CPUCTL_SRESET
 
|-
 
|-
| 22
+
| 3
| RSTAT0_EXC_FLUSH
+
| TSEC_FALCON_CPUCTL_HRESET
 
|-
 
|-
| 23-25
+
| 4
| RSTAT0_IRQ_FLUSH
+
| TSEC_FALCON_CPUCTL_HALTED
 
|-
 
|-
| 28
+
| 5
| RSTAT0_VALIDRD
+
| TSEC_FALCON_CPUCTL_STOPPED
 
|-
 
|-
| 29
+
| 6
| RSTAT0_WAITING
+
| TSEC_FALCON_CPUCTL_ALIAS_EN
|-
  −
| 30
  −
| RSTAT0_HALTED
  −
|-
  −
| 31
  −
| RSTAT0_MTHD_FULL
   
|}
 
|}
 +
 +
Used for signaling the Falcon CPU.
 +
 +
=== TSEC_FALCON_BOOTVEC ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-31
| RSTAT1_WB_ALLOC
+
| TSEC_FALCON_BOOTVEC_VEC
|-
+
|}
| 4-7
+
 
| RSTAT1_WB_VALID
+
Takes the Falcon's boot vector address.
 +
 
 +
=== TSEC_FALCON_HWCFG ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 8-9
+
| 0-8
| RSTAT1_WB0_SZ
+
| TSEC_FALCON_HWCFG_IMEM_SIZE
 
|-
 
|-
| 10-11
+
| 9-17
| RSTAT1_WB1_SZ
+
| TSEC_FALCON_HWCFG_DMEM_SIZE
 
|-
 
|-
| 12-13
+
| 18-26
| RSTAT1_WB2_SZ
+
| TSEC_FALCON_HWCFG_METHODFIFO_DEPTH
 
|-
 
|-
| 14-15
+
| 27-31
| RSTAT1_WB3_SZ
+
| TSEC_FALCON_HWCFG_DMAQUEUE_DEPTH
|-
  −
| 16-19
  −
| RSTAT1_WB0_IDX
  −
|-
  −
| 20-23
  −
| RSTAT1_WB1_IDX
  −
|-
  −
| 24-27
  −
| RSTAT1_WB2_IDX
  −
|-
  −
| 28-31
  −
| RSTAT1_WB3_IDX
   
|}
 
|}
 +
 +
=== TSEC_FALCON_DMACTL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0
| RSTAT2_DMAQ_NUM
+
| TSEC_FALCON_DMACTL_REQUIRE_CTX
 
|-
 
|-
| 4
+
| 1
| RSTAT2_DMA_ENABLE
+
| TSEC_FALCON_DMACTL_DMEM_SCRUBBING
 
|-
 
|-
| 5-7
+
| 2
| RSTAT2_LDSTQ_NUM
+
| TSEC_FALCON_DMACTL_IMEM_SCRUBBING
 
|-
 
|-
| 16-19
+
| 3-6
| RSTAT2_EM_BUSY
+
| TSEC_FALCON_DMACTL_DMAQ_NUM
 
|-
 
|-
| 20-23
+
| 7
| RSTAT2_EM_ACKED
+
| TSEC_FALCON_DMACTL_SECURE_STAT
 +
|}
 +
 
 +
Used for configuring the Falcon's DMA engine.
 +
 
 +
=== TSEC_FALCON_DMATRFBASE ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 24-27
+
| 0-31
| RSTAT2_EM_ISWR
+
| TSEC_FALCON_DMATRFBASE_BASE
|-
  −
| 28-31
  −
| RSTAT2_EM_DVLD
   
|}
 
|}
 +
 +
Base address of the external memory buffer, shifted right by 8.
 +
 +
The current transfer address is calculated by adding [[#TSEC_FALCON_DMATRFFBOFFS|TSEC_FALCON_DMATRFFBOFFS]] to the base.
 +
 +
=== TSEC_FALCON_DMATRFMOFFS ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-15
| RSTAT3_MTHD_IDLE
+
| TSEC_FALCON_DMATRFMOFFS_OFFS
 +
|}
 +
 
 +
For transfers to DMEM: the destination address.
 +
For transfers to IMEM: the destination virtual IMEM page.
 +
 
 +
=== TSEC_FALCON_DMATRFCMD ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_FALCON_DMATRFCMD_FULL
 
|-
 
|-
 
| 1
 
| 1
| RSTAT3_CTXSW_IDLE
+
| TSEC_FALCON_DMATRFCMD_IDLE
 
|-
 
|-
| 2
+
| 2-3
| RSTAT3_DMA_IDLE
+
| TSEC_FALCON_DMATRFCMD_SEC
|-
  −
| 3
  −
| RSTAT3_SCP_IDLE
   
|-
 
|-
 
| 4
 
| 4
| RSTAT3_LDST_IDLE
+
| TSEC_FALCON_DMATRFCMD_IMEM
 
|-
 
|-
 
| 5
 
| 5
| RSTAT3_SBWB_EMPTY
+
| TSEC_FALCON_DMATRFCMD_WRITE
 
|-
 
|-
| 6-8
+
| 8-10
| RSTAT3_CSWIE
+
| TSEC_FALCON_DMATRFCMD_SIZE
|-
  −
| 10
  −
| RSTAT3_CSWE
   
|-
 
|-
 
| 12-14
 
| 12-14
| RSTAT3_CTXSW_STATE
+
| TSEC_FALCON_DMATRFCMD_CTXDMA
0x00: IDLE
+
|}
0x01: SM_CHECK
+
 
0x02: SM_SAVE
+
Used for configuring DMA transfers.
0x03: SM_SAVE_WAIT
+
 
0x04: SM_BLK_BIND
+
=== TSEC_FALCON_DMATRFFBOFFS ===
0x05: SM_RESET
+
{| class="wikitable" border="1"
  0x06: SM_RESETWAIT
+
! Bits
  0x07: SM_ACK
+
! Description
 
|-
 
|-
| 15
+
| 0-31
| RSTAT3_CTXSW_PEND
+
| TSEC_FALCON_DMATRFFBOFFS_OFFS
 +
|}
 +
 
 +
For transfers to IMEM: the destination physical IMEM page.
 +
 
 +
=== TSEC_FALCON_DMAPOLL_FB ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 17
+
| 0
| RSTAT3_DMA_FBREQ_IDLE
+
| TSEC_FALCON_DMAPOLL_FB_FENCE_ACTIVE
 
|-
 
|-
| 18
+
| 1
| RSTAT3_DMA_ACKQ_EMPTY
+
| TSEC_FALCON_DMAPOLL_FB_DMA_ACTIVE
 
|-
 
|-
| 19
+
| 4
| RSTAT3_DMA_RDQ_EMPTY
+
| TSEC_FALCON_DMAPOLL_FB_CFG_R_FENCE
 
|-
 
|-
| 20
+
| 5
| RSTAT3_DMA_WR_BUSY
+
| TSEC_FALCON_DMAPOLL_FB_CFG_W_FENCE
 
|-
 
|-
| 21
+
| 16-23
| RSTAT3_DMA_RD_BUSY
+
| TSEC_FALCON_DMAPOLL_FB_WCOUNT
 
|-
 
|-
| 22
+
| 24-31
| RSTAT3_LDST_XT_BUSY
+
| TSEC_FALCON_DMAPOLL_FB_RCOUNT
|-
  −
| 23
  −
| RSTAT3_LDST_XT_BLOCK
  −
|-
  −
| 24
  −
| RSTAT3_ENG_IDLE
   
|}
 
|}
 +
 +
Contains the status of a DMA transfer between the Falcon and external memory.
 +
 +
=== TSEC_FALCON_DMAPOLL_CP ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-1
+
| 0
| RSTAT4_ICD_STATE
+
| TSEC_FALCON_DMAPOLL_CP_FENCE_ACTIVE
0x00: NORMAL
  −
0x01: WAIT_ISSUE_CLEAR
  −
0x02: WAIT_EXLDQ_CLEAR
  −
0x03: FULL_DBG_MODE
   
|-
 
|-
| 2-3
+
| 1
| RSTAT4_ICD_MODE
+
| TSEC_FALCON_DMAPOLL_CP_DMA_ACTIVE
0x00: SUPPRESSICD
  −
0x01: ENTERICD_IBRK
  −
0x02: ENTERICD_STEP
   
|-
 
|-
| 16
+
| 4
| RSTAT4_ICD_EMASK_TRAP0
+
| TSEC_FALCON_DMAPOLL_CP_CFG_R_FENCE
 
|-
 
|-
| 17
+
| 5
| RSTAT4_ICD_EMASK_TRAP1
+
| TSEC_FALCON_DMAPOLL_CP_CFG_W_FENCE
 
|-
 
|-
| 18
+
| 16-23
| RSTAT4_ICD_EMASK_TRAP2
+
| TSEC_FALCON_DMAPOLL_CP_WCOUNT
 
|-
 
|-
| 19
+
| 24-31
| RSTAT4_ICD_EMASK_TRAP3
+
| TSEC_FALCON_DMAPOLL_CP_RCOUNT
 +
|}
 +
 
 +
Contains the status of a DMA transfer between the Falcon and the SCP.
 +
 
 +
=== TSEC_FALCON_HWCFG1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 20
+
| 0-3
| RSTAT4_ICD_EMASK_EXC_UNIMP
+
| TSEC_FALCON_HWCFG1_CORE_REV
 
|-
 
|-
| 21
+
| 4-5
| RSTAT4_ICD_EMASK_EXC_IMISS
+
| TSEC_FALCON_HWCFG1_SECURITY_MODEL
 
|-
 
|-
| 22
+
| 6-7
| RSTAT4_ICD_EMASK_EXC_IMHIT
+
| TSEC_FALCON_HWCFG1_CORE_REV_SUBVERSION
 
|-
 
|-
| 23
+
| 8-11
| RSTAT4_ICD_EMASK_EXC_IBREAK
+
| TSEC_FALCON_HWCFG1_IMEM_PORTS
 
|-
 
|-
| 24
+
| 12-15
| RSTAT4_ICD_EMASK_IV0
+
| TSEC_FALCON_HWCFG1_DMEM_PORTS
 
|-
 
|-
| 25
+
| 16-20
| RSTAT4_ICD_EMASK_IV1
+
| TSEC_FALCON_HWCFG1_TAG_WIDTH
|-
  −
| 26
  −
| RSTAT4_ICD_EMASK_IV2
   
|-
 
|-
 
| 27
 
| 27
| RSTAT4_ICD_EMASK_EXT0
+
| TSEC_FALCON_HWCFG1_DBG_PRIV_BUS
 
|-
 
|-
 
| 28
 
| 28
| RSTAT4_ICD_EMASK_EXT1
+
| TSEC_FALCON_HWCFG1_CSB_SIZE_16M
 
|-
 
|-
 
| 29
 
| 29
| RSTAT4_ICD_EMASK_EXT2
+
| TSEC_FALCON_HWCFG1_PRIV_DIRECT
 
|-
 
|-
 
| 30
 
| 30
| RSTAT4_ICD_EMASK_EXT3
+
| TSEC_FALCON_HWCFG1_DMEM_APERTURES
 
|-
 
|-
 
| 31
 
| 31
| RSTAT4_ICD_EMASK_EXT4
+
| TSEC_FALCON_HWCFG1_IMEM_AUTOFILL
 
|}
 
|}
 +
 +
=== TSEC_FALCON_CPUCTL_ALIAS ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-7
+
| 1
| RSTAT5_LRU_STATE
+
| TSEC_FALCON_CPUCTL_ALIAS_STARTCPU
 
|}
 
|}
   −
=== TSEC_FALCON_SCTL ===
+
=== TSEC_FALCON_STACKCFG ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-1
+
| 0-15
| TSEC_FALCON_SCTL_SEC_MODE
+
| TSEC_FALCON_STACKCFG_BOTTOM
0: Non-secure
  −
1: Light Secure
  −
2: Heavy Secure
   
|-
 
|-
| 4-5
+
| 31
| Previous security mode
+
| TSEC_FALCON_STACKCFG_SPEXC
0: Non-secure
  −
1: Light Secure
  −
2: Heavy Secure
  −
|-
  −
| 12-13
  −
| Unknown
  −
|-
  −
| 14
  −
| Initialize the transition to LS mode
   
|}
 
|}
   −
=== TSEC_FALCON_SSTAT ===
+
=== TSEC_FALCON_IMCTL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 31
+
| 0-23
| Set on memory protection violation
+
| TSEC_FALCON_IMCTL_ADDR_BLK
 +
|-
 +
| 24-26
 +
| TSEC_FALCON_IMCTL_CMD
 +
0x00: NOP
 +
0x01: IMINV (ITLB)
 +
0x02: IMBLK (PTLB)
 +
0x03: IMTAG (VTLB)
 +
0x04: IMTAG_SETVLD
 
|}
 
|}
   −
=== TSEC_FALCON_SPROT_IMEM ===
+
Controls the Falcon TLB.
 +
 
 +
=== TSEC_FALCON_IMSTAT ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-31
| Read access level
+
| TSEC_FALCON_IMSTAT_VAL
|-
  −
| 4-7
  −
| Write access level
   
|}
 
|}
   −
Controls accesses to Falcon IMEM.
+
Returns the result of the last command from [[#TSEC_FALCON_IMCTL|TSEC_FALCON_IMCTL]].
   −
=== TSEC_FALCON_SPROT_DMEM ===
+
=== TSEC_FALCON_TRACEIDX ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-7
| Read access level
+
| TSEC_FALCON_TRACEIDX_IDX
 +
|-
 +
| 16-23
 +
| TSEC_FALCON_TRACEIDX_MAXIDX
 
|-
 
|-
| 4-7
+
| 24-31
| Write access level
+
| TSEC_FALCON_TRACEIDX_CNT
 
|}
 
|}
   −
Controls accesses to Falcon DMEM.
+
Controls the index for tracing with [[#TSEC_FALCON_TRACEPC|TSEC_FALCON_TRACEPC]].
   −
=== TSEC_FALCON_SPROT_CPUCTL ===
+
=== TSEC_FALCON_TRACEPC ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-23
| Read access level
+
| TSEC_FALCON_TRACEPC_PC
|-
  −
| 4-7
  −
| Write access level
   
|}
 
|}
   −
Controls accesses to the [[#TSEC_FALCON_CPUCTL|TSEC_FALCON_CPUCTL]] register.
+
Returns the PC of the last call or branch executed.
   −
=== TSEC_FALCON_SPROT_MISC ===
+
=== TSEC_FALCON_IMFILLRNG0 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-15
| Read access level
+
| TSEC_FALCON_IMFILLRNG0_TAG_LO
 
|-
 
|-
| 4-7
+
| 16-31
| Write access level
+
| TSEC_FALCON_IMFILLRNG0_TAG_HI
 
|}
 
|}
   −
Controls accesses to the following registers:
+
=== TSEC_FALCON_IMFILLRNG1 ===
* TSEC_FALCON_PRIVSTATE
  −
* TSEC_FALCON_SFTRESET
  −
* TSEC_FALCON_ADDR
  −
* [[#TSEC_FALCON_DMACTL|TSEC_FALCON_DMACTL]]
  −
* [[#TSEC_FALCON_IMCTL|TSEC_FALCON_IMCTL]]
  −
* [[#TSEC_FALCON_IMSTAT|TSEC_FALCON_IMSTAT]]
  −
* TSEC_FALCON_UNK_250
  −
* TSEC_FALCON_DMAINFO_CTL
  −
 
  −
=== TSEC_FALCON_SPROT_IRQ ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-15
| Read access level
+
| TSEC_FALCON_IMFILLRNG1_TAG_LO
 
|-
 
|-
| 4-7
+
| 16-31
| Write access level
+
| TSEC_FALCON_IMFILLRNG1_TAG_HI
 
|}
 
|}
   −
Controls accesses to the following registers:
+
=== TSEC_FALCON_IMFILLCTL ===
* [[#TSEC_FALCON_IRQMODE|TSEC_FALCON_IRQMODE]]
  −
* [[#TSEC_FALCON_IRQMSET|TSEC_FALCON_IRQMSET]]
  −
* [[#TSEC_FALCON_IRQMCLR|TSEC_FALCON_IRQMCLR]]
  −
* [[#TSEC_FALCON_IRQDEST|TSEC_FALCON_IRQDEST]]
  −
* TSEC_FALCON_GPTMRINT
  −
* TSEC_FALCON_GPTMRVAL
  −
* TSEC_FALCON_GPTMRCTL
  −
* TSEC_FALCON_IRQDEST2
  −
* TSEC_FALCON_UNK_E0
  −
 
  −
=== TSEC_FALCON_SPROT_MTHD ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-7
| Read access level
+
| TSEC_FALCON_IMFILLCTL_NBLOCKS
|-
  −
| 4-7
  −
| Write access level
   
|}
 
|}
   −
Controls accesses to the following registers:
+
=== TSEC_FALCON_IMCTL_DEBUG ===
* [[#TSEC_FALCON_ITFEN|TSEC_FALCON_ITFEN]]
  −
* TSEC_FALCON_CURCTX
  −
* TSEC_FALCON_NXTCTX
  −
* TSEC_FALCON_CTXACK
  −
* TSEC_FALCON_MTHDDATA
  −
* TSEC_FALCON_MTHDID
  −
* TSEC_FALCON_MTHDWDAT
  −
* TSEC_FALCON_MTHDCOUNT
  −
* TSEC_FALCON_MTHDPOP
  −
* TSEC_FALCON_MTHDRAMSZ
  −
* [[#TSEC_FALCON_DEBUG1|TSEC_FALCON_DEBUG1]]
  −
 
  −
=== TSEC_FALCON_SPROT_SCTL ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-23
| Read access level
+
| TSEC_FALCON_IMCTL_DEBUG_ADDR_BLK
 
|-
 
|-
| 4-7
+
| 24-26
| Write access level
+
| TSEC_FALCON_IMCTL_DEBUG_CMD
 +
0x00: NOP
 +
0x02: IMBLK
 +
0x03: IMTAG
 
|}
 
|}
   −
Controls accesses to the [[#TSEC_FALCON_SCTL|TSEC_FALCON_SCTL]] register.
+
=== TSEC_FALCON_CMEMBASE ===
 
  −
=== TSEC_FALCON_SPROT_WDTMR ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 18-31
| Read access level
+
| TSEC_FALCON_CMEMBASE_VAL
|-
  −
| 4-7
  −
| Write access level
   
|}
 
|}
   −
Controls accesses to the following registers:
+
=== TSEC_FALCON_DMEMAPERT ===
* TSEC_FALCON_WDTMRVAL
  −
* TSEC_FALCON_WDTMRCTL
  −
 
  −
=== TSEC_SCP_CTL0 ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 10
+
| 0-7
| Enable the LOAD interface
+
| TSEC_FALCON_DMEMAPERT_TIME_OUT
 
|-
 
|-
| 12
+
| 8-11
| Enable the STORE interface
+
| TSEC_FALCON_DMEMAPERT_TIME_UNIT
|-
  −
| 14
  −
| Enable the CMD interface
   
|-
 
|-
 
| 16
 
| 16
| Enable the SEQ controller
+
| TSEC_FALCON_DMEMAPERT_ENABLE
 
|-
 
|-
| 20
+
| 17-19
| Enable the [[#TSEC_SCP_CMD|TSEC_SCP_CMD]] register
+
| TSEC_FALCON_DMEMAPERT_LDSTQ_NUM
 
|}
 
|}
   −
=== TSEC_SCP_CTL1 ===
+
=== TSEC_FALCON_EXTERRADDR ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-31
| Flush the SEQ controller
+
| TSEC_FALCON_EXTERRADDR_ADDR
|-
  −
| 8
  −
| Unknown
  −
|-
  −
| 11
  −
| Enable RNG test mode
  −
|-
  −
| 12
  −
| Enable the RNG controller
  −
|-
  −
| 16
  −
| Enable LOAD interface dummy mode (all reads return 0)
  −
|-
  −
| 20
  −
| Enable LOAD interface bypassing (all reads are dropped)
  −
|-
  −
| 24
  −
| Enable STORE interface bypassing (all writes are dropped)
   
|}
 
|}
   −
=== TSEC_SCP_CTL_STAT ===
+
=== TSEC_FALCON_EXTERRSTAT ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 20
+
| 0-23
| TSEC_SCP_CTL_STAT_DEBUG_MODE
+
| TSEC_FALCON_EXTERRSTAT_PC
 +
|-
 +
| 24-27
 +
| TSEC_FALCON_EXTERRSTAT_STAT
 +
|-
 +
| 31
 +
| TSEC_FALCON_EXTERRSTAT_VALID
 
|}
 
|}
   −
=== TSEC_SCP_CTL_LOCK ===
+
=== TSEC_FALCON_CG2 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
|-
  −
| 0
  −
| Enable lockdown mode
   
|-
 
|-
 
| 1
 
| 1
| Unknown
+
| TSEC_FALCON_CG2_SLCG_FALCON_DMA
 
|-
 
|-
 
| 2
 
| 2
| Unknown
+
| TSEC_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM
 
|-
 
|-
 
| 3
 
| 3
| Unknown
+
| TSEC_FALCON_CG2_SLCG_FALCON_PIPE
 
|-
 
|-
 
| 4
 
| 4
| Lock the SCP
+
| TSEC_FALCON_CG2_SLCG_FALCON_DIV
 
|-
 
|-
 
| 5
 
| 5
| Unknown
+
| TSEC_FALCON_CG2_SLCG_FALCON_ICD
 
|-
 
|-
 
| 6
 
| 6
| Unknown
+
| TSEC_FALCON_CG2_SLCG_FALCON_CFG
 
|-
 
|-
 
| 7
 
| 7
| Unknown
+
| TSEC_FALCON_CG2_SLCG_FALCON_CTXSW
 +
|-
 +
| 8
 +
| TSEC_FALCON_CG2_SLCG_FALCON_PMB
 +
|-
 +
| 9
 +
| TSEC_FALCON_CG2_SLCG_FALCON_RF
 +
|-
 +
| 10
 +
| TSEC_FALCON_CG2_SLCG_FALCON_MUL
 +
|-
 +
| 11
 +
| TSEC_FALCON_CG2_SLCG_FALCON_LDST
 +
|-
 +
| 12
 +
| TSEC_FALCON_CG2_SLCG_FALCON_TSYNC
 +
|-
 +
| 13
 +
| TSEC_FALCON_CG2_SLCG_FALCON_GPTMR
 +
|-
 +
| 14
 +
| TSEC_FALCON_CG2_SLCG_FALCON_WDTMR
 +
|-
 +
| 15
 +
| TSEC_FALCON_CG2_SLCG_FALCON_IRQSTAT
 +
|-
 +
| 16
 +
| TSEC_FALCON_CG2_SLCG_FALCON_TOP
 +
|-
 +
| 17
 +
| TSEC_FALCON_CG2_SLCG_FBIF
 
|}
 
|}
   −
Controls lockdown mode and can only be cleared in Heavy Secure mode.
+
=== TSEC_FALCON_IMEMC0 ===
 
  −
=== TSEC_SCP_CFG ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 2-7
| Unknown
+
| TSEC_FALCON_IMEMC_OFFS
 
|-
 
|-
| 1
+
| 8-15
| Unknown
+
| TSEC_FALCON_IMEMC_BLK
 
|-
 
|-
| 2
+
| 24
| Unknown
+
| TSEC_FALCON_IMEMC_AINCW
 
|-
 
|-
| 3
+
| 25
| Unknown
+
| TSEC_FALCON_IMEMC_AINCR
 
|-
 
|-
| 4
+
| 28
| Unknown
+
| TSEC_FALCON_IMEMC_SECURE
 
|-
 
|-
| 8
+
| 29
| Flush the CMD interface
+
| TSEC_FALCON_IMEMC_SEC_ATOMIC
 
|-
 
|-
| 12-13
+
| 30
| Carry chain size
+
| TSEC_FALCON_IMEMC_SEC_WR_VIO
0: 32 bits
  −
1: 64 bits
  −
2: 96 bits
  −
3: 128 bits
   
|-
 
|-
| 16-31
+
| 31
| Timeout value
+
| TSEC_FALCON_IMEMC_SEC_LOCK
 
|}
 
|}
   −
=== TSEC_SCP_CTL_SCP ===
+
Used for configuring access to Falcon's IMEM.
 +
 
 +
=== TSEC_FALCON_IMEMD0 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-31
| Swap SCP master
+
| TSEC_FALCON_IMEMD_DATA
|-
  −
| 1
  −
| Current SCP master
  −
0: Falcon
  −
1: External
   
|}
 
|}
   −
=== TSEC_SCP_CTL_PKEY ===
+
Returns or takes the value for an IMEM read/write operation.
 +
 
 +
=== TSEC_FALCON_IMEMT0 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-15
| TSEC_SCP_CTL_PKEY_REQUEST_RELOAD
+
| TSEC_FALCON_IMEMT_TAG
|-
  −
| 1
  −
| TSEC_SCP_CTL_PKEY_LOADED
   
|}
 
|}
   −
=== TSEC_SCP_CTL_DBG ===
+
Returns or takes the virtual page index for an IMEM read/write operation.
 +
 
 +
=== TSEC_FALCON_DMEMC0 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 2-7
| Unknown
+
| TSEC_FALCON_DMEMC_OFFS
 +
|-
 +
| 8-15
 +
| TSEC_FALCON_DMEMC_BLK
 
|-
 
|-
| 4
+
| 24
| Unknown
+
| TSEC_FALCON_DMEMC_AINCW
 
|-
 
|-
| 8
+
| 25
| Unknown
+
| TSEC_FALCON_DMEMC_AINCR
 +
|}
 +
 
 +
Used for configuring access to Falcon's DMEM.
 +
 
 +
=== TSEC_FALCON_DMEMD0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 12
+
| 0-31
| Unknown
+
| TSEC_FALCON_DMEMD_DATA
 
|}
 
|}
   −
=== TSEC_SCP_DBG0 ===
+
Returns or takes the value for a DMEM read/write operation.
 +
 
 +
=== TSEC_FALCON_ICD_CMD ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 2,764: Line 2,842:  
|-
 
|-
 
| 0-3
 
| 0-3
| Index
+
| TSEC_FALCON_ICD_CMD_OPC
 +
0x00: STOP
 +
0x01: RUN (run from PC)
 +
0x02: JRUN (run from address)
 +
0x03: RUNB (run from PC)
 +
0x04: JRUNB (run from address)
 +
0x05: STEP (step from PC)
 +
0x06: JSTEP (step from address)
 +
0x07: EMASK (set exception mask)
 +
0x08: RREG (read register)
 +
0x09: WREG (write register)
 +
0x0A: RDM (read data memory)
 +
0x0B: WDM (write data memory)
 +
0x0C: RCM (read MMIO/configuration memory)
 +
0x0D: WCM (write MMIO/configuration memory)
 +
0x0E: RSTAT (read status)
 +
0x0F: SBU (store buffer update)
 
|-
 
|-
| 4
+
| 6-7
| Automatic increment
+
| TSEC_FALCON_ICD_CMD_SZ
|-
+
  0x00: B (byte)
| 5-6
+
  0x01: HW (half word)
| Target
+
  0x02: W (word)
0: None
  −
  1: STORE
  −
  2: LOAD
  −
  3: SEQ
   
|-
 
|-
 
| 8-12
 
| 8-12
| SEQ size
+
| TSEC_FALCON_ICD_CMD_IDX
|-
+
0x00: REG0 | RSTAT0 | WB0
| 13-16
+
0x01: REG1 | RSTAT1 | WB1
| Unknown
+
0x02: REG2 | RSTAT2 | WB2
|-
+
0x03: REG3 | RSTAT3 | WB3
| 17
+
0x04: REG4 | RSTAT4
| SEQ instruction is valid
+
0x05: REG5 | RSTAT5
 +
0x06: REG6
 +
0x07: REG7
 +
0x08: REG8
 +
0x09: REG9
 +
0x0A: REG10
 +
0x0B: REG11
 +
0x0C: REG12
 +
0x0D: REG13
 +
0x0E: REG14
 +
0x0F: REG15
 +
0x10: IV0
 +
0x11: IV1
 +
0x12: UNDEFINED
 +
0x13: EV
 +
0x14: SP
 +
0x15: PC
 +
0x16: IMB
 +
0x17: DMB
 +
0x18: CSW
 +
0x19: CCR
 +
0x1A: SEC
 +
0x1B: CTX
 +
0x1C: EXCI
 +
0x1D: SEC1
 +
0x1E: IMB1
 +
0x1F: DMB1
 
|-
 
|-
| 18
+
| 14
| SEQ controller is running in HS mode
+
| TSEC_FALCON_ICD_CMD_ERROR
 
|-
 
|-
| 19-22
+
| 15
| LOAD size
+
| TSEC_FALCON_ICD_CMD_RDVLD
 
|-
 
|-
| 23
+
| 16-31
| LOAD instruction is valid
+
| TSEC_FALCON_ICD_CMD_PARM
|-
+
0x0001: EMASK_TRAP0
| 24
+
0x0002: EMASK_TRAP1
| LOAD interface is running in HS mode
+
0x0004: EMASK_TRAP2
|-
+
0x0008: EMASK_TRAP3
| 25-26
+
0x0010: EMASK_EXC_UNIMP
| STORE size
+
0x0020: EMASK_EXC_IMISS
|-
+
0x0040: EMASK_EXC_IMHIT
| 30
+
0x0080: EMASK_EXC_IBREAK
| STORE instruction is valid
+
0x0100: EMASK_IV0
|-
+
0x0200: EMASK_IV1
| 31
+
0x0400: EMASK_IV2
| STORE interface is running in HS mode
+
0x0800: EMASK_EXT0
 +
0x1000: EMASK_EXT1
 +
0x2000: EMASK_EXT2
 +
0x4000: EMASK_EXT3
 +
0x8000: EMASK_EXT4
 
|}
 
|}
   −
Used for debugging crypto controllers such as the SEQ (crypto sequence).
+
Used for sending commands to the Falcon's in-chip debugger.
   −
=== TSEC_SCP_DBG1 ===
+
=== TSEC_FALCON_ICD_ADDR ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-31
| SEQ instruction's first operand
+
| TSEC_FALCON_ICD_ADDR_ADDR
|-
+
|}
| 4-9
+
 
| SEQ instruction's second operand
+
Takes the target address for the Falcon's in-chip debugger.
 +
 
 +
=== TSEC_FALCON_ICD_WDATA ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 10-14
+
| 0-31
| SEQ instruction's opcode
+
| TSEC_FALCON_ICD_WDATA_DATA
 
|}
 
|}
   −
Used for retrieving debug data. Contains information on the last crypto sequence created when debugging the SEQ controller.
+
Takes the data for writing using the Falcon's in-chip debugger.
   −
=== TSEC_SCP_DBG2 ===
+
=== TSEC_FALCON_ICD_RDATA ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-1
+
| 0-31
| SEQ controller's state
+
| TSEC_FALCON_ICD_RDATA_DATA
0: Idle
  −
1: Recording is active (cs0begin/cs1begin)
  −
|-
  −
| 4-7
  −
| Number of SEQ instructions left
  −
|-
  −
| 12-15
  −
| Active crypto key register
   
|}
 
|}
   −
Used for retrieving additional debug data associated with the SEQ controller.
+
Returns the data read using the Falcon's in-chip debugger.
   −
=== TSEC_SCP_CMD ===
+
When reading from an internal status register (STAT), the following applies:
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0
| Destination register
+
| RSTAT0_MEM_STALL
 
|-
 
|-
| 8-13
+
| 1
| Source register or immediate value
+
| RSTAT0_DMA_STALL
 +
|-
 +
| 2
 +
| RSTAT0_FENCE_STALL
 
|-
 
|-
| 20-24
+
| 3
| Command opcode
+
| RSTAT0_DIV_STALL
0x0:  nop (fuc5 opcode 0x00)
  −
0x1:  cmov (fuc5 opcode 0x84)
  −
0x2:  cxsin (fuc5 opcode 0x88) or xdst (with cxset)
  −
0x3:  cxsout (fuc5 opcode 0x8C) or xdld (with cxset)
  −
0x4:  crnd (fuc5 opcode 0x90)
  −
0x5:  cs0begin (fuc5 opcode 0x94)
  −
0x6:  cs0exec (fuc5 opcode 0x98)
  −
0x7:  cs1begin (fuc5 opcode 0x9C)
  −
0x8:  cs1exec (fuc5 opcode 0xA0)
  −
0x9:  invalid (fuc5 opcode 0xA4)
  −
0xA:  cchmod (fuc5 opcode 0xA8)
  −
0xB:  cxor (fuc5 opcode 0xAC)
  −
0xC:  cadd (fuc5 opcode 0xB0)
  −
0xD:  cand (fuc5 opcode 0xB4)
  −
0xE:  crev (fuc5 opcode 0xB8)
  −
0xF:  cprecmac (fuc5 opcode 0xBC)
  −
0x10: csecret (fuc5 opcode 0xC0)
  −
0x11: ckeyreg (fuc5 opcode 0xC4)
  −
0x12: ckexp (fuc5 opcode 0xC8)
  −
0x13: ckrexp (fuc5 opcode 0xCC)
  −
0x14: cenc (fuc5 opcode 0xD0)
  −
0x15: cdec (fuc5 opcode 0xD4)
  −
0x16: csigauth (fuc5 opcode 0xD8)
  −
0x17: csigenc (fuc5 opcode 0xDC)
  −
0x18: csigclr (fuc5 opcode 0xE0)
   
|-
 
|-
| 28
+
| 4
| CMD instruction is valid
+
| RSTAT0_DMA_STALL_DMAQ
 
|-
 
|-
| 31
+
| 5
| CMD interface is running in HS mode
+
| RSTAT0_DMA_STALL_DMWAITING
|}
  −
 
  −
Contains information on the last crypto command executed.
  −
 
  −
=== TSEC_SCP_STAT0 ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
| 0
+
| 6
| SCP is active
+
| RSTAT0_DMA_STALL_IMWAITING
 
|-
 
|-
| 2
+
| 7
| CMD interface is active
+
| RSTAT0_ANY_STALL
 
|-
 
|-
| 4
+
| 8
| STORE interface is active
+
| RSTAT0_SBFULL_STALL
 
|-
 
|-
| 6
+
| 9
| SEQ controller is active
+
| RSTAT0_SBHIT_STALL
 
|-
 
|-
| 8
+
| 10
| [[#TSEC_SCP_CMD|TSEC_SCP_CMD]] register is enabled
+
| RSTAT0_FLOW_STALL
 
|-
 
|-
| 10
+
| 11
| LOAD interface is active
+
| RSTAT0_SP_STALL
 
|-
 
|-
| 14
+
| 12
| AES controller is active
+
| RSTAT0_BL_STALL
 
|-
 
|-
| 16
+
| 13
| RNG controller is active
+
| RSTAT0_IPND_STALL
|}
  −
 
  −
Contains the status of the crypto controllers and interfaces.
  −
 
  −
=== TSEC_SCP_STAT1 ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
| 0-1
+
| 14
| Signature comparison result
+
| RSTAT0_LDSTQ_STALL
0: None
  −
1: Running
  −
2: Failed
  −
3: Succeeded
   
|-
 
|-
| 4
+
| 16
| LOAD interface is running in HS mode
+
| RSTAT0_NOINSTR_STALL
 
|-
 
|-
| 6
+
| 20
| LOAD interface is ready
+
| RSTAT0_HALTSTOP_FLUSH
 
|-
 
|-
| 8
+
| 21
| STORE interface is running in HS mode
+
| RSTAT0_AFILL_FLUSH
 
|-
 
|-
| 10
+
| 22
| STORE interface received a valid instruction
+
| RSTAT0_EXC_FLUSH
 
|-
 
|-
| 12
+
| 23-25
| CMD interface is running in HS mode
+
| RSTAT0_IRQ_FLUSH
 
|-
 
|-
| 14
+
| 28
| CMD interface received a valid instruction
+
| RSTAT0_VALIDRD
 +
|-
 +
| 29
 +
| RSTAT0_WAITING
 +
|-
 +
| 30
 +
| RSTAT0_HALTED
 +
|-
 +
| 31
 +
| RSTAT0_MTHD_FULL
 
|}
 
|}
  −
Contains the status of the last authentication attempt and other miscellaneous statuses.
  −
  −
=== TSEC_SCP_STAT2 ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-4
+
| 0-3
| Current SEQ opcode
+
| RSTAT1_WB_ALLOC
 
|-
 
|-
| 5-9
+
| 4-7
| Current CMD opcode
+
| RSTAT1_WB_VALID
 
|-
 
|-
| 10-14
+
| 8-9
| Pending CMD opcode
+
| RSTAT1_WB0_SZ
 
|-
 
|-
| 15-16
+
| 10-11
| AES operation
+
| RSTAT1_WB1_SZ
0: Encryption
  −
1: Decryption
  −
2: Key expansion
  −
3: Key reverse expansion
   
|-
 
|-
| 24
+
| 12-13
| Unknown
+
| RSTAT1_WB2_SZ
 
|-
 
|-
| 25
+
| 14-15
| STORE operation is stalled
+
| RSTAT1_WB3_SZ
 
|-
 
|-
| 26
+
| 16-19
| LOAD operation is stalled
+
| RSTAT1_WB0_IDX
 
|-
 
|-
| 27
+
| 20-23
| RNG operation is stalled
+
| RSTAT1_WB1_IDX
 
|-
 
|-
| 28
+
| 24-27
| Unknown
+
| RSTAT1_WB2_IDX
 
|-
 
|-
| 29
+
| 28-31
| AES operation is stalled
+
| RSTAT1_WB3_IDX
 
|}
 
|}
  −
Contains the status of crypto operations.
  −
  −
=== TSEC_SCP_RNG_STAT0 ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-3
| Internal RND controller is ready
+
| RSTAT2_DMAQ_NUM
 
|-
 
|-
| 4-7
+
| 4
| Unknown
+
| RSTAT2_DMA_ENABLE
 
|-
 
|-
| 8-11
+
| 5-7
| Unknown
+
| RSTAT2_LDSTQ_NUM
 
|-
 
|-
| 16
+
| 16-19
| Unknown
+
| RSTAT2_EM_BUSY
 
|-
 
|-
| 20
+
| 20-23
| Unknown
+
| RSTAT2_EM_ACKED
|}
  −
 
  −
=== TSEC_SCP_RNG_STAT1 ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
| 0-15
+
| 24-27
| Unknown
+
| RSTAT2_EM_ISWR
 
|-
 
|-
| 16-31
+
| 28-31
| Unknown
+
| RSTAT2_EM_DVLD
 
|}
 
|}
  −
=== TSEC_SCP_IRQSTAT ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 3,039: Line 3,103:  
|-
 
|-
 
| 0
 
| 0
| RND ready
+
| RSTAT3_MTHD_IDLE
 
|-
 
|-
| 8
+
| 1
| ACL error
+
| RSTAT3_CTXSW_IDLE
 
|-
 
|-
| 12
+
| 2
| SEC error
+
| RSTAT3_DMA_IDLE
 
|-
 
|-
| 16
+
| 3
| CMD error
+
| RSTAT3_SCP_IDLE
 
|-
 
|-
| 20
+
| 4
| Single step
+
| RSTAT3_LDST_IDLE
 
|-
 
|-
| 24
+
| 5
| RND operation
+
| RSTAT3_SBWB_EMPTY
 
|-
 
|-
| 28
+
| 6-8
| Timeout
+
| RSTAT3_CSWIE
|}
  −
 
  −
Used for getting the status of crypto IRQs.
  −
 
  −
=== TSEC_SCP_IRQMASK ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
| 0
+
| 10
| RND ready
+
| RSTAT3_CSWE
 
|-
 
|-
| 8
+
| 12-14
| ACL error
+
| RSTAT3_CTXSW_STATE
 +
0x00: IDLE
 +
0x01: SM_CHECK
 +
0x02: SM_SAVE
 +
0x03: SM_SAVE_WAIT
 +
0x04: SM_BLK_BIND
 +
0x05: SM_RESET
 +
0x06: SM_RESETWAIT
 +
0x07: SM_ACK
 
|-
 
|-
| 12
+
| 15
| SEC error
+
| RSTAT3_CTXSW_PEND
 
|-
 
|-
| 16
+
| 17
| CMD error
+
| RSTAT3_DMA_FBREQ_IDLE
 
|-
 
|-
| 20
+
| 18
| Single step
+
| RSTAT3_DMA_ACKQ_EMPTY
 
|-
 
|-
| 24
+
| 19
| RND operation
+
| RSTAT3_DMA_RDQ_EMPTY
 
|-
 
|-
| 28
+
| 20
| Timeout
+
| RSTAT3_DMA_WR_BUSY
|}
  −
 
  −
Used for getting the value of the mask for crypto IRQs.
  −
 
  −
=== TSEC_SCP_ACL_ERR ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
| 0
+
| 21
| Writing to a crypto register without the correct ACL
+
| RSTAT3_DMA_RD_BUSY
 
|-
 
|-
| 4
+
| 22
| Reading from a crypto register without the correct ACL
+
| RSTAT3_LDST_XT_BUSY
 
|-
 
|-
| 8
+
| 23
| Invalid ACL change (cchmod)
+
| RSTAT3_LDST_XT_BLOCK
 
|-
 
|-
| 31
+
| 24
| ACL error occurred
+
| RSTAT3_ENG_IDLE
 
|}
 
|}
  −
Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|ACL error]] IRQ.
  −
  −
=== TSEC_SCP_SEC_ERR ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-1
| Unknown
+
| RSTAT4_ICD_STATE
 +
0x00: NORMAL
 +
0x01: WAIT_ISSUE_CLEAR
 +
0x02: WAIT_EXLDQ_CLEAR
 +
0x03: FULL_DBG_MODE
 
|-
 
|-
| 1-2
+
| 2-3
| Unknown
+
| RSTAT4_ICD_MODE
 +
0x00: SUPPRESSICD
 +
0x01: ENTERICD_IBRK
 +
0x02: ENTERICD_STEP
 
|-
 
|-
| 4
+
| 16
| Unknown
+
| RSTAT4_ICD_EMASK_TRAP0
 
|-
 
|-
| 5-6
+
| 17
| Unknown
+
| RSTAT4_ICD_EMASK_TRAP1
 
|-
 
|-
| 16
+
| 18
| Unknown
+
| RSTAT4_ICD_EMASK_TRAP2
 
|-
 
|-
| 17-18
+
| 19
| Unknown
+
| RSTAT4_ICD_EMASK_TRAP3
 
|-
 
|-
 
| 20
 
| 20
| Unknown
+
| RSTAT4_ICD_EMASK_EXC_UNIMP
 +
|-
 +
| 21
 +
| RSTAT4_ICD_EMASK_EXC_IMISS
 
|-
 
|-
| 21-22
+
| 22
| Unknown
+
| RSTAT4_ICD_EMASK_EXC_IMHIT
 
|-
 
|-
| 24
+
| 23
| Unknown
+
| RSTAT4_ICD_EMASK_EXC_IBREAK
 
|-
 
|-
| 25-26
+
| 24
| Unknown
+
| RSTAT4_ICD_EMASK_IV0
 +
|-
 +
| 25
 +
| RSTAT4_ICD_EMASK_IV1
 +
|-
 +
| 26
 +
| RSTAT4_ICD_EMASK_IV2
 +
|-
 +
| 27
 +
| RSTAT4_ICD_EMASK_EXT0
 +
|-
 +
| 28
 +
| RSTAT4_ICD_EMASK_EXT1
 +
|-
 +
| 29
 +
| RSTAT4_ICD_EMASK_EXT2
 +
|-
 +
| 30
 +
| RSTAT4_ICD_EMASK_EXT3
 
|-
 
|-
 
| 31
 
| 31
| SEC error occurred
+
| RSTAT4_ICD_EMASK_EXT4
 +
|}
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-7
 +
| RSTAT5_LRU_STATE
 
|}
 
|}
   −
=== TSEC_SCP_CMD_ERR ===
+
=== TSEC_FALCON_SCTL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-1
| Invalid command
+
| TSEC_FALCON_SCTL_SEC_MODE
 +
0: Non-secure
 +
1: Light Secure
 +
2: Heavy Secure
 
|-
 
|-
| 4
+
| 4-5
| Empty crypto sequence
+
| Previous security mode
 +
0: Non-secure
 +
1: Light Secure
 +
2: Heavy Secure
 
|-
 
|-
| 8
+
| 12-13
| Crypto sequence is too long
+
| Unknown
 
|-
 
|-
| 12
+
| 14
| Crypto sequence was not finished
+
| Initialize the transition to LS mode
|-
  −
| 16
  −
| Forbidden signature operation (csigenc, csigclr or csigauth in NS mode)
  −
|-
  −
| 20
  −
| Invalid signature operation (csigauth in HS mode)
  −
|-
  −
| 24
  −
| Forbidden ACL change (cchmod in NS mode)
   
|}
 
|}
   −
Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|CMD error]] IRQ.
+
=== TSEC_FALCON_SSTAT ===
 
  −
=== TSEC_SCP_RND_CTL0 ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-31
+
| 31
| RND clock trigger lower limit
+
| Set on memory protection violation
 
|}
 
|}
   −
=== TSEC_SCP_RND_CTL1 ===
+
=== TSEC_FALCON_SPROT_IMEM ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-15
+
| 0-3
| RND clock trigger upper limit
+
| Read access level
 
|-
 
|-
| 16-31
+
| 4-7
| RND clock trigger mask
+
| Write access level
 
|}
 
|}
   −
=== TSEC_TFBIF_CTL ===
+
Controls accesses to Falcon IMEM.
 +
 
 +
=== TSEC_FALCON_SPROT_DMEM ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-3
| TSEC_TFBIF_CTL_CLR_BWCOUNT
+
| Read access level
 
|-
 
|-
| 1
+
| 4-7
| TSEC_TFBIF_CTL_ENABLE
+
| Write access level
 +
|}
 +
 
 +
Controls accesses to Falcon DMEM.
 +
 
 +
=== TSEC_FALCON_SPROT_CPUCTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 2
+
| 0-3
| TSEC_TFBIF_CTL_CLR_IDLEWDERR
+
| Read access level
 
|-
 
|-
| 3
+
| 4-7
| TSEC_TFBIF_CTL_RESET
+
| Write access level
 +
|}
 +
 
 +
Controls accesses to the [[#TSEC_FALCON_CPUCTL|TSEC_FALCON_CPUCTL]] register.
 +
 
 +
=== TSEC_FALCON_SPROT_MISC ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 4
+
| 0-3
| TSEC_TFBIF_CTL_IDLE
+
| Read access level
 
|-
 
|-
| 5
+
| 4-7
| TSEC_TFBIF_CTL_IDLEWDERR
+
| Write access level
|-
  −
| 6
  −
| TSEC_TFBIF_CTL_SRTOUT
  −
|-
  −
| 7
  −
| TSEC_TFBIF_CTL_CLR_SRTOUT
  −
|-
  −
| 8-11
  −
| TSEC_TFBIF_CTL_SRTOVAL
  −
|-
  −
| 12
  −
| TSEC_TFBIF_CTL_VPR
   
|}
 
|}
   −
=== TSEC_TFBIF_MCCIF_FIFOCTRL ===
+
Controls accesses to the following registers:
 +
* [[#TSEC_FALCON_PRIVSTATE|TSEC_FALCON_PRIVSTATE]]
 +
* [[#TSEC_FALCON_SFTRESET|TSEC_FALCON_SFTRESET]]
 +
* [[#TSEC_FALCON_ADDR|TSEC_FALCON_ADDR]]
 +
* [[#TSEC_FALCON_DMACTL|TSEC_FALCON_DMACTL]]
 +
* [[#TSEC_FALCON_IMCTL|TSEC_FALCON_IMCTL]]
 +
* [[#TSEC_FALCON_IMSTAT|TSEC_FALCON_IMSTAT]]
 +
* TSEC_FALCON_UNK_250
 +
* [[#TSEC_FALCON_DMAINFO_CTL|TSEC_FALCON_DMAINFO_CTL]]
 +
 
 +
=== TSEC_FALCON_SPROT_IRQ ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-3
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVERRIDE
+
| Read access level
 
|-
 
|-
| 1
+
| 4-7
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVERRIDE
+
| Write access level
|-
+
|}
| 2
+
 
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRCL_MCLE2X
+
Controls accesses to the following registers:
|-
+
* [[#TSEC_FALCON_IRQMODE|TSEC_FALCON_IRQMODE]]
| 3
+
* [[#TSEC_FALCON_IRQMSET|TSEC_FALCON_IRQMSET]]
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDMC_RDFAST
+
* [[#TSEC_FALCON_IRQMCLR|TSEC_FALCON_IRQMCLR]]
|-
+
* [[#TSEC_FALCON_IRQDEST|TSEC_FALCON_IRQDEST]]
| 4
+
* [[#TSEC_FALCON_GPTMRINT|TSEC_FALCON_GPTMRINT]]
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRMC_CLLE2X
+
* [[#TSEC_FALCON_GPTMRVAL|TSEC_FALCON_GPTMRVAL]]
|-
+
* [[#TSEC_FALCON_GPTMRCTL|TSEC_FALCON_GPTMRCTL]]
| 5
+
* [[#TSEC_FALCON_IRQDEST2|TSEC_FALCON_IRQDEST2]]
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDCL_RDFAST
+
* TSEC_FALCON_UNK_E0
|-
  −
| 6
  −
| TSEC_TFBIF_MCCIF_FIFOCTRL_CCLK_OVERRIDE
  −
|-
  −
| 7
  −
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVR_MODE
  −
|-
  −
| 8
  −
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVR_MODE
  −
|}
     −
=== TSEC_TFBIF_MCCIF_FIFOCTRL1 ===
+
=== TSEC_FALCON_SPROT_MTHD ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-15
+
| 0-3
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SRD2MC_REORDER_DEPTH_LIMIT
+
| Read access level
 
|-
 
|-
| 16-31
+
| 4-7
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SWR2MC_REORDER_DEPTH_LIMIT
+
| Write access level
 
|}
 
|}
   −
=== TSEC_TFBIF_THROTTLE ===
+
Controls accesses to the following registers:
 +
* [[#TSEC_FALCON_ITFEN|TSEC_FALCON_ITFEN]]
 +
* [[#TSEC_FALCON_CURCTX|TSEC_FALCON_CURCTX]]
 +
* [[#TSEC_FALCON_NXTCTX|TSEC_FALCON_NXTCTX]]
 +
* [[#TSEC_FALCON_CTXACK|TSEC_FALCON_CTXACK]]
 +
* [[#TSEC_FALCON_MTHDDATA|TSEC_FALCON_MTHDDATA]]
 +
* [[#TSEC_FALCON_MTHDID|TSEC_FALCON_MTHDID]]
 +
* [[#TSEC_FALCON_MTHDWDAT|TSEC_FALCON_MTHDWDAT]]
 +
* [[#TSEC_FALCON_MTHDCOUNT|TSEC_FALCON_MTHDCOUNT]]
 +
* [[#TSEC_FALCON_MTHDPOP|TSEC_FALCON_MTHDPOP]]
 +
* [[#TSEC_FALCON_MTHDRAMSZ|TSEC_FALCON_MTHDRAMSZ]]
 +
* [[#TSEC_FALCON_DEBUG1|TSEC_FALCON_DEBUG1]]
 +
 
 +
=== TSEC_FALCON_SPROT_SCTL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-11
+
| 0-3
| TSEC_TFBIF_THROTTLE_BUCKET_SIZE
+
| Read access level
 
|-
 
|-
| 16-27
+
| 4-7
| TSEC_TFBIF_THROTTLE_LEAK_COUNT
+
| Write access level
|-
  −
| 30-31
  −
| TSEC_TFBIF_THROTTLE_LEAK_SIZE
   
|}
 
|}
   −
=== TSEC_TFBIF_DBG_STAT0 ===
+
Controls accesses to the [[#TSEC_FALCON_SCTL|TSEC_FALCON_SCTL]] register.
 +
 
 +
=== TSEC_FALCON_SPROT_WDTMR ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-3
| TSEC_TFBIF_DBG_STAT0_1K_TRANSFER
+
| Read access level
 
|-
 
|-
| 1
+
| 4-7
| TSEC_TFBIF_DBG_STAT0_RREQ_ISSUED
+
| Write access level
 +
|}
 +
 
 +
Controls accesses to the following registers:
 +
* [[#TSEC_FALCON_WDTMRVAL|TSEC_FALCON_WDTMRVAL]]
 +
* [[#TSEC_FALCON_WDTMRCTL|TSEC_FALCON_WDTMRCTL]]
 +
 
 +
=== TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 2
+
| 0-31
| TSEC_TFBIF_DBG_STAT0_WREQ_ISSUED
+
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL
 +
|}
 +
 
 +
=== TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 3
+
| 0-30
| TSEC_TFBIF_DBG_STAT0_TAGQ_ISSUED
+
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL
 
|-
 
|-
| 4
+
| 31
| TSEC_TFBIF_DBG_STAT0_STALL_RDATQ
+
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT
 +
|}
 +
 
 +
=== TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 5
+
| 0-31
| TSEC_TFBIF_DBG_STAT0_STALL_RACKQ
+
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL
 +
|}
 +
 
 +
=== TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 6
+
| 0-30
| TSEC_TFBIF_DBG_STAT0_STALL_WREQQ
+
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL
 
|-
 
|-
| 7
+
| 31
| TSEC_TFBIF_DBG_STAT0_STALL_WDATQ
+
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT
 +
|}
 +
 
 +
=== TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 8
+
| 0-31
| TSEC_TFBIF_DBG_STAT0_STALL_WACKQ
+
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL
 +
|}
 +
 
 +
=== TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 9
+
| 0-30
| TSEC_TFBIF_DBG_STAT0_STALL_RREQ_PENDING
+
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL
 
|-
 
|-
| 10
+
| 31
| TSEC_TFBIF_DBG_STAT0_STALL_WREQ_PENDING
+
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT
 +
|}
 +
 
 +
=== TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 11
+
| 0-31
| TSEC_TFBIF_DBG_STAT0_STALL_MREQ
+
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL
|-
  −
| 12
  −
| TSEC_TFBIF_DBG_STAT0_ENGINE_IDLE
  −
|-
  −
| 13
  −
| TSEC_TFBIF_DBG_STAT0_RMCCIF_IDLE
  −
|-
  −
| 14
  −
| TSEC_TFBIF_DBG_STAT0_WMCCIF_IDLE
  −
|-
  −
| 15
  −
| TSEC_TFBIF_DBG_STAT0_CSB_IDLE
  −
|-
  −
| 16
  −
| TSEC_TFBIF_DBG_STAT0_RU_IDLE
  −
|-
  −
| 17
  −
| TSEC_TFBIF_DBG_STAT0_WU_IDLE
  −
|-
  −
| 19
  −
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_ACTIVE
  −
|-
  −
| 20
  −
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_MCB
   
|}
 
|}
   −
=== TSEC_TFBIF_SPROT_EMEM ===
+
=== TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-30
| Read access level
+
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL
 
|-
 
|-
| 4-7
+
| 31
| Write access level
+
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT
 
|}
 
|}
   −
Controls accesses to external memory regions. Accessible in HS mode only.
+
=== TSEC_FALCON_DMAINFO_CTL ===
 
  −
=== TSEC_TFBIF_TRANSCFG ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 3,382: Line 3,502:  
|-
 
|-
 
| 0
 
| 0
| TSEC_TFBIF_TRANSCFG_ATT0_SWID
+
| TSEC_FALCON_DMAINFO_CTL_CLR_FBRD
 
|-
 
|-
| 4
+
| 1
| TSEC_TFBIF_TRANSCFG_ATT1_SWID
+
| TSEC_FALCON_DMAINFO_CTL_CLR_FBWR
 +
|}
 +
 
 +
=== TSEC_SCP_CTL0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 8
+
| 10
| TSEC_TFBIF_TRANSCFG_ATT2_SWID
+
| Enable the LOAD interface
 
|-
 
|-
 
| 12
 
| 12
| TSEC_TFBIF_TRANSCFG_ATT3_SWID
+
| Enable the STORE interface
 +
|-
 +
| 14
 +
| Enable the CMD interface
 
|-
 
|-
 
| 16
 
| 16
| TSEC_TFBIF_TRANSCFG_ATT4_SWID
+
| Enable the SEQ controller
 
|-
 
|-
 
| 20
 
| 20
| TSEC_TFBIF_TRANSCFG_ATT5_SWID
+
| Enable the [[#TSEC_SCP_CMD|TSEC_SCP_CMD]] register
|-
  −
| 24
  −
| TSEC_TFBIF_TRANSCFG_ATT6_SWID
  −
|-
  −
| 28
  −
| TSEC_TFBIF_TRANSCFG_ATT7_SWID
   
|}
 
|}
   −
Configures the software ID per CTXDMA port for memory transactions. Software ID 0 (HW_SWID) forces all transactions to go through the SMMU while software ID 1 (PHY_SWID) bypasses it. Accessible in HS mode only.
+
=== TSEC_SCP_CTL1 ===
 
  −
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
  −
 
  −
=== TSEC_TFBIF_REGIONCFG ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-2
+
| 0
| TSEC_TFBIF_REGIONCFG_T0_APERT_ID
+
| Flush the SEQ controller
 
|-
 
|-
| 3
+
| 8
| TSEC_TFBIF_REGIONCFG_T0_VPR
+
| Unknown
|-
  −
| 4-6
  −
| TSEC_TFBIF_REGIONCFG_T1_APERT_ID
  −
|-
  −
| 7
  −
| TSEC_TFBIF_REGIONCFG_T1_VPR
  −
|-
  −
| 8-10
  −
| TSEC_TFBIF_REGIONCFG_T2_APERT_ID
   
|-
 
|-
 
| 11
 
| 11
| TSEC_TFBIF_REGIONCFG_T2_VPR
+
| Enable RNG test mode
 
|-
 
|-
| 12-14
+
| 12
| TSEC_TFBIF_REGIONCFG_T3_APERT_ID
+
| Enable the RNG controller
 
|-
 
|-
| 15
+
| 16
| TSEC_TFBIF_REGIONCFG_T3_VPR
+
| Enable LOAD interface dummy mode (all reads return 0)
 
|-
 
|-
| 16-18
+
| 20
| TSEC_TFBIF_REGIONCFG_T4_APERT_ID
+
| Enable LOAD interface bypassing (all reads are dropped)
 
|-
 
|-
| 19
+
| 24
| TSEC_TFBIF_REGIONCFG_T4_VPR
+
| Enable STORE interface bypassing (all writes are dropped)
 +
|}
 +
 
 +
=== TSEC_SCP_CTL_STAT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 20-22
+
| 20
| TSEC_TFBIF_REGIONCFG_T5_APERT_ID
+
| TSEC_SCP_CTL_STAT_DEBUG_MODE
|-
+
|}
| 23
  −
| TSEC_TFBIF_REGIONCFG_T5_VPR
  −
|-
  −
| 24-26
  −
| TSEC_TFBIF_REGIONCFG_T6_APERT_ID
  −
|-
  −
| 27
  −
| TSEC_TFBIF_REGIONCFG_T6_VPR
  −
|-
  −
| 28-30
  −
| TSEC_TFBIF_REGIONCFG_T7_APERT_ID
  −
|-
  −
| 31
  −
| TSEC_TFBIF_REGIONCFG_T7_VPR
  −
|}
     −
Configures the aperture ID and VPR mode per CTXDMA port for memory region accessing. Accessible in HS mode only.
+
=== TSEC_SCP_CTL_LOCK ===
 
  −
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
  −
 
  −
=== TSEC_TFBIF_ACTMON_ACTIVE_MASK ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 3,474: Line 3,571:  
|-
 
|-
 
| 0
 
| 0
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_STARVED_MC
+
| Enable lockdown mode
 
|-
 
|-
 
| 1
 
| 1
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_STALLED_MC
+
| Unknown
 
|-
 
|-
 
| 2
 
| 2
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED_MC
+
| Unknown
 
|-
 
|-
 
| 3
 
| 3
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_ACTIVE
+
| Unknown
|}
  −
 
  −
Takes the memory access mask for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
  −
 
  −
=== TSEC_TFBIF_ACTMON_ACTIVE_BORPS ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
| 0
+
| 4
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STARVED_MC_POLARITY
+
| Lock the SCP
|-
  −
| 1
  −
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STARVED_MC_OPERATION
  −
|-
  −
| 2
  −
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STALLED_MC_POLARITY
  −
|-
  −
| 3
  −
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STALLED_MC_OPERATION
  −
|-
  −
| 4
  −
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_DELAYED_MC_POLARITY
   
|-
 
|-
 
| 5
 
| 5
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_DELAYED_MC_OPERATION
+
| Unknown
 
|-
 
|-
 
| 6
 
| 6
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE_POLARITY
+
| Unknown
 
|-
 
|-
 
| 7
 
| 7
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE_OPERATION
+
| Unknown
 
|}
 
|}
   −
Takes the billions of records per second count for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
+
Controls lockdown mode and can only be cleared in Heavy Secure mode.
   −
=== TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT ===
+
=== TSEC_SCP_CFG ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-31
+
| 0
| TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT_VAL
+
| Unknown
 +
|-
 +
| 1
 +
| Unknown
 +
|-
 +
| 2
 +
| Unknown
 +
|-
 +
| 3
 +
| Unknown
 +
|-
 +
| 4
 +
| Unknown
 +
|-
 +
| 8
 +
| Flush the CMD interface
 +
|-
 +
| 12-13
 +
| Carry chain size
 +
0: 32 bits
 +
1: 64 bits
 +
2: 96 bits
 +
3: 128 bits
 +
|-
 +
| 16-31
 +
| Timeout value
 +
|}
 +
 
 +
=== TSEC_SCP_CTL_SCP ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Swap SCP master
 +
|-
 +
| 1
 +
| Current SCP master
 +
0: Falcon
 +
1: External
 +
|}
 +
 
 +
=== TSEC_SCP_CTL_PKEY ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_SCP_CTL_PKEY_REQUEST_RELOAD
 +
|-
 +
| 1
 +
| TSEC_SCP_CTL_PKEY_LOADED
 
|}
 
|}
   −
Controls the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
+
=== TSEC_SCP_CTL_DBG ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Unknown
 +
|-
 +
| 4
 +
| Unknown
 +
|-
 +
| 8
 +
| Unknown
 +
|-
 +
| 12
 +
| Unknown
 +
|}
 +
 
 +
=== TSEC_SCP_DBG0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Index
 +
|-
 +
| 4
 +
| Automatic increment
 +
|-
 +
| 5-6
 +
| Target
 +
0: None
 +
1: STORE
 +
2: LOAD
 +
3: SEQ
 +
|-
 +
| 8-12
 +
| SEQ size
 +
|-
 +
| 13-16
 +
| Unknown
 +
|-
 +
| 17
 +
| SEQ instruction is valid
 +
|-
 +
| 18
 +
| SEQ controller is running in HS mode
 +
|-
 +
| 19-22
 +
| LOAD size
 +
|-
 +
| 23
 +
| LOAD instruction is valid
 +
|-
 +
| 24
 +
| LOAD interface is running in HS mode
 +
|-
 +
| 25-26
 +
| STORE size
 +
|-
 +
| 30
 +
| STORE instruction is valid
 +
|-
 +
| 31
 +
| STORE interface is running in HS mode
 +
|}
 +
 
 +
Used for debugging crypto controllers such as the SEQ (crypto sequence).
 +
 
 +
=== TSEC_SCP_DBG1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| SEQ instruction's first operand
 +
|-
 +
| 4-9
 +
| SEQ instruction's second operand
 +
|-
 +
| 10-14
 +
| SEQ instruction's opcode
 +
|}
 +
 
 +
Used for retrieving debug data. Contains information on the last crypto sequence created when debugging the SEQ controller.
 +
 
 +
=== TSEC_SCP_DBG2 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-1
 +
| SEQ controller's state
 +
0: Idle
 +
1: Recording is active (cs0begin/cs1begin)
 +
|-
 +
| 4-7
 +
| Number of SEQ instructions left
 +
|-
 +
| 12-15
 +
| Active crypto key register
 +
|}
 +
 
 +
Used for retrieving additional debug data associated with the SEQ controller.
 +
 
 +
=== TSEC_SCP_CMD ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Destination register
 +
|-
 +
| 8-13
 +
| Source register or immediate value
 +
|-
 +
| 20-24
 +
| Command opcode
 +
0x0:  nop (fuc5 opcode 0x00)
 +
0x1:  cmov (fuc5 opcode 0x84)
 +
0x2:  cxsin (fuc5 opcode 0x88) or xdst (with cxset)
 +
0x3:  cxsout (fuc5 opcode 0x8C) or xdld (with cxset)
 +
0x4:  crnd (fuc5 opcode 0x90)
 +
0x5:  cs0begin (fuc5 opcode 0x94)
 +
0x6:  cs0exec (fuc5 opcode 0x98)
 +
0x7:  cs1begin (fuc5 opcode 0x9C)
 +
0x8:  cs1exec (fuc5 opcode 0xA0)
 +
0x9:  invalid (fuc5 opcode 0xA4)
 +
0xA:  cchmod (fuc5 opcode 0xA8)
 +
0xB:  cxor (fuc5 opcode 0xAC)
 +
0xC:  cadd (fuc5 opcode 0xB0)
 +
0xD:  cand (fuc5 opcode 0xB4)
 +
0xE:  crev (fuc5 opcode 0xB8)
 +
0xF:  cprecmac (fuc5 opcode 0xBC)
 +
0x10: csecret (fuc5 opcode 0xC0)
 +
0x11: ckeyreg (fuc5 opcode 0xC4)
 +
0x12: ckexp (fuc5 opcode 0xC8)
 +
0x13: ckrexp (fuc5 opcode 0xCC)
 +
0x14: cenc (fuc5 opcode 0xD0)
 +
0x15: cdec (fuc5 opcode 0xD4)
 +
0x16: csigauth (fuc5 opcode 0xD8)
 +
0x17: csigenc (fuc5 opcode 0xDC)
 +
0x18: csigclr (fuc5 opcode 0xE0)
 +
|-
 +
| 28
 +
| CMD instruction is valid
 +
|-
 +
| 31
 +
| CMD interface is running in HS mode
 +
|}
 +
 
 +
Contains information on the last crypto command executed.
 +
 
 +
=== TSEC_SCP_STAT0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| SCP is active
 +
|-
 +
| 2
 +
| CMD interface is active
 +
|-
 +
| 4
 +
| STORE interface is active
 +
|-
 +
| 6
 +
| SEQ controller is active
 +
|-
 +
| 8
 +
| [[#TSEC_SCP_CMD|TSEC_SCP_CMD]] register is enabled
 +
|-
 +
| 10
 +
| LOAD interface is active
 +
|-
 +
| 14
 +
| AES controller is active
 +
|-
 +
| 16
 +
| RNG controller is active
 +
|}
 +
 
 +
Contains the status of the crypto controllers and interfaces.
 +
 
 +
=== TSEC_SCP_STAT1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-1
 +
| Signature comparison result
 +
0: None
 +
1: Running
 +
2: Failed
 +
3: Succeeded
 +
|-
 +
| 4
 +
| LOAD interface is running in HS mode
 +
|-
 +
| 6
 +
| LOAD interface is ready
 +
|-
 +
| 8
 +
| STORE interface is running in HS mode
 +
|-
 +
| 10
 +
| STORE interface received a valid instruction
 +
|-
 +
| 12
 +
| CMD interface is running in HS mode
 +
|-
 +
| 14
 +
| CMD interface received a valid instruction
 +
|}
 +
 
 +
Contains the status of the last authentication attempt and other miscellaneous statuses.
 +
 
 +
=== TSEC_SCP_STAT2 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-4
 +
| Current SEQ opcode
 +
|-
 +
| 5-9
 +
| Current CMD opcode
 +
|-
 +
| 10-14
 +
| Pending CMD opcode
 +
|-
 +
| 15-16
 +
| AES operation
 +
0: Encryption
 +
1: Decryption
 +
2: Key expansion
 +
3: Key reverse expansion
 +
|-
 +
| 24
 +
| Unknown
 +
|-
 +
| 25
 +
| STORE operation is stalled
 +
|-
 +
| 26
 +
| LOAD operation is stalled
 +
|-
 +
| 27
 +
| RNG operation is stalled
 +
|-
 +
| 28
 +
| Unknown
 +
|-
 +
| 29
 +
| AES operation is stalled
 +
|}
 +
 
 +
Contains the status of crypto operations.
 +
 
 +
=== TSEC_SCP_RNG_STAT0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Internal RND controller is ready
 +
|-
 +
| 4-7
 +
| Unknown
 +
|-
 +
| 8-11
 +
| Unknown
 +
|-
 +
| 16
 +
| Unknown
 +
|-
 +
| 20
 +
| Unknown
 +
|}
 +
 
 +
=== TSEC_SCP_RNG_STAT1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-15
 +
| Unknown
 +
|-
 +
| 16-31
 +
| Unknown
 +
|}
 +
 
 +
=== TSEC_SCP_IRQSTAT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| RND ready
 +
|-
 +
| 8
 +
| ACL error
 +
|-
 +
| 12
 +
| SEC error
 +
|-
 +
| 16
 +
| CMD error
 +
|-
 +
| 20
 +
| Single step
 +
|-
 +
| 24
 +
| RND operation
 +
|-
 +
| 28
 +
| Timeout
 +
|}
 +
 
 +
Used for getting the status of crypto IRQs.
 +
 
 +
=== TSEC_SCP_IRQMASK ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| RND ready
 +
|-
 +
| 8
 +
| ACL error
 +
|-
 +
| 12
 +
| SEC error
 +
|-
 +
| 16
 +
| CMD error
 +
|-
 +
| 20
 +
| Single step
 +
|-
 +
| 24
 +
| RND operation
 +
|-
 +
| 28
 +
| Timeout
 +
|}
 +
 
 +
Used for getting the value of the mask for crypto IRQs.
 +
 
 +
=== TSEC_SCP_ACL_ERR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Writing to a crypto register without the correct ACL
 +
|-
 +
| 4
 +
| Reading from a crypto register without the correct ACL
 +
|-
 +
| 8
 +
| Invalid ACL change (cchmod)
 +
|-
 +
| 31
 +
| ACL error occurred
 +
|}
 +
 
 +
Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|ACL error]] IRQ.
 +
 
 +
=== TSEC_SCP_SEC_ERR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Unknown
 +
|-
 +
| 1-2
 +
| Unknown
 +
|-
 +
| 4
 +
| Unknown
 +
|-
 +
| 5-6
 +
| Unknown
 +
|-
 +
| 16
 +
| Unknown
 +
|-
 +
| 17-18
 +
| Unknown
 +
|-
 +
| 20
 +
| Unknown
 +
|-
 +
| 21-22
 +
| Unknown
 +
|-
 +
| 24
 +
| Unknown
 +
|-
 +
| 25-26
 +
| Unknown
 +
|-
 +
| 31
 +
| SEC error occurred
 +
|}
 +
 
 +
=== TSEC_SCP_CMD_ERR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Invalid command
 +
|-
 +
| 4
 +
| Empty crypto sequence
 +
|-
 +
| 8
 +
| Crypto sequence is too long
 +
|-
 +
| 12
 +
| Crypto sequence was not finished
 +
|-
 +
| 16
 +
| Forbidden signature operation (csigenc, csigclr or csigauth in NS mode)
 +
|-
 +
| 20
 +
| Invalid signature operation (csigauth in HS mode)
 +
|-
 +
| 24
 +
| Forbidden ACL change (cchmod in NS mode)
 +
|}
 +
 
 +
Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|CMD error]] IRQ.
 +
 
 +
=== TSEC_SCP_RND_CTL0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| RND clock trigger lower limit
 +
|}
 +
 
 +
=== TSEC_SCP_RND_CTL1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-15
 +
| RND clock trigger upper limit
 +
|-
 +
| 16-31
 +
| RND clock trigger mask
 +
|}
 +
 
 +
=== TSEC_TFBIF_CTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_CTL_CLR_BWCOUNT
 +
|-
 +
| 1
 +
| TSEC_TFBIF_CTL_ENABLE
 +
|-
 +
| 2
 +
| TSEC_TFBIF_CTL_CLR_IDLEWDERR
 +
|-
 +
| 3
 +
| TSEC_TFBIF_CTL_RESET
 +
|-
 +
| 4
 +
| TSEC_TFBIF_CTL_IDLE
 +
|-
 +
| 5
 +
| TSEC_TFBIF_CTL_IDLEWDERR
 +
|-
 +
| 6
 +
| TSEC_TFBIF_CTL_SRTOUT
 +
|-
 +
| 7
 +
| TSEC_TFBIF_CTL_CLR_SRTOUT
 +
|-
 +
| 8-11
 +
| TSEC_TFBIF_CTL_SRTOVAL
 +
|-
 +
| 12
 +
| TSEC_TFBIF_CTL_VPR
 +
|}
 +
 
 +
=== TSEC_TFBIF_MCCIF_FIFOCTRL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVERRIDE
 +
|-
 +
| 1
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVERRIDE
 +
|-
 +
| 2
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRCL_MCLE2X
 +
|-
 +
| 3
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDMC_RDFAST
 +
|-
 +
| 4
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRMC_CLLE2X
 +
|-
 +
| 5
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDCL_RDFAST
 +
|-
 +
| 6
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_CCLK_OVERRIDE
 +
|-
 +
| 7
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVR_MODE
 +
|-
 +
| 8
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVR_MODE
 +
|}
 +
 
 +
=== TSEC_TFBIF_THROTTLE ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-11
 +
| TSEC_TFBIF_THROTTLE_BUCKET_SIZE
 +
|-
 +
| 16-27
 +
| TSEC_TFBIF_THROTTLE_LEAK_COUNT
 +
|-
 +
| 30-31
 +
| TSEC_TFBIF_THROTTLE_LEAK_SIZE
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_STAT0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_DBG_STAT0_1K_TRANSFER
 +
|-
 +
| 1
 +
| TSEC_TFBIF_DBG_STAT0_RREQ_ISSUED
 +
|-
 +
| 2
 +
| TSEC_TFBIF_DBG_STAT0_WREQ_ISSUED
 +
|-
 +
| 3
 +
| TSEC_TFBIF_DBG_STAT0_TAGQ_ISSUED
 +
|-
 +
| 4
 +
| TSEC_TFBIF_DBG_STAT0_STALL_RDATQ
 +
|-
 +
| 5
 +
| TSEC_TFBIF_DBG_STAT0_STALL_RACKQ
 +
|-
 +
| 6
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WREQQ
 +
|-
 +
| 7
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WDATQ
 +
|-
 +
| 8
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WACKQ
 +
|-
 +
| 9
 +
| TSEC_TFBIF_DBG_STAT0_STALL_RREQ_PENDING
 +
|-
 +
| 10
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WREQ_PENDING
 +
|-
 +
| 11
 +
| TSEC_TFBIF_DBG_STAT0_STALL_MREQ
 +
|-
 +
| 12
 +
| TSEC_TFBIF_DBG_STAT0_ENGINE_IDLE
 +
|-
 +
| 13
 +
| TSEC_TFBIF_DBG_STAT0_RMCCIF_IDLE
 +
|-
 +
| 14
 +
| TSEC_TFBIF_DBG_STAT0_WMCCIF_IDLE
 +
|-
 +
| 15
 +
| TSEC_TFBIF_DBG_STAT0_CSB_IDLE
 +
|-
 +
| 16
 +
| TSEC_TFBIF_DBG_STAT0_RU_IDLE
 +
|-
 +
| 17
 +
| TSEC_TFBIF_DBG_STAT0_WU_IDLE
 +
|-
 +
| 19
 +
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_ACTIVE
 +
|-
 +
| 20
 +
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_MCB
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_STAT1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_DBG_STAT1_DATA
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_RDCOUNT_LO ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_DBG_RDCOUNT_LO_DATA
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_RDCOUNT_HI ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_DBG_RDCOUNT_HI_DATA
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_WRCOUNT_LO ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_DBG_WRCOUNT_LO_DATA
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_WRCOUNT_HI ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_DBG_WRCOUNT_HI_DATA
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_R32COUNT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_DBG_R32COUNT_DATA
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_R64COUNT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_DBG_R64COUNT_DATA
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_R128COUNT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_DBG_R128COUNT_DATA
 +
|}
 +
 
 +
=== TSEC_TFBIF_MCCIF_FIFOCTRL1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-15
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SRD2MC_REORDER_DEPTH_LIMIT
 +
|-
 +
| 16-31
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SWR2MC_REORDER_DEPTH_LIMIT
 +
|}
 +
 
 +
=== TSEC_TFBIF_WRR_RDP ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-15
 +
| TSEC_TFBIF_WRR_RDP_EXT_WEIGHT
 +
|-
 +
| 16-31
 +
| TSEC_TFBIF_WRR_RDP_INT_WEIGHT
 +
|}
 +
 
 +
=== TSEC_TFBIF_SPROT_EMEM ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to external memory regions. Accessible in HS mode only.
 +
 
 +
=== TSEC_TFBIF_TRANSCFG ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_TRANSCFG_ATT0_SWID
 +
|-
 +
| 4
 +
| TSEC_TFBIF_TRANSCFG_ATT1_SWID
 +
|-
 +
| 8
 +
| TSEC_TFBIF_TRANSCFG_ATT2_SWID
 +
|-
 +
| 12
 +
| TSEC_TFBIF_TRANSCFG_ATT3_SWID
 +
|-
 +
| 16
 +
| TSEC_TFBIF_TRANSCFG_ATT4_SWID
 +
|-
 +
| 20
 +
| TSEC_TFBIF_TRANSCFG_ATT5_SWID
 +
|-
 +
| 24
 +
| TSEC_TFBIF_TRANSCFG_ATT6_SWID
 +
|-
 +
| 28
 +
| TSEC_TFBIF_TRANSCFG_ATT7_SWID
 +
|}
 +
 
 +
Configures the software ID per CTXDMA port for memory transactions. Software ID 0 (HW_SWID) forces all transactions to go through the SMMU while software ID 1 (PHY_SWID) bypasses it. Accessible in HS mode only.
 +
 
 +
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
 +
 
 +
=== TSEC_TFBIF_REGIONCFG ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-2
 +
| TSEC_TFBIF_REGIONCFG_T0_APERT_ID
 +
|-
 +
| 3
 +
| TSEC_TFBIF_REGIONCFG_T0_VPR
 +
|-
 +
| 4-6
 +
| TSEC_TFBIF_REGIONCFG_T1_APERT_ID
 +
|-
 +
| 7
 +
| TSEC_TFBIF_REGIONCFG_T1_VPR
 +
|-
 +
| 8-10
 +
| TSEC_TFBIF_REGIONCFG_T2_APERT_ID
 +
|-
 +
| 11
 +
| TSEC_TFBIF_REGIONCFG_T2_VPR
 +
|-
 +
| 12-14
 +
| TSEC_TFBIF_REGIONCFG_T3_APERT_ID
 +
|-
 +
| 15
 +
| TSEC_TFBIF_REGIONCFG_T3_VPR
 +
|-
 +
| 16-18
 +
| TSEC_TFBIF_REGIONCFG_T4_APERT_ID
 +
|-
 +
| 19
 +
| TSEC_TFBIF_REGIONCFG_T4_VPR
 +
|-
 +
| 20-22
 +
| TSEC_TFBIF_REGIONCFG_T5_APERT_ID
 +
|-
 +
| 23
 +
| TSEC_TFBIF_REGIONCFG_T5_VPR
 +
|-
 +
| 24-26
 +
| TSEC_TFBIF_REGIONCFG_T6_APERT_ID
 +
|-
 +
| 27
 +
| TSEC_TFBIF_REGIONCFG_T6_VPR
 +
|-
 +
| 28-30
 +
| TSEC_TFBIF_REGIONCFG_T7_APERT_ID
 +
|-
 +
| 31
 +
| TSEC_TFBIF_REGIONCFG_T7_VPR
 +
|}
 +
 
 +
Configures the aperture ID and VPR mode per CTXDMA port for memory region accessing. Accessible in HS mode only.
 +
 
 +
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
 +
 
 +
=== TSEC_TFBIF_ACTMON_ACTIVE_MASK ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_STARVED_MC
 +
|-
 +
| 1
 +
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_STALLED_MC
 +
|-
 +
| 2
 +
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED_MC
 +
|-
 +
| 3
 +
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_ACTIVE
 +
|}
 +
 
 +
Takes the memory access mask for the Activity Monitor. Disconnected on the TSEC.
 +
 
 +
=== TSEC_TFBIF_ACTMON_ACTIVE_BORPS ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STARVED_MC_POLARITY
 +
|-
 +
| 1
 +
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STARVED_MC_OPERATION
 +
|-
 +
| 2
 +
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STALLED_MC_POLARITY
 +
|-
 +
| 3
 +
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STALLED_MC_OPERATION
 +
|-
 +
| 4
 +
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_DELAYED_MC_POLARITY
 +
|-
 +
| 5
 +
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_DELAYED_MC_OPERATION
 +
|-
 +
| 6
 +
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE_POLARITY
 +
|-
 +
| 7
 +
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE_OPERATION
 +
|}
 +
 
 +
Takes the billions of records per second count for the Activity Monitor. Disconnected on the TSEC.
 +
 
 +
=== TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT_VAL
 +
|}
 +
 
 +
Controls the Activity Monitor. Disconnected on the TSEC.
 +
 
 +
 
 +
=== TSEC_TFBIF_ACTMON_MCB_MASK ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_ACTMON_MCB_MASK_STARVED_MC
 +
|-
 +
| 1
 +
| TSEC_TFBIF_ACTMON_MCB_MASK_STALLED_MC
 +
|-
 +
| 2
 +
| TSEC_TFBIF_ACTMON_MCB_MASK_DELAYED_MC
 +
|-
 +
| 3
 +
| TSEC_TFBIF_ACTMON_MCB_MASK_ACTIVE
 +
|}
 +
 
 +
Disconnected on the TSEC.
 +
 
 +
=== TSEC_TFBIF_ACTMON_MCB_BORPS ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_ACTMON_MCB_BORPS_STARVED_MC_POLARITY
 +
|-
 +
| 1
 +
| TSEC_TFBIF_ACTMON_MCB_BORPS_STARVED_MC_OPERATION
 +
|-
 +
| 2
 +
| TSEC_TFBIF_ACTMON_MCB_BORPS_STALLED_MC_POLARITY
 +
|-
 +
| 3
 +
| TSEC_TFBIF_ACTMON_MCB_BORPS_STALLED_MC_OPERATION
 +
|-
 +
| 4
 +
| TSEC_TFBIF_ACTMON_MCB_BORPS_DELAYED_MC_POLARITY
 +
|-
 +
| 5
 +
| TSEC_TFBIF_ACTMON_MCB_BORPS_DELAYED_MC_OPERATION
 +
|-
 +
| 6
 +
| TSEC_TFBIF_ACTMON_MCB_BORPS_ACTIVE_POLARITY
 +
|-
 +
| 7
 +
| TSEC_TFBIF_ACTMON_MCB_BORPS_ACTIVE_OPERATION
 +
|}
 +
 
 +
Disconnected on the TSEC.
 +
 
 +
=== TSEC_TFBIF_ACTMON_MCB_WEIGHT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_ACTMON_MCB_WEIGHT_VAL
 +
|}
 +
 
 +
Disconnected on the TSEC.
 +
 
 +
 
 +
=== TSEC_TFBIF_THI_TRANSPROP ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-6
 +
| TSEC_TFBIF_THI_TRANSPROP_STREAMID0
 +
|-
 +
| 8-14
 +
| TSEC_TFBIF_THI_TRANSPROP_STREAMID1
 +
|-
 +
| 16
 +
| TSEC_TFBIF_THI_TRANSPROP_TZ_AUTH
 +
|}
    
=== TSEC_CG ===
 
=== TSEC_CG ===

Navigation menu