Line 8: |
Line 8: |
| * 0x54500000 to 0x54501000: THI (Tegra Host Interface) | | * 0x54500000 to 0x54501000: THI (Tegra Host Interface) |
| * 0x54501000 to 0x54501400: [[#Falcon|FALCON (Falcon microcontroller)]] | | * 0x54501000 to 0x54501400: [[#Falcon|FALCON (Falcon microcontroller)]] |
− | * 0x54501400 to 0x54501500: [[#SCP|SCP (Secure Co-processor)]] | + | * 0x54501400 to 0x54501600: [[#SCP|SCP (Secure Co-processor)]] |
− | * 0x54501500 to 0x54501600: RND (Random Number Generator)
| |
| * 0x54501600 to 0x54501680: TFBIF (Tegra Framebuffer Interface) | | * 0x54501600 to 0x54501680: TFBIF (Tegra Framebuffer Interface) |
| * 0x54501680 to 0x54501700: CG (Clock Gate) | | * 0x54501680 to 0x54501700: CG (Clock Gate) |
Line 692: |
Line 691: |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#TSEC_SCP_RND_STAT0|TSEC_SCP_RND_STAT0]] | + | | [[#TSEC_SCP_RNG_STAT0|TSEC_SCP_RNG_STAT0]] |
| | 0x54501470 | | | 0x54501470 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#TSEC_SCP_RND_STAT1|TSEC_SCP_RND_STAT1]] | + | | [[#TSEC_SCP_RNG_STAT1|TSEC_SCP_RNG_STAT1]] |
| | 0x54501474 | | | 0x54501474 |
| | 0x04 | | | 0x04 |
Line 720: |
Line 719: |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#TSEC_RND_CTL0|TSEC_RND_CTL0]] | + | | [[#TSEC_SCP_RND_CTL0|TSEC_SCP_RND_CTL0]] |
| | 0x54501500 | | | 0x54501500 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#TSEC_RND_CTL1|TSEC_RND_CTL1]] | + | | [[#TSEC_SCP_RND_CTL1|TSEC_RND_SCP_CTL1]] |
| | 0x54501504 | | | 0x54501504 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_RND_CTL2 | + | | TSEC_SCP_RND_CTL2 |
| | 0x54501508 | | | 0x54501508 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_RND_CTL3 | + | | TSEC_SCP_RND_CTL3 |
| | 0x5450150C | | | 0x5450150C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_RND_CTL4 | + | | TSEC_SCP_RND_CTL4 |
| | 0x54501510 | | | 0x54501510 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_RND_CTL5 | + | | TSEC_SCP_RND_CTL5 |
| | 0x54501514 | | | 0x54501514 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_RND_CTL6 | + | | TSEC_SCP_RND_CTL6 |
| | 0x54501518 | | | 0x54501518 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_RND_CTL7 | + | | TSEC_SCP_RND_CTL7 |
| | 0x5450151C | | | 0x5450151C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_RND_CTL8 | + | | TSEC_SCP_RND_CTL8 |
| | 0x54501520 | | | 0x54501520 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_RND_CTL9 | + | | TSEC_SCP_RND_CTL9 |
| | 0x54501524 | | | 0x54501524 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_RND_CTL10 | + | | TSEC_SCP_RND_CTL10 |
| | 0x54501528 | | | 0x54501528 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_RND_CTL11 | + | | TSEC_SCP_RND_CTL11 |
| | 0x5450152C | | | 0x5450152C |
| | 0x04 | | | 0x04 |
Line 2,625: |
Line 2,624: |
| |- | | |- |
| | 11 | | | 11 |
− | | Enable RND test mode | + | | Enable RNG test mode |
| |- | | |- |
| | 12 | | | 12 |
− | | Enable the RND controller | + | | Enable the RNG controller |
| |- | | |- |
| | 16 | | | 16 |
Line 2,921: |
Line 2,920: |
| |- | | |- |
| | 16 | | | 16 |
− | | RND controller is active | + | | RNG controller is active |
| |} | | |} |
| | | |
Line 2,990: |
Line 2,989: |
| |- | | |- |
| | 27 | | | 27 |
− | | RND operation is stalled | + | | RNG operation is stalled |
| |- | | |- |
| | 28 | | | 28 |
Line 3,001: |
Line 3,000: |
| Contains the status of crypto operations. | | Contains the status of crypto operations. |
| | | |
− | === TSEC_SCP_RND_STAT0 === | + | === TSEC_SCP_RNG_STAT0 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 3,007: |
Line 3,006: |
| |- | | |- |
| | 0 | | | 0 |
− | | RND controller is ready | + | | Internal RND controller is ready |
| |- | | |- |
| | 4-7 | | | 4-7 |
Line 3,022: |
Line 3,021: |
| |} | | |} |
| | | |
− | === TSEC_SCP_RND_STAT1 === | + | === TSEC_SCP_RNG_STAT1 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 3,180: |
Line 3,179: |
| Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|CMD error]] IRQ. | | Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|CMD error]] IRQ. |
| | | |
− | === TSEC_RND_CTL0 === | + | === TSEC_SCP_RND_CTL0 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 3,189: |
Line 3,188: |
| |} | | |} |
| | | |
− | === TSEC_RND_CTL1 === | + | === TSEC_SCP_RND_CTL1 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 3,924: |
Line 3,923: |
| This instruction initializes a crypto register with random data. | | This instruction initializes a crypto register with random data. |
| | | |
− | Executing this instruction only succeeds if the RND interface is enabled for the SCP, which requires taking the following steps: | + | Executing this instruction only succeeds if the RNG controller is enabled for the SCP, which requires taking the following steps: |
− | * Write 0x7FFF to [[#TSEC_RND_CTL0|TSEC_RND_CTL0]]. | + | * Write 0x7FFF to [[#TSEC_SCP_RND_CTL0|TSEC_SCP_RND_CTL0]]. |
− | * Write 0x3FF0000 to [[#TSEC_RND_CTL1|TSEC_RND_CTL1]]. | + | * Write 0x3FF0000 to [[#TSEC_SCP_RND_CTL1|TSEC_SCP_RND_CTL1]]. |
− | * Write 0xFF00 to TSEC_RND_CTL11. | + | * Write 0xFF00 to TSEC_SCP_RND_CTL11. |
| * Write 0x1000 to [[#TSEC_SCP_CTL1|TSEC_SCP_CTL1]]. | | * Write 0x1000 to [[#TSEC_SCP_CTL1|TSEC_SCP_CTL1]]. |
| | | |