Line 104: |
Line 104: |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_IRQSSET|FALCON_IRQSSET]] | + | | [[#TSEC_FALCON_IRQSSET|TSEC_FALCON_IRQSSET]] |
| | 0x54501000 | | | 0x54501000 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_IRQSCLR|FALCON_IRQSCLR]] | + | | [[#TSEC_FALCON_IRQSCLR|TSEC_FALCON_IRQSCLR]] |
| | 0x54501004 | | | 0x54501004 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_IRQSTAT|FALCON_IRQSTAT]] | + | | [[#TSEC_FALCON_IRQSTAT|TSEC_FALCON_IRQSTAT]] |
| | 0x54501008 | | | 0x54501008 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_IRQMODE|FALCON_IRQMODE]] | + | | [[#TSEC_FALCON_IRQMODE|TSEC_FALCON_IRQMODE]] |
| | 0x5450100C | | | 0x5450100C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_IRQMSET|FALCON_IRQMSET]] | + | | [[#TSEC_FALCON_IRQMSET|TSEC_FALCON_IRQMSET]] |
| | 0x54501010 | | | 0x54501010 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_IRQMCLR|FALCON_IRQMCLR]] | + | | [[#TSEC_FALCON_IRQMCLR|TSEC_FALCON_IRQMCLR]] |
| | 0x54501014 | | | 0x54501014 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_IRQMASK|FALCON_IRQMASK]] | + | | [[#TSEC_FALCON_IRQMASK|TSEC_FALCON_IRQMASK]] |
| | 0x54501018 | | | 0x54501018 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_IRQDEST|FALCON_IRQDEST]] | + | | [[#TSEC_FALCON_IRQDEST|TSEC_FALCON_IRQDEST]] |
| | 0x5450101C | | | 0x5450101C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_GPTMRINT | + | | TSEC_FALCON_GPTMRINT |
| | 0x54501020 | | | 0x54501020 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_GPTMRVAL | + | | TSEC_FALCON_GPTMRVAL |
| | 0x54501024 | | | 0x54501024 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_GPTMRCTL | + | | TSEC_FALCON_GPTMRCTL |
| | 0x54501028 | | | 0x54501028 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_PTIMER0 | + | | TSEC_FALCON_PTIMER0 |
| | 0x5450102C | | | 0x5450102C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_PTIMER1 | + | | TSEC_FALCON_PTIMER1 |
| | 0x54501030 | | | 0x54501030 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_WDTMRVAL | + | | TSEC_FALCON_WDTMRVAL |
| | 0x54501034 | | | 0x54501034 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_WDTMRCTL | + | | TSEC_FALCON_WDTMRCTL |
| | 0x54501038 | | | 0x54501038 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_IRQDEST2|FALCON_IRQDEST2]] | + | | [[#TSEC_FALCON_IRQDEST2|TSEC_FALCON_IRQDEST2]] |
| | 0x5450103C | | | 0x5450103C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_MAILBOX0|FALCON_MAILBOX0]] | + | | [[#TSEC_FALCON_MAILBOX0|TSEC_FALCON_MAILBOX0]] |
| | 0x54501040 | | | 0x54501040 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_MAILBOX1|FALCON_MAILBOX1]] | + | | [[#TSEC_FALCON_MAILBOX1|TSEC_FALCON_MAILBOX1]] |
| | 0x54501044 | | | 0x54501044 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_ITFEN|FALCON_ITFEN]] | + | | [[#TSEC_FALCON_ITFEN|TSEC_FALCON_ITFEN]] |
| | 0x54501048 | | | 0x54501048 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_IDLESTATE|FALCON_IDLESTATE]] | + | | [[#TSEC_FALCON_IDLESTATE|TSEC_FALCON_IDLESTATE]] |
| | 0x5450104C | | | 0x5450104C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_CURCTX | + | | TSEC_FALCON_CURCTX |
| | 0x54501050 | | | 0x54501050 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_NXTCTX | + | | TSEC_FALCON_NXTCTX |
| | 0x54501054 | | | 0x54501054 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_CTXACK | + | | TSEC_FALCON_CTXACK |
| | 0x54501058 | | | 0x54501058 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_FHSTATE | + | | TSEC_FALCON_FHSTATE |
| | 0x5450105C | | | 0x5450105C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_PRIVSTATE | + | | TSEC_FALCON_PRIVSTATE |
| | 0x54501060 | | | 0x54501060 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_MTHDDATA | + | | TSEC_FALCON_MTHDDATA |
| | 0x54501064 | | | 0x54501064 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_MTHDID | + | | TSEC_FALCON_MTHDID |
| | 0x54501068 | | | 0x54501068 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_MTHDWDAT | + | | TSEC_FALCON_MTHDWDAT |
| | 0x5450106C | | | 0x5450106C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_MTHDCOUNT | + | | TSEC_FALCON_MTHDCOUNT |
| | 0x54501070 | | | 0x54501070 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_MTHDPOP | + | | TSEC_FALCON_MTHDPOP |
| | 0x54501074 | | | 0x54501074 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_MTHDRAMSZ | + | | TSEC_FALCON_MTHDRAMSZ |
| | 0x54501078 | | | 0x54501078 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_SFTRESET | + | | TSEC_FALCON_SFTRESET |
| | 0x5450107C | | | 0x5450107C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_OS | + | | TSEC_FALCON_OS |
| | 0x54501080 | | | 0x54501080 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_RM | + | | TSEC_FALCON_RM |
| | 0x54501084 | | | 0x54501084 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_SOFT_PM | + | | TSEC_FALCON_SOFT_PM |
| | 0x54501088 | | | 0x54501088 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_SOFT_MODE | + | | TSEC_FALCON_SOFT_MODE |
| | 0x5450108C | | | 0x5450108C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_DEBUG1|FALCON_DEBUG1]] | + | | [[#TSEC_FALCON_DEBUG1|TSEC_FALCON_DEBUG1]] |
| | 0x54501090 | | | 0x54501090 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_DEBUGINFO|FALCON_DEBUGINFO]] | + | | [[#TSEC_FALCON_DEBUGINFO|TSEC_FALCON_DEBUGINFO]] |
| | 0x54501094 | | | 0x54501094 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IBRKPT1 | + | | TSEC_FALCON_IBRKPT1 |
| | 0x54501098 | | | 0x54501098 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IBRKPT2 | + | | TSEC_FALCON_IBRKPT2 |
| | 0x5450109C | | | 0x5450109C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_CGCTL | + | | TSEC_FALCON_CGCTL |
| | 0x545010A0 | | | 0x545010A0 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_ENGCTL | + | | TSEC_FALCON_ENGCTL |
| | 0x545010A4 | | | 0x545010A4 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_PMM | + | | TSEC_FALCON_PMM |
| | 0x545010A8 | | | 0x545010A8 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_ADDR | + | | TSEC_FALCON_ADDR |
| | 0x545010AC | | | 0x545010AC |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IBRKPT3 | + | | TSEC_FALCON_IBRKPT3 |
| | 0x545010B0 | | | 0x545010B0 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IBRKPT4 | + | | TSEC_FALCON_IBRKPT4 |
| | 0x545010B4 | | | 0x545010B4 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IBRKPT5 | + | | TSEC_FALCON_IBRKPT5 |
| | 0x545010B8 | | | 0x545010B8 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_EXCI|FALCON_EXCI]] | + | | [[#TSEC_FALCON_EXCI|TSEC_FALCON_EXCI]] |
| | 0x545010D0 | | | 0x545010D0 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_SVEC_SPR|FALCON_SVEC_SPR]] | + | | [[#TSEC_FALCON_SVEC_SPR|TSEC_FALCON_SVEC_SPR]] |
| | 0x545010D4 | | | 0x545010D4 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_RSTAT0|FALCON_RSTAT0]] | + | | [[#TSEC_FALCON_RSTAT0|TSEC_FALCON_RSTAT0]] |
| | 0x545010D8 | | | 0x545010D8 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_RSTAT3|FALCON_RSTAT3]] | + | | [[#TSEC_FALCON_RSTAT3|TSEC_FALCON_RSTAT3]] |
| | 0x545010DC | | | 0x545010DC |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_UNK_E0 | + | | TSEC_FALCON_UNK_E0 |
| | 0x545010E0 | | | 0x545010E0 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_CPUCTL|FALCON_CPUCTL]] | + | | [[#TSEC_FALCON_CPUCTL|TSEC_FALCON_CPUCTL]] |
| | 0x54501100 | | | 0x54501100 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_BOOTVEC|FALCON_BOOTVEC]] | + | | [[#TSEC_FALCON_BOOTVEC|TSEC_FALCON_BOOTVEC]] |
| | 0x54501104 | | | 0x54501104 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_HWCFG|FALCON_HWCFG]] | + | | [[#TSEC_FALCON_HWCFG|TSEC_FALCON_HWCFG]] |
| | 0x54501108 | | | 0x54501108 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_DMACTL|FALCON_DMACTL]] | + | | [[#TSEC_FALCON_DMACTL|TSEC_FALCON_DMACTL]] |
| | 0x5450110C | | | 0x5450110C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_DMATRFBASE|FALCON_DMATRFBASE]] | + | | [[#TSEC_FALCON_DMATRFBASE|TSEC_FALCON_DMATRFBASE]] |
| | 0x54501110 | | | 0x54501110 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_DMATRFMOFFS|FALCON_DMATRFMOFFS]] | + | | [[#TSEC_FALCON_DMATRFMOFFS|TSEC_FALCON_DMATRFMOFFS]] |
| | 0x54501114 | | | 0x54501114 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_DMATRFCMD|FALCON_DMATRFCMD]] | + | | [[#TSEC_FALCON_DMATRFCMD|TSEC_FALCON_DMATRFCMD]] |
| | 0x54501118 | | | 0x54501118 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_DMATRFFBOFFS|FALCON_DMATRFFBOFFS]] | + | | [[#TSEC_FALCON_DMATRFFBOFFS|TSEC_FALCON_DMATRFFBOFFS]] |
| | 0x5450111C | | | 0x5450111C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_DMAPOLL_FB|FALCON_DMAPOLL_FB]] | + | | [[#TSEC_FALCON_DMAPOLL_FB|TSEC_FALCON_DMAPOLL_FB]] |
| | 0x54501120 | | | 0x54501120 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_DMAPOLL_CP|FALCON_DMAPOLL_CP]] | + | | [[#TSEC_FALCON_DMAPOLL_CP|TSEC_FALCON_DMAPOLL_CP]] |
| | 0x54501124 | | | 0x54501124 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DBG_STATE | + | | TSEC_FALCON_DBG_STATE |
| | 0x54501128 | | | 0x54501128 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_HWCFG1|FALCON_HWCFG1]] | + | | [[#TSEC_FALCON_HWCFG1|TSEC_FALCON_HWCFG1]] |
| | 0x5450112C | | | 0x5450112C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_CPUCTL_ALIAS | + | | TSEC_FALCON_CPUCTL_ALIAS |
| | 0x54501130 | | | 0x54501130 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_STACKCFG | + | | TSEC_FALCON_STACKCFG |
| | 0x54501138 | | | 0x54501138 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_IMCTL|FALCON_IMCTL]] | + | | [[#TSEC_FALCON_IMCTL|TSEC_FALCON_IMCTL]] |
| | 0x54501140 | | | 0x54501140 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_IMSTAT|FALCON_IMSTAT]] | + | | [[#TSEC_FALCON_IMSTAT|TSEC_FALCON_IMSTAT]] |
| | 0x54501144 | | | 0x54501144 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_TRACEIDX|FALCON_TRACEIDX]] | + | | [[#TSEC_FALCON_TRACEIDX|TSEC_FALCON_TRACEIDX]] |
| | 0x54501148 | | | 0x54501148 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_TRACEPC|FALCON_TRACEPC]] | + | | [[#TSEC_FALCON_TRACEPC|TSEC_FALCON_TRACEPC]] |
| | 0x5450114C | | | 0x5450114C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IMFILLRNG0 | + | | TSEC_FALCON_IMFILLRNG0 |
| | 0x54501150 | | | 0x54501150 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IMFILLRNG1 | + | | TSEC_FALCON_IMFILLRNG1 |
| | 0x54501154 | | | 0x54501154 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IMFILLCTL | + | | TSEC_FALCON_IMFILLCTL |
| | 0x54501158 | | | 0x54501158 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IMCTL_DEBUG | + | | TSEC_FALCON_IMCTL_DEBUG |
| | 0x5450115C | | | 0x5450115C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_CMEMBASE | + | | TSEC_FALCON_CMEMBASE |
| | 0x54501160 | | | 0x54501160 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMEMAPERT | + | | TSEC_FALCON_DMEMAPERT |
| | 0x54501164 | | | 0x54501164 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_EXTERRADDR | + | | TSEC_FALCON_EXTERRADDR |
| | 0x54501168 | | | 0x54501168 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_EXTERRSTAT | + | | TSEC_FALCON_EXTERRSTAT |
| | 0x5450116C | | | 0x5450116C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_CG2 | + | | TSEC_FALCON_CG2 |
| | 0x5450117C | | | 0x5450117C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_IMEMC0|FALCON_IMEMC0]] | + | | [[#TSEC_FALCON_IMEMC0|TSEC_FALCON_IMEMC0]] |
| | 0x54501180 | | | 0x54501180 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_IMEMD0|FALCON_IMEMD0]] | + | | [[#TSEC_FALCON_IMEMD0|TSEC_FALCON_IMEMD0]] |
| | 0x54501184 | | | 0x54501184 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_IMEMT0|FALCON_IMEMT0]] | + | | [[#TSEC_FALCON_IMEMT0|TSEC_FALCON_IMEMT0]] |
| | 0x54501188 | | | 0x54501188 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IMEMC1 | + | | TSEC_FALCON_IMEMC1 |
| | 0x54501190 | | | 0x54501190 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IMEMD1 | + | | TSEC_FALCON_IMEMD1 |
| | 0x54501194 | | | 0x54501194 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IMEMT1 | + | | TSEC_FALCON_IMEMT1 |
| | 0x54501198 | | | 0x54501198 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IMEMC2 | + | | TSEC_FALCON_IMEMC2 |
| | 0x545011A0 | | | 0x545011A0 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IMEMD2 | + | | TSEC_FALCON_IMEMD2 |
| | 0x545011A4 | | | 0x545011A4 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IMEMT2 | + | | TSEC_FALCON_IMEMT2 |
| | 0x545011A8 | | | 0x545011A8 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IMEMC3 | + | | TSEC_FALCON_IMEMC3 |
| | 0x545011B0 | | | 0x545011B0 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IMEMD3 | + | | TSEC_FALCON_IMEMD3 |
| | 0x545011B4 | | | 0x545011B4 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_IMEMT3 | + | | TSEC_FALCON_IMEMT3 |
| | 0x545011B8 | | | 0x545011B8 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_DMEMC0|FALCON_DMEMC0]] | + | | [[#TSEC_FALCON_DMEMC0|TSEC_FALCON_DMEMC0]] |
| | 0x545011C0 | | | 0x545011C0 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_DMEMD0|FALCON_DMEMD0]] | + | | [[#TSEC_FALCON_DMEMD0|TSEC_FALCON_DMEMD0]] |
| | 0x545011C4 | | | 0x545011C4 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMEMC1 | + | | TSEC_FALCON_DMEMC1 |
| | 0x545011C8 | | | 0x545011C8 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMEMD1 | + | | TSEC_FALCON_DMEMD1 |
| | 0x545011CC | | | 0x545011CC |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMEMC2 | + | | TSEC_FALCON_DMEMC2 |
| | 0x545011D0 | | | 0x545011D0 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMEMD2 | + | | TSEC_FALCON_DMEMD2 |
| | 0x545011D4 | | | 0x545011D4 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMEMC3 | + | | TSEC_FALCON_DMEMC3 |
| | 0x545011D8 | | | 0x545011D8 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMEMD3 | + | | TSEC_FALCON_DMEMD3 |
| | 0x545011DC | | | 0x545011DC |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMEMC4 | + | | TSEC_FALCON_DMEMC4 |
| | 0x545011E0 | | | 0x545011E0 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMEMD4 | + | | TSEC_FALCON_DMEMD4 |
| | 0x545011E4 | | | 0x545011E4 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMEMC5 | + | | TSEC_FALCON_DMEMC5 |
| | 0x545011E8 | | | 0x545011E8 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMEMD5 | + | | TSEC_FALCON_DMEMD5 |
| | 0x545011EC | | | 0x545011EC |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMEMC6 | + | | TSEC_FALCON_DMEMC6 |
| | 0x545011F0 | | | 0x545011F0 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMEMD6 | + | | TSEC_FALCON_DMEMD6 |
| | 0x545011F4 | | | 0x545011F4 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMEMC7 | + | | TSEC_FALCON_DMEMC7 |
| | 0x545011F8 | | | 0x545011F8 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMEMD7 | + | | TSEC_FALCON_DMEMD7 |
| | 0x545011FC | | | 0x545011FC |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_ICD_CMD|FALCON_ICD_CMD]] | + | | [[#TSEC_FALCON_ICD_CMD|TSEC_FALCON_ICD_CMD]] |
| | 0x54501200 | | | 0x54501200 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_ICD_ADDR|FALCON_ICD_ADDR]] | + | | [[#TSEC_FALCON_ICD_ADDR|TSEC_FALCON_ICD_ADDR]] |
| | 0x54501204 | | | 0x54501204 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_ICD_WDATA|FALCON_ICD_WDATA]] | + | | [[#TSEC_FALCON_ICD_WDATA|TSEC_FALCON_ICD_WDATA]] |
| | 0x54501208 | | | 0x54501208 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_ICD_RDATA|FALCON_ICD_RDATA]] | + | | [[#TSEC_FALCON_ICD_RDATA|TSEC_FALCON_ICD_RDATA]] |
| | 0x5450120C | | | 0x5450120C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_SCTL|FALCON_SCTL]] | + | | [[#TSEC_FALCON_SCTL|TSEC_FALCON_SCTL]] |
| | 0x54501240 | | | 0x54501240 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_SSTAT|FALCON_SSTAT]] | + | | [[#TSEC_FALCON_SSTAT|TSEC_FALCON_SSTAT]] |
| | 0x54501244 | | | 0x54501244 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_UNK_250 | + | | TSEC_FALCON_UNK_250 |
| | 0x54501250 | | | 0x54501250 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_UNK_260 | + | | TSEC_FALCON_UNK_260 |
| | 0x54501260 | | | 0x54501260 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_SPROT_IMEM|FALCON_SPROT_IMEM]] | + | | [[#TSEC_FALCON_SPROT_IMEM|TSEC_FALCON_SPROT_IMEM]] |
| | 0x54501280 | | | 0x54501280 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_SPROT_DMEM|FALCON_SPROT_DMEM]] | + | | [[#TSEC_FALCON_SPROT_DMEM|TSEC_FALCON_SPROT_DMEM]] |
| | 0x54501284 | | | 0x54501284 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_SPROT_CPUCTL|FALCON_SPROT_CPUCTL]] | + | | [[#TSEC_FALCON_SPROT_CPUCTL|TSEC_FALCON_SPROT_CPUCTL]] |
| | 0x54501288 | | | 0x54501288 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_SPROT_MISC|FALCON_SPROT_MISC]] | + | | [[#TSEC_FALCON_SPROT_MISC|TSEC_FALCON_SPROT_MISC]] |
| | 0x5450128C | | | 0x5450128C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_SPROT_IRQ|FALCON_SPROT_IRQ]] | + | | [[#TSEC_FALCON_SPROT_IRQ|TSEC_FALCON_SPROT_IRQ]] |
| | 0x54501290 | | | 0x54501290 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_SPROT_MTHD|FALCON_SPROT_MTHD]] | + | | [[#TSEC_FALCON_SPROT_MTHD|TSEC_FALCON_SPROT_MTHD]] |
| | 0x54501294 | | | 0x54501294 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_SPROT_SCTL|FALCON_SPROT_SCTL]] | + | | [[#TSEC_FALCON_SPROT_SCTL|TSEC_FALCON_SPROT_SCTL]] |
| | 0x54501298 | | | 0x54501298 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#FALCON_SPROT_WDTMR|FALCON_SPROT_WDTMR]] | + | | [[#TSEC_FALCON_SPROT_WDTMR|TSEC_FALCON_SPROT_WDTMR]] |
| | 0x5450129C | | | 0x5450129C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMAINFO_FINISHED_FBRD_LOW | + | | TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW |
| | 0x545012C0 | | | 0x545012C0 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMAINFO_FINISHED_FBRD_HIGH | + | | TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH |
| | 0x545012C4 | | | 0x545012C4 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMAINFO_FINISHED_FBWR_LOW | + | | TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW |
| | 0x545012C8 | | | 0x545012C8 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMAINFO_FINISHED_FBWR_HIGH | + | | TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH |
| | 0x545012CC | | | 0x545012CC |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMAINFO_CURRENT_FBRD_LOW | + | | TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW |
| | 0x545012D0 | | | 0x545012D0 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMAINFO_CURRENT_FBRD_HIGH | + | | TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH |
| | 0x545012D4 | | | 0x545012D4 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMAINFO_CURRENT_FBWR_LOW | + | | TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW |
| | 0x545012D8 | | | 0x545012D8 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMAINFO_CURRENT_FBWR_HIGH | + | | TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH |
| | 0x545012DC | | | 0x545012DC |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | FALCON_DMAINFO_CTL | + | | TSEC_FALCON_DMAINFO_CTL |
| | 0x545012E0 | | | 0x545012E0 |
| | 0x04 | | | 0x04 |
Line 1,178: |
Line 1,178: |
| |} | | |} |
| | | |
− | === FALCON_IRQSSET === | + | === TSEC_FALCON_IRQSSET === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,184: |
Line 1,184: |
| |- | | |- |
| | 0 | | | 0 |
− | | FALCON_IRQSSET_GPTMR | + | | TSEC_FALCON_IRQSSET_GPTMR |
| |- | | |- |
| | 1 | | | 1 |
− | | FALCON_IRQSSET_WDTMR | + | | TSEC_FALCON_IRQSSET_WDTMR |
| |- | | |- |
| | 2 | | | 2 |
− | | FALCON_IRQSSET_MTHD | + | | TSEC_FALCON_IRQSSET_MTHD |
| |- | | |- |
| | 3 | | | 3 |
− | | FALCON_IRQSSET_CTXSW | + | | TSEC_FALCON_IRQSSET_CTXSW |
| |- | | |- |
| | 4 | | | 4 |
− | | FALCON_IRQSSET_HALT | + | | TSEC_FALCON_IRQSSET_HALT |
| |- | | |- |
| | 5 | | | 5 |
− | | FALCON_IRQSSET_EXTERR | + | | TSEC_FALCON_IRQSSET_EXTERR |
| |- | | |- |
| | 6 | | | 6 |
− | | FALCON_IRQSSET_SWGEN0 | + | | TSEC_FALCON_IRQSSET_SWGEN0 |
| |- | | |- |
| | 7 | | | 7 |
− | | FALCON_IRQSSET_SWGEN1 | + | | TSEC_FALCON_IRQSSET_SWGEN1 |
| |- | | |- |
| | 8-15 | | | 8-15 |
− | | FALCON_IRQSSET_EXT | + | | TSEC_FALCON_IRQSSET_EXT |
| |- | | |- |
| | 16 | | | 16 |
− | | FALCON_IRQSSET_DMA | + | | TSEC_FALCON_IRQSSET_DMA |
| |} | | |} |
| | | |
| Used for setting Falcon's IRQs. | | Used for setting Falcon's IRQs. |
| | | |
− | === FALCON_IRQSCLR === | + | === TSEC_FALCON_IRQSCLR === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,222: |
Line 1,222: |
| |- | | |- |
| | 0 | | | 0 |
− | | FALCON_IRQSCLR_GPTMR | + | | TSEC_FALCON_IRQSCLR_GPTMR |
| |- | | |- |
| | 1 | | | 1 |
− | | FALCON_IRQSCLR_WDTMR | + | | TSEC_FALCON_IRQSCLR_WDTMR |
| |- | | |- |
| | 2 | | | 2 |
− | | FALCON_IRQSCLR_MTHD | + | | TSEC_FALCON_IRQSCLR_MTHD |
| |- | | |- |
| | 3 | | | 3 |
− | | FALCON_IRQSCLR_CTXSW | + | | TSEC_FALCON_IRQSCLR_CTXSW |
| |- | | |- |
| | 4 | | | 4 |
− | | FALCON_IRQSCLR_HALT | + | | TSEC_FALCON_IRQSCLR_HALT |
| |- | | |- |
| | 5 | | | 5 |
− | | FALCON_IRQSCLR_EXTERR | + | | TSEC_FALCON_IRQSCLR_EXTERR |
| |- | | |- |
| | 6 | | | 6 |
− | | FALCON_IRQSCLR_SWGEN0 | + | | TSEC_FALCON_IRQSCLR_SWGEN0 |
| |- | | |- |
| | 7 | | | 7 |
− | | FALCON_IRQSCLR_SWGEN1 | + | | TSEC_FALCON_IRQSCLR_SWGEN1 |
| |- | | |- |
| | 8-15 | | | 8-15 |
− | | FALCON_IRQSCLR_EXT | + | | TSEC_FALCON_IRQSCLR_EXT |
| |- | | |- |
| | 16 | | | 16 |
− | | FALCON_IRQSCLR_DMA | + | | TSEC_FALCON_IRQSCLR_DMA |
| |} | | |} |
| | | |
| Used for clearing Falcon's IRQs. | | Used for clearing Falcon's IRQs. |
| | | |
− | === FALCON_IRQSTAT === | + | === TSEC_FALCON_IRQSTAT === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,260: |
Line 1,260: |
| |- | | |- |
| | 0 | | | 0 |
− | | FALCON_IRQSTAT_GPTMR | + | | TSEC_FALCON_IRQSTAT_GPTMR |
| |- | | |- |
| | 1 | | | 1 |
− | | FALCON_IRQSTAT_WDTMR | + | | TSEC_FALCON_IRQSTAT_WDTMR |
| |- | | |- |
| | 2 | | | 2 |
− | | FALCON_IRQSTAT_MTHD | + | | TSEC_FALCON_IRQSTAT_MTHD |
| |- | | |- |
| | 3 | | | 3 |
− | | FALCON_IRQSTAT_CTXSW | + | | TSEC_FALCON_IRQSTAT_CTXSW |
| |- | | |- |
| | 4 | | | 4 |
− | | FALCON_IRQSTAT_HALT | + | | TSEC_FALCON_IRQSTAT_HALT |
| |- | | |- |
| | 5 | | | 5 |
− | | FALCON_IRQSTAT_EXTERR | + | | TSEC_FALCON_IRQSTAT_EXTERR |
| |- | | |- |
| | 6 | | | 6 |
− | | FALCON_IRQSTAT_SWGEN0 | + | | TSEC_FALCON_IRQSTAT_SWGEN0 |
| |- | | |- |
| | 7 | | | 7 |
− | | FALCON_IRQSTAT_SWGEN1 | + | | TSEC_FALCON_IRQSTAT_SWGEN1 |
| |- | | |- |
| | 8-15 | | | 8-15 |
− | | FALCON_IRQSTAT_EXT | + | | TSEC_FALCON_IRQSTAT_EXT |
| |- | | |- |
| | 16 | | | 16 |
− | | FALCON_IRQSTAT_DMA | + | | TSEC_FALCON_IRQSTAT_DMA |
| |} | | |} |
| | | |
| Used for getting the status of Falcon's IRQs. | | Used for getting the status of Falcon's IRQs. |
| | | |
− | === FALCON_IRQMODE === | + | === TSEC_FALCON_IRQMODE === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,298: |
Line 1,298: |
| |- | | |- |
| | 0 | | | 0 |
− | | FALCON_IRQMODE_LVL_GPTMR | + | | TSEC_FALCON_IRQMODE_LVL_GPTMR |
| |- | | |- |
| | 1 | | | 1 |
− | | FALCON_IRQMODE_LVL_WDTMR | + | | TSEC_FALCON_IRQMODE_LVL_WDTMR |
| |- | | |- |
| | 2 | | | 2 |
− | | FALCON_IRQMODE_LVL_MTHD | + | | TSEC_FALCON_IRQMODE_LVL_MTHD |
| |- | | |- |
| | 3 | | | 3 |
− | | FALCON_IRQMODE_LVL_CTXSW | + | | TSEC_FALCON_IRQMODE_LVL_CTXSW |
| |- | | |- |
| | 4 | | | 4 |
− | | FALCON_IRQMODE_LVL_HALT | + | | TSEC_FALCON_IRQMODE_LVL_HALT |
| |- | | |- |
| | 5 | | | 5 |
− | | FALCON_IRQMODE_LVL_EXTERR | + | | TSEC_FALCON_IRQMODE_LVL_EXTERR |
| |- | | |- |
| | 6 | | | 6 |
− | | FALCON_IRQMODE_LVL_SWGEN0 | + | | TSEC_FALCON_IRQMODE_LVL_SWGEN0 |
| |- | | |- |
| | 7 | | | 7 |
− | | FALCON_IRQMODE_LVL_SWGEN1 | + | | TSEC_FALCON_IRQMODE_LVL_SWGEN1 |
| |- | | |- |
| | 8-15 | | | 8-15 |
− | | FALCON_IRQMODE_LVL_EXT | + | | TSEC_FALCON_IRQMODE_LVL_EXT |
| |- | | |- |
| | 16 | | | 16 |
− | | FALCON_IRQMODE_LVL_DMA | + | | TSEC_FALCON_IRQMODE_LVL_DMA |
| |} | | |} |
| | | |
| Used for changing the mode Falcon's IRQs. A value of 1 means level triggered while a value of 0 means edge triggered. | | Used for changing the mode Falcon's IRQs. A value of 1 means level triggered while a value of 0 means edge triggered. |
| | | |
− | === FALCON_IRQMSET === | + | === TSEC_FALCON_IRQMSET === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,336: |
Line 1,336: |
| |- | | |- |
| | 0 | | | 0 |
− | | FALCON_IRQMSET_GPTMR | + | | TSEC_FALCON_IRQMSET_GPTMR |
| |- | | |- |
| | 1 | | | 1 |
− | | FALCON_IRQMSET_WDTMR | + | | TSEC_FALCON_IRQMSET_WDTMR |
| |- | | |- |
| | 2 | | | 2 |
− | | FALCON_IRQMSET_MTHD | + | | TSEC_FALCON_IRQMSET_MTHD |
| |- | | |- |
| | 3 | | | 3 |
− | | FALCON_IRQMSET_CTXSW | + | | TSEC_FALCON_IRQMSET_CTXSW |
| |- | | |- |
| | 4 | | | 4 |
− | | FALCON_IRQMSET_HALT | + | | TSEC_FALCON_IRQMSET_HALT |
| |- | | |- |
| | 5 | | | 5 |
− | | FALCON_IRQMSET_EXTERR | + | | TSEC_FALCON_IRQMSET_EXTERR |
| |- | | |- |
| | 6 | | | 6 |
− | | FALCON_IRQMSET_SWGEN0 | + | | TSEC_FALCON_IRQMSET_SWGEN0 |
| |- | | |- |
| | 7 | | | 7 |
− | | FALCON_IRQMSET_SWGEN1 | + | | TSEC_FALCON_IRQMSET_SWGEN1 |
| |- | | |- |
| | 8-15 | | | 8-15 |
− | | FALCON_IRQMSET_EXT | + | | TSEC_FALCON_IRQMSET_EXT |
| |- | | |- |
| | 16 | | | 16 |
− | | FALCON_IRQMSET_DMA | + | | TSEC_FALCON_IRQMSET_DMA |
| |} | | |} |
| | | |
| Used for setting the mask for Falcon's IRQs. | | Used for setting the mask for Falcon's IRQs. |
| | | |
− | === FALCON_IRQMCLR === | + | === TSEC_FALCON_IRQMCLR === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,374: |
Line 1,374: |
| |- | | |- |
| | 0 | | | 0 |
− | | FALCON_IRQMCLR_GPTMR | + | | TSEC_FALCON_IRQMCLR_GPTMR |
| |- | | |- |
| | 1 | | | 1 |
− | | FALCON_IRQMCLR_WDTMR | + | | TSEC_FALCON_IRQMCLR_WDTMR |
| |- | | |- |
| | 2 | | | 2 |
− | | FALCON_IRQMCLR_MTHD | + | | TSEC_FALCON_IRQMCLR_MTHD |
| |- | | |- |
| | 3 | | | 3 |
− | | FALCON_IRQMCLR_CTXSW | + | | TSEC_FALCON_IRQMCLR_CTXSW |
| |- | | |- |
| | 4 | | | 4 |
− | | FALCON_IRQMCLR_HALT | + | | TSEC_FALCON_IRQMCLR_HALT |
| |- | | |- |
| | 5 | | | 5 |
− | | FALCON_IRQMCLR_EXTERR | + | | TSEC_FALCON_IRQMCLR_EXTERR |
| |- | | |- |
| | 6 | | | 6 |
− | | FALCON_IRQMCLR_SWGEN0 | + | | TSEC_FALCON_IRQMCLR_SWGEN0 |
| |- | | |- |
| | 7 | | | 7 |
− | | FALCON_IRQMCLR_SWGEN1 | + | | TSEC_FALCON_IRQMCLR_SWGEN1 |
| |- | | |- |
| | 8-15 | | | 8-15 |
− | | FALCON_IRQMCLR_EXT | + | | TSEC_FALCON_IRQMCLR_EXT |
| |- | | |- |
| | 16 | | | 16 |
− | | FALCON_IRQMCLR_DMA | + | | TSEC_FALCON_IRQMCLR_DMA |
| |} | | |} |
| | | |
| Used for clearing the mask for Falcon's IRQs. | | Used for clearing the mask for Falcon's IRQs. |
| | | |
− | === FALCON_IRQMASK === | + | === TSEC_FALCON_IRQMASK === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,412: |
Line 1,412: |
| |- | | |- |
| | 0 | | | 0 |
− | | FALCON_IRQMASK_GPTMR | + | | TSEC_FALCON_IRQMASK_GPTMR |
| |- | | |- |
| | 1 | | | 1 |
− | | FALCON_IRQMASK_WDTMR | + | | TSEC_FALCON_IRQMASK_WDTMR |
| |- | | |- |
| | 2 | | | 2 |
− | | FALCON_IRQMASK_MTHD | + | | TSEC_FALCON_IRQMASK_MTHD |
| |- | | |- |
| | 3 | | | 3 |
− | | FALCON_IRQMASK_CTXSW | + | | TSEC_FALCON_IRQMASK_CTXSW |
| |- | | |- |
| | 4 | | | 4 |
− | | FALCON_IRQMASK_HALT | + | | TSEC_FALCON_IRQMASK_HALT |
| |- | | |- |
| | 5 | | | 5 |
− | | FALCON_IRQMASK_EXTERR | + | | TSEC_FALCON_IRQMASK_EXTERR |
| |- | | |- |
| | 6 | | | 6 |
− | | FALCON_IRQMASK_SWGEN0 | + | | TSEC_FALCON_IRQMASK_SWGEN0 |
| |- | | |- |
| | 7 | | | 7 |
− | | FALCON_IRQMASK_SWGEN1 | + | | TSEC_FALCON_IRQMASK_SWGEN1 |
| |- | | |- |
| | 8-15 | | | 8-15 |
− | | FALCON_IRQMASK_EXT | + | | TSEC_FALCON_IRQMASK_EXT |
| |- | | |- |
| | 16 | | | 16 |
− | | FALCON_IRQMASK_DMA | + | | TSEC_FALCON_IRQMASK_DMA |
| |} | | |} |
| | | |
| Used for getting the value of the mask for Falcon's IRQs. | | Used for getting the value of the mask for Falcon's IRQs. |
| | | |
− | === FALCON_IRQDEST === | + | === TSEC_FALCON_IRQDEST === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,450: |
Line 1,450: |
| |- | | |- |
| | 0 | | | 0 |
− | | FALCON_IRQDEST_HOST_GPTMR | + | | TSEC_FALCON_IRQDEST_HOST_GPTMR |
| |- | | |- |
| | 1 | | | 1 |
− | | FALCON_IRQDEST_HOST_WDTMR | + | | TSEC_FALCON_IRQDEST_HOST_WDTMR |
| |- | | |- |
| | 2 | | | 2 |
− | | FALCON_IRQDEST_HOST_MTHD | + | | TSEC_FALCON_IRQDEST_HOST_MTHD |
| |- | | |- |
| | 3 | | | 3 |
− | | FALCON_IRQDEST_HOST_CTXSW | + | | TSEC_FALCON_IRQDEST_HOST_CTXSW |
| |- | | |- |
| | 4 | | | 4 |
− | | FALCON_IRQDEST_HOST_HALT | + | | TSEC_FALCON_IRQDEST_HOST_HALT |
| |- | | |- |
| | 5 | | | 5 |
− | | FALCON_IRQDEST_HOST_EXTERR | + | | TSEC_FALCON_IRQDEST_HOST_EXTERR |
| |- | | |- |
| | 6 | | | 6 |
− | | FALCON_IRQDEST_HOST_SWGEN0 | + | | TSEC_FALCON_IRQDEST_HOST_SWGEN0 |
| |- | | |- |
| | 7 | | | 7 |
− | | FALCON_IRQDEST_HOST_SWGEN1 | + | | TSEC_FALCON_IRQDEST_HOST_SWGEN1 |
| |- | | |- |
| | 8-15 | | | 8-15 |
− | | FALCON_IRQDEST_HOST_EXT | + | | TSEC_FALCON_IRQDEST_HOST_EXT |
| |- | | |- |
| | 16 | | | 16 |
− | | FALCON_IRQDEST_TARGET_GPTMR | + | | TSEC_FALCON_IRQDEST_TARGET_GPTMR |
| |- | | |- |
| | 17 | | | 17 |
− | | FALCON_IRQDEST_TARGET_WDTMR | + | | TSEC_FALCON_IRQDEST_TARGET_WDTMR |
| |- | | |- |
| | 18 | | | 18 |
− | | FALCON_IRQDEST_TARGET_MTHD | + | | TSEC_FALCON_IRQDEST_TARGET_MTHD |
| |- | | |- |
| | 19 | | | 19 |
− | | FALCON_IRQDEST_TARGET_CTXSW | + | | TSEC_FALCON_IRQDEST_TARGET_CTXSW |
| |- | | |- |
| | 20 | | | 20 |
− | | FALCON_IRQDEST_TARGET_HALT | + | | TSEC_FALCON_IRQDEST_TARGET_HALT |
| |- | | |- |
| | 21 | | | 21 |
− | | FALCON_IRQDEST_TARGET_EXTERR | + | | TSEC_FALCON_IRQDEST_TARGET_EXTERR |
| |- | | |- |
| | 22 | | | 22 |
− | | FALCON_IRQDEST_TARGET_SWGEN0 | + | | TSEC_FALCON_IRQDEST_TARGET_SWGEN0 |
| |- | | |- |
| | 23 | | | 23 |
− | | FALCON_IRQDEST_TARGET_SWGEN1 | + | | TSEC_FALCON_IRQDEST_TARGET_SWGEN1 |
| |- | | |- |
| | 24-31 | | | 24-31 |
− | | FALCON_IRQDEST_TARGET_EXT | + | | TSEC_FALCON_IRQDEST_TARGET_EXT |
| |} | | |} |
| | | |
| Used for routing Falcon's IRQs. | | Used for routing Falcon's IRQs. |
| | | |
− | === FALCON_IRQDEST2 === | + | === TSEC_FALCON_IRQDEST2 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,512: |
Line 1,512: |
| |- | | |- |
| | 0 | | | 0 |
− | | FALCON_IRQDEST2_HOST_DMA | + | | TSEC_FALCON_IRQDEST2_HOST_DMA |
| |- | | |- |
| | 16 | | | 16 |
− | | FALCON_IRQDEST2_TARGET_DMA | + | | TSEC_FALCON_IRQDEST2_TARGET_DMA |
| |} | | |} |
| | | |
| Used for routing Falcon's IRQs. | | Used for routing Falcon's IRQs. |
| | | |
− | === FALCON_MAILBOX0 === | + | === TSEC_FALCON_MAILBOX0 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,526: |
Line 1,526: |
| |- | | |- |
| | 0-31 | | | 0-31 |
− | | FALCON_MAILBOX0_DATA | + | | TSEC_FALCON_MAILBOX0_DATA |
| |} | | |} |
| | | |
| Scratch register for reading/writing data to Falcon. | | Scratch register for reading/writing data to Falcon. |
| | | |
− | === FALCON_MAILBOX1 === | + | === TSEC_FALCON_MAILBOX1 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,537: |
Line 1,537: |
| |- | | |- |
| | 0-31 | | | 0-31 |
− | | FALCON_MAILBOX1_DATA | + | | TSEC_FALCON_MAILBOX1_DATA |
| |} | | |} |
| | | |
| Scratch register for reading/writing data to Falcon. | | Scratch register for reading/writing data to Falcon. |
| | | |
− | === FALCON_ITFEN === | + | === TSEC_FALCON_ITFEN === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,548: |
Line 1,548: |
| |- | | |- |
| | 0 | | | 0 |
− | | FALCON_ITFEN_CTXEN | + | | TSEC_FALCON_ITFEN_CTXEN |
| |- | | |- |
| | 1 | | | 1 |
− | | FALCON_ITFEN_MTHDEN | + | | TSEC_FALCON_ITFEN_MTHDEN |
| |} | | |} |
| | | |
| Used for enabling/disabling Falcon interfaces. | | Used for enabling/disabling Falcon interfaces. |
| | | |
− | === FALCON_IDLESTATE === | + | === TSEC_FALCON_IDLESTATE === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,562: |
Line 1,562: |
| |- | | |- |
| | 0 | | | 0 |
− | | FALCON_IDLESTATE_FALCON_BUSY | + | | TSEC_FALCON_IDLESTATE_FALCON_BUSY |
| |- | | |- |
| | 1-15 | | | 1-15 |
− | | FALCON_IDLESTATE_EXT_BUSY | + | | TSEC_FALCON_IDLESTATE_EXT_BUSY |
| |} | | |} |
| | | |
| Used for detecting if Falcon is busy or not. | | Used for detecting if Falcon is busy or not. |
| | | |
− | === FALCON_DEBUG1 === | + | === TSEC_FALCON_DEBUG1 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,576: |
Line 1,576: |
| |- | | |- |
| | 0-15 | | | 0-15 |
− | | FALCON_DEBUG1_MTHD_DRAIN_TIME | + | | TSEC_FALCON_DEBUG1_MTHD_DRAIN_TIME |
| |- | | |- |
| | 16 | | | 16 |
− | | FALCON_DEBUG1_CTXSW_MODE | + | | TSEC_FALCON_DEBUG1_CTXSW_MODE |
| |- | | |- |
| | 17 | | | 17 |
− | | FALCON_DEBUG1_TRACE_FORMAT | + | | TSEC_FALCON_DEBUG1_TRACE_FORMAT |
| |} | | |} |
| | | |
− | === FALCON_DEBUGINFO === | + | === TSEC_FALCON_DEBUGINFO === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,591: |
Line 1,591: |
| |- | | |- |
| | 0-31 | | | 0-31 |
− | | FALCON_DEBUGINFO_DATA | + | | TSEC_FALCON_DEBUGINFO_DATA |
| |} | | |} |
| | | |
Line 1,598: |
Line 1,598: |
| [6.0.0+] [[NV_services|nvservices]] sets this to 0x8005FF00 >> 8 (physical DRAM address inside the GPU UCODE carveout) before starting the nvhost_tsec firmware. | | [6.0.0+] [[NV_services|nvservices]] sets this to 0x8005FF00 >> 8 (physical DRAM address inside the GPU UCODE carveout) before starting the nvhost_tsec firmware. |
| | | |
− | === FALCON_EXCI === | + | === TSEC_FALCON_EXCI === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,604: |
Line 1,604: |
| |- | | |- |
| | 0-19 | | | 0-19 |
− | | FALCON_EXCI_EXPC | + | | TSEC_FALCON_EXCI_EXPC |
| |- | | |- |
| | 20-23 | | | 20-23 |
− | | FALCON_EXCI_EXCAUSE | + | | TSEC_FALCON_EXCI_EXCAUSE |
| 0x00: TRAP0 | | 0x00: TRAP0 |
| 0x01: TRAP1 | | 0x01: TRAP1 |
Line 1,621: |
Line 1,621: |
| Contains information about raised exceptions. | | Contains information about raised exceptions. |
| | | |
− | === FALCON_SVEC_SPR === | + | === TSEC_FALCON_SVEC_SPR === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,627: |
Line 1,627: |
| |- | | |- |
| | 18 | | | 18 |
− | | FALCON_SVEC_SPR_SIGPASS | + | | TSEC_FALCON_SVEC_SPR_SIGPASS |
| |} | | |} |
| | | |
− | === FALCON_RSTAT0 === | + | === TSEC_FALCON_RSTAT0 === |
− | Mirror of the [[#FALCON_ICD_RDATA|ICD status register 0]]. | + | Mirror of the [[#TSEC_FALCON_ICD_RDATA|ICD status register 0]]. |
| | | |
− | === FALCON_RSTAT3 === | + | === TSEC_FALCON_RSTAT3 === |
− | Mirror of the [[#FALCON_ICD_RDATA|ICD status register 3]]. | + | Mirror of the [[#TSEC_FALCON_ICD_RDATA|ICD status register 3]]. |
| | | |
− | === FALCON_CPUCTL === | + | === TSEC_FALCON_CPUCTL === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,642: |
Line 1,642: |
| |- | | |- |
| | 0 | | | 0 |
− | | FALCON_CPUCTL_IINVAL | + | | TSEC_FALCON_CPUCTL_IINVAL |
| |- | | |- |
| | 1 | | | 1 |
− | | FALCON_CPUCTL_STARTCPU | + | | TSEC_FALCON_CPUCTL_STARTCPU |
| |- | | |- |
| | 2 | | | 2 |
− | | FALCON_CPUCTL_SRESET | + | | TSEC_FALCON_CPUCTL_SRESET |
| |- | | |- |
| | 3 | | | 3 |
− | | FALCON_CPUCTL_HRESET | + | | TSEC_FALCON_CPUCTL_HRESET |
| |- | | |- |
| | 4 | | | 4 |
− | | FALCON_CPUCTL_HALTED | + | | TSEC_FALCON_CPUCTL_HALTED |
| |- | | |- |
| | 5 | | | 5 |
− | | FALCON_CPUCTL_STOPPED | + | | TSEC_FALCON_CPUCTL_STOPPED |
| |- | | |- |
| | 6 | | | 6 |
− | | FALCON_CPUCTL_ALIAS_EN | + | | TSEC_FALCON_CPUCTL_ALIAS_EN |
| |} | | |} |
| | | |
| Used for signaling the Falcon CPU. | | Used for signaling the Falcon CPU. |
| | | |
− | === FALCON_BOOTVEC === | + | === TSEC_FALCON_BOOTVEC === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,671: |
Line 1,671: |
| |- | | |- |
| | 0-31 | | | 0-31 |
− | | FALCON_BOOTVEC_VEC | + | | TSEC_FALCON_BOOTVEC_VEC |
| |} | | |} |
| | | |
| Takes the Falcon's boot vector address. | | Takes the Falcon's boot vector address. |
| | | |
− | === FALCON_HWCFG === | + | === TSEC_FALCON_HWCFG === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,682: |
Line 1,682: |
| |- | | |- |
| | 0-8 | | | 0-8 |
− | | FALCON_HWCFG_IMEM_SIZE | + | | TSEC_FALCON_HWCFG_IMEM_SIZE |
| |- | | |- |
| | 9-17 | | | 9-17 |
− | | FALCON_HWCFG_DMEM_SIZE | + | | TSEC_FALCON_HWCFG_DMEM_SIZE |
| |- | | |- |
| | 18-26 | | | 18-26 |
− | | FALCON_HWCFG_METHODFIFO_DEPTH | + | | TSEC_FALCON_HWCFG_METHODFIFO_DEPTH |
| |- | | |- |
| | 27-31 | | | 27-31 |
− | | FALCON_HWCFG_DMAQUEUE_DEPTH | + | | TSEC_FALCON_HWCFG_DMAQUEUE_DEPTH |
| |} | | |} |
| | | |
− | === FALCON_DMACTL === | + | === TSEC_FALCON_DMACTL === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,700: |
Line 1,700: |
| |- | | |- |
| | 0 | | | 0 |
− | | FALCON_DMACTL_REQUIRE_CTX | + | | TSEC_FALCON_DMACTL_REQUIRE_CTX |
| |- | | |- |
| | 1 | | | 1 |
− | | FALCON_DMACTL_DMEM_SCRUBBING | + | | TSEC_FALCON_DMACTL_DMEM_SCRUBBING |
| |- | | |- |
| | 2 | | | 2 |
− | | FALCON_DMACTL_IMEM_SCRUBBING | + | | TSEC_FALCON_DMACTL_IMEM_SCRUBBING |
| |- | | |- |
| | 3-6 | | | 3-6 |
− | | FALCON_DMACTL_DMAQ_NUM | + | | TSEC_FALCON_DMACTL_DMAQ_NUM |
| |- | | |- |
| | 7 | | | 7 |
− | | FALCON_DMACTL_SECURE_STAT | + | | TSEC_FALCON_DMACTL_SECURE_STAT |
| |} | | |} |
| | | |
| Used for configuring the Falcon's DMA engine. | | Used for configuring the Falcon's DMA engine. |
| | | |
− | === FALCON_DMATRFBASE === | + | === TSEC_FALCON_DMATRFBASE === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,723: |
Line 1,723: |
| |- | | |- |
| | 0-31 | | | 0-31 |
− | | FALCON_DMATRFBASE_BASE | + | | TSEC_FALCON_DMATRFBASE_BASE |
| |} | | |} |
| | | |
| Base address of the external memory buffer, shifted right by 8. | | Base address of the external memory buffer, shifted right by 8. |
| | | |
− | The current transfer address is calculated by adding [[#FALCON_DMATRFFBOFFS|FALCON_DMATRFFBOFFS]] to the base. | + | The current transfer address is calculated by adding [[#TSEC_FALCON_DMATRFFBOFFS|TSEC_FALCON_DMATRFFBOFFS]] to the base. |
| | | |
− | === FALCON_DMATRFMOFFS === | + | === TSEC_FALCON_DMATRFMOFFS === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,736: |
Line 1,736: |
| |- | | |- |
| | 0-15 | | | 0-15 |
− | | FALCON_DMATRFMOFFS_OFFS | + | | TSEC_FALCON_DMATRFMOFFS_OFFS |
| |} | | |} |
| | | |
Line 1,742: |
Line 1,742: |
| For transfers to IMEM: the destination virtual IMEM page. | | For transfers to IMEM: the destination virtual IMEM page. |
| | | |
− | === FALCON_DMATRFCMD === | + | === TSEC_FALCON_DMATRFCMD === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,748: |
Line 1,748: |
| |- | | |- |
| | 0 | | | 0 |
− | | FALCON_DMATRFCMD_FULL | + | | TSEC_FALCON_DMATRFCMD_FULL |
| |- | | |- |
| | 1 | | | 1 |
− | | FALCON_DMATRFCMD_IDLE | + | | TSEC_FALCON_DMATRFCMD_IDLE |
| |- | | |- |
| | 2-3 | | | 2-3 |
− | | FALCON_DMATRFCMD_SEC | + | | TSEC_FALCON_DMATRFCMD_SEC |
| |- | | |- |
| | 4 | | | 4 |
− | | FALCON_DMATRFCMD_IMEM | + | | TSEC_FALCON_DMATRFCMD_IMEM |
| |- | | |- |
| | 5 | | | 5 |
− | | FALCON_DMATRFCMD_WRITE | + | | TSEC_FALCON_DMATRFCMD_WRITE |
| |- | | |- |
| | 8-10 | | | 8-10 |
− | | FALCON_DMATRFCMD_SIZE | + | | TSEC_FALCON_DMATRFCMD_SIZE |
| |- | | |- |
| | 12-14 | | | 12-14 |
− | | FALCON_DMATRFCMD_CTXDMA | + | | TSEC_FALCON_DMATRFCMD_CTXDMA |
| |} | | |} |
| | | |
| Used for configuring DMA transfers. | | Used for configuring DMA transfers. |
| | | |
− | === FALCON_DMATRFFBOFFS === | + | === TSEC_FALCON_DMATRFFBOFFS === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,777: |
Line 1,777: |
| |- | | |- |
| | 0-15 | | | 0-15 |
− | | FALCON_DMATRFFBOFFS_OFFS | + | | TSEC_FALCON_DMATRFFBOFFS_OFFS |
| |} | | |} |
| | | |
| For transfers to IMEM: the destination physical IMEM page. | | For transfers to IMEM: the destination physical IMEM page. |
| | | |
− | === FALCON_DMAPOLL_FB === | + | === TSEC_FALCON_DMAPOLL_FB === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,788: |
Line 1,788: |
| |- | | |- |
| | 0 | | | 0 |
− | | FALCON_DMAPOLL_FB_FENCE_ACTIVE | + | | TSEC_FALCON_DMAPOLL_FB_FENCE_ACTIVE |
| |- | | |- |
| | 1 | | | 1 |
− | | FALCON_DMAPOLL_FB_DMA_ACTIVE | + | | TSEC_FALCON_DMAPOLL_FB_DMA_ACTIVE |
| |- | | |- |
| | 4 | | | 4 |
− | | FALCON_DMAPOLL_FB_CFG_R_FENCE | + | | TSEC_FALCON_DMAPOLL_FB_CFG_R_FENCE |
| |- | | |- |
| | 5 | | | 5 |
− | | FALCON_DMAPOLL_FB_CFG_W_FENCE | + | | TSEC_FALCON_DMAPOLL_FB_CFG_W_FENCE |
| |- | | |- |
| | 16-23 | | | 16-23 |
− | | FALCON_DMAPOLL_FB_WCOUNT | + | | TSEC_FALCON_DMAPOLL_FB_WCOUNT |
| |- | | |- |
| | 24-31 | | | 24-31 |
− | | FALCON_DMAPOLL_FB_RCOUNT | + | | TSEC_FALCON_DMAPOLL_FB_RCOUNT |
| |} | | |} |
| | | |
| Contains the status of a DMA transfer between the Falcon and external memory. | | Contains the status of a DMA transfer between the Falcon and external memory. |
| | | |
− | === FALCON_DMAPOLL_CP === | + | === TSEC_FALCON_DMAPOLL_CP === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,814: |
Line 1,814: |
| |- | | |- |
| | 0 | | | 0 |
− | | FALCON_DMAPOLL_CP_FENCE_ACTIVE | + | | TSEC_FALCON_DMAPOLL_CP_FENCE_ACTIVE |
| |- | | |- |
| | 1 | | | 1 |
− | | FALCON_DMAPOLL_CP_DMA_ACTIVE | + | | TSEC_FALCON_DMAPOLL_CP_DMA_ACTIVE |
| |- | | |- |
| | 4 | | | 4 |
− | | FALCON_DMAPOLL_CP_CFG_R_FENCE | + | | TSEC_FALCON_DMAPOLL_CP_CFG_R_FENCE |
| |- | | |- |
| | 5 | | | 5 |
− | | FALCON_DMAPOLL_CP_CFG_W_FENCE | + | | TSEC_FALCON_DMAPOLL_CP_CFG_W_FENCE |
| |- | | |- |
| | 16-23 | | | 16-23 |
− | | FALCON_DMAPOLL_CP_WCOUNT | + | | TSEC_FALCON_DMAPOLL_CP_WCOUNT |
| |- | | |- |
| | 24-31 | | | 24-31 |
− | | FALCON_DMAPOLL_CP_RCOUNT | + | | TSEC_FALCON_DMAPOLL_CP_RCOUNT |
| |} | | |} |
| | | |
| Contains the status of a DMA transfer between the Falcon and the SCP. | | Contains the status of a DMA transfer between the Falcon and the SCP. |
| | | |
− | === FALCON_HWCFG1 === | + | === TSEC_FALCON_HWCFG1 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,840: |
Line 1,840: |
| |- | | |- |
| | 0-3 | | | 0-3 |
− | | FALCON_HWCFG1_CORE_REV | + | | TSEC_FALCON_HWCFG1_CORE_REV |
| |- | | |- |
| | 4-5 | | | 4-5 |
− | | FALCON_HWCFG1_SECURITY_MODEL | + | | TSEC_FALCON_HWCFG1_SECURITY_MODEL |
| |- | | |- |
| | 6-7 | | | 6-7 |
− | | FALCON_HWCFG1_CORE_REV_SUBVERSION | + | | TSEC_FALCON_HWCFG1_CORE_REV_SUBVERSION |
| |- | | |- |
| | 8-11 | | | 8-11 |
− | | FALCON_HWCFG1_IMEM_PORTS | + | | TSEC_FALCON_HWCFG1_IMEM_PORTS |
| |- | | |- |
| | 12-15 | | | 12-15 |
− | | FALCON_HWCFG1_DMEM_PORTS | + | | TSEC_FALCON_HWCFG1_DMEM_PORTS |
| |- | | |- |
| | 16-20 | | | 16-20 |
− | | FALCON_HWCFG1_TAG_WIDTH | + | | TSEC_FALCON_HWCFG1_TAG_WIDTH |
| |- | | |- |
| | 27 | | | 27 |
− | | FALCON_HWCFG1_DBG_PRIV_BUS | + | | TSEC_FALCON_HWCFG1_DBG_PRIV_BUS |
| |- | | |- |
| | 28 | | | 28 |
− | | FALCON_HWCFG1_CSB_SIZE_16M | + | | TSEC_FALCON_HWCFG1_CSB_SIZE_16M |
| |- | | |- |
| | 29 | | | 29 |
− | | FALCON_HWCFG1_PRIV_DIRECT | + | | TSEC_FALCON_HWCFG1_PRIV_DIRECT |
| |- | | |- |
| | 30 | | | 30 |
− | | FALCON_HWCFG1_DMEM_APERTURES | + | | TSEC_FALCON_HWCFG1_DMEM_APERTURES |
| |- | | |- |
| | 31 | | | 31 |
− | | FALCON_HWCFG1_IMEM_AUTOFILL | + | | TSEC_FALCON_HWCFG1_IMEM_AUTOFILL |
| |} | | |} |
| | | |
− | === FALCON_IMCTL === | + | === TSEC_FALCON_IMCTL === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,879: |
Line 1,879: |
| |- | | |- |
| | 0-23 | | | 0-23 |
− | | FALCON_IMCTL_ADDR_BLK | + | | TSEC_FALCON_IMCTL_ADDR_BLK |
| |- | | |- |
| | 24-26 | | | 24-26 |
− | | FALCON_IMCTL_CMD | + | | TSEC_FALCON_IMCTL_CMD |
| 0x00: NOP | | 0x00: NOP |
| 0x01: IMINV (ITLB) | | 0x01: IMINV (ITLB) |
Line 1,892: |
Line 1,892: |
| Controls the Falcon TLB. | | Controls the Falcon TLB. |
| | | |
− | === FALCON_IMSTAT === | + | === TSEC_FALCON_IMSTAT === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,898: |
Line 1,898: |
| |- | | |- |
| | 0-31 | | | 0-31 |
− | | FALCON_IMSTAT_VAL | + | | TSEC_FALCON_IMSTAT_VAL |
| |} | | |} |
| | | |
− | Returns the result of the last command from [[#FALCON_IMCTL|FALCON_IMCTL]]. | + | Returns the result of the last command from [[#TSEC_FALCON_IMCTL|TSEC_FALCON_IMCTL]]. |
| | | |
− | === FALCON_TRACEIDX === | + | === TSEC_FALCON_TRACEIDX === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,909: |
Line 1,909: |
| |- | | |- |
| | 0-7 | | | 0-7 |
− | | FALCON_TRACEIDX_IDX | + | | TSEC_FALCON_TRACEIDX_IDX |
| |- | | |- |
| | 16-23 | | | 16-23 |
− | | FALCON_TRACEIDX_MAXIDX | + | | TSEC_FALCON_TRACEIDX_MAXIDX |
| |- | | |- |
| | 24-31 | | | 24-31 |
− | | FALCON_TRACEIDX_CNT | + | | TSEC_FALCON_TRACEIDX_CNT |
| |} | | |} |
| | | |
− | Controls the index for tracing with [[#FALCON_TRACEPC|FALCON_TRACEPC]]. | + | Controls the index for tracing with [[#TSEC_FALCON_TRACEPC|TSEC_FALCON_TRACEPC]]. |
| | | |
− | === FALCON_TRACEPC === | + | === TSEC_FALCON_TRACEPC === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,926: |
Line 1,926: |
| |- | | |- |
| | 0-23 | | | 0-23 |
− | | FALCON_TRACEPC_PC | + | | TSEC_FALCON_TRACEPC_PC |
| |} | | |} |
| | | |
| Returns the PC of the last call or branch executed. | | Returns the PC of the last call or branch executed. |
| | | |
− | === FALCON_IMEMC0 === | + | === TSEC_FALCON_IMEMC0 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,937: |
Line 1,937: |
| |- | | |- |
| | 2-7 | | | 2-7 |
− | | FALCON_IMEMC_OFFS | + | | TSEC_FALCON_IMEMC_OFFS |
| |- | | |- |
| | 8-15 | | | 8-15 |
− | | FALCON_IMEMC_BLK | + | | TSEC_FALCON_IMEMC_BLK |
| |- | | |- |
| | 24 | | | 24 |
− | | FALCON_IMEMC_AINCW | + | | TSEC_FALCON_IMEMC_AINCW |
| |- | | |- |
| | 25 | | | 25 |
− | | FALCON_IMEMC_AINCR | + | | TSEC_FALCON_IMEMC_AINCR |
| |- | | |- |
| | 28 | | | 28 |
− | | FALCON_IMEMC_SECURE | + | | TSEC_FALCON_IMEMC_SECURE |
| |- | | |- |
| | 29 | | | 29 |
− | | FALCON_IMEMC_SEC_ATOMIC | + | | TSEC_FALCON_IMEMC_SEC_ATOMIC |
| |- | | |- |
| | 30 | | | 30 |
− | | FALCON_IMEMC_SEC_WR_VIO | + | | TSEC_FALCON_IMEMC_SEC_WR_VIO |
| |- | | |- |
| | 31 | | | 31 |
− | | FALCON_IMEMC_SEC_LOCK | + | | TSEC_FALCON_IMEMC_SEC_LOCK |
| |} | | |} |
| | | |
| Used for configuring access to Falcon's IMEM. | | Used for configuring access to Falcon's IMEM. |
| | | |
− | === FALCON_IMEMD0 === | + | === TSEC_FALCON_IMEMD0 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,969: |
Line 1,969: |
| |- | | |- |
| | 0-31 | | | 0-31 |
− | | FALCON_IMEMD_DATA | + | | TSEC_FALCON_IMEMD_DATA |
| |} | | |} |
| | | |
| Returns or takes the value for an IMEM read/write operation. | | Returns or takes the value for an IMEM read/write operation. |
| | | |
− | === FALCON_IMEMT0 === | + | === TSEC_FALCON_IMEMT0 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,980: |
Line 1,980: |
| |- | | |- |
| | 0-15 | | | 0-15 |
− | | FALCON_IMEMT_TAG | + | | TSEC_FALCON_IMEMT_TAG |
| |} | | |} |
| | | |
| Returns or takes the virtual page index for an IMEM read/write operation. | | Returns or takes the virtual page index for an IMEM read/write operation. |
| | | |
− | === FALCON_DMEMC0 === | + | === TSEC_FALCON_DMEMC0 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,991: |
Line 1,991: |
| |- | | |- |
| | 2-7 | | | 2-7 |
− | | FALCON_DMEMC_OFFS | + | | TSEC_FALCON_DMEMC_OFFS |
| |- | | |- |
| | 8-15 | | | 8-15 |
− | | FALCON_DMEMC_BLK | + | | TSEC_FALCON_DMEMC_BLK |
| |- | | |- |
| | 24 | | | 24 |
− | | FALCON_DMEMC_AINCW | + | | TSEC_FALCON_DMEMC_AINCW |
| |- | | |- |
| | 25 | | | 25 |
− | | FALCON_DMEMC_AINCR | + | | TSEC_FALCON_DMEMC_AINCR |
| |} | | |} |
| | | |
| Used for configuring access to Falcon's DMEM. | | Used for configuring access to Falcon's DMEM. |
| | | |
− | === FALCON_DMEMD0 === | + | === TSEC_FALCON_DMEMD0 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 2,011: |
Line 2,011: |
| |- | | |- |
| | 0-31 | | | 0-31 |
− | | FALCON_DMEMD_DATA | + | | TSEC_FALCON_DMEMD_DATA |
| |} | | |} |
| | | |
| Returns or takes the value for a DMEM read/write operation. | | Returns or takes the value for a DMEM read/write operation. |
| | | |
− | === FALCON_ICD_CMD === | + | === TSEC_FALCON_ICD_CMD === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 2,022: |
Line 2,022: |
| |- | | |- |
| | 0-3 | | | 0-3 |
− | | FALCON_ICD_CMD_OPC | + | | TSEC_FALCON_ICD_CMD_OPC |
| 0x00: STOP | | 0x00: STOP |
| 0x01: RUN (run from PC) | | 0x01: RUN (run from PC) |
Line 2,041: |
Line 2,041: |
| |- | | |- |
| | 6-7 | | | 6-7 |
− | | FALCON_ICD_CMD_SZ | + | | TSEC_FALCON_ICD_CMD_SZ |
| 0x00: B (byte) | | 0x00: B (byte) |
| 0x01: HW (half word) | | 0x01: HW (half word) |
Line 2,047: |
Line 2,047: |
| |- | | |- |
| | 8-12 | | | 8-12 |
− | | FALCON_ICD_CMD_IDX | + | | TSEC_FALCON_ICD_CMD_IDX |
| 0x00: REG0 | RSTAT0 | WB0 | | 0x00: REG0 | RSTAT0 | WB0 |
| 0x01: REG1 | RSTAT1 | WB1 | | 0x01: REG1 | RSTAT1 | WB1 |
Line 2,082: |
Line 2,082: |
| |- | | |- |
| | 14 | | | 14 |
− | | FALCON_ICD_CMD_ERROR | + | | TSEC_FALCON_ICD_CMD_ERROR |
| |- | | |- |
| | 15 | | | 15 |
− | | FALCON_ICD_CMD_RDVLD | + | | TSEC_FALCON_ICD_CMD_RDVLD |
| |- | | |- |
| | 16-31 | | | 16-31 |
− | | FALCON_ICD_CMD_PARM | + | | TSEC_FALCON_ICD_CMD_PARM |
| 0x0001: EMASK_TRAP0 | | 0x0001: EMASK_TRAP0 |
| 0x0002: EMASK_TRAP1 | | 0x0002: EMASK_TRAP1 |
Line 2,109: |
Line 2,109: |
| Used for sending commands to the Falcon's in-chip debugger. | | Used for sending commands to the Falcon's in-chip debugger. |
| | | |
− | === FALCON_ICD_ADDR === | + | === TSEC_FALCON_ICD_ADDR === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 2,115: |
Line 2,115: |
| |- | | |- |
| | 0-31 | | | 0-31 |
− | | FALCON_ICD_ADDR_ADDR | + | | TSEC_FALCON_ICD_ADDR_ADDR |
| |} | | |} |
| | | |
| Takes the target address for the Falcon's in-chip debugger. | | Takes the target address for the Falcon's in-chip debugger. |
| | | |
− | === FALCON_ICD_WDATA === | + | === TSEC_FALCON_ICD_WDATA === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 2,126: |
Line 2,126: |
| |- | | |- |
| | 0-31 | | | 0-31 |
− | | FALCON_ICD_WDATA_DATA | + | | TSEC_FALCON_ICD_WDATA_DATA |
| |} | | |} |
| | | |
| Takes the data for writing using the Falcon's in-chip debugger. | | Takes the data for writing using the Falcon's in-chip debugger. |
| | | |
− | === FALCON_ICD_RDATA === | + | === TSEC_FALCON_ICD_RDATA === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 2,137: |
Line 2,137: |
| |- | | |- |
| | 0-31 | | | 0-31 |
− | | FALCON_ICD_RDATA_DATA | + | | TSEC_FALCON_ICD_RDATA_DATA |
| |} | | |} |
| | | |
Line 2,417: |
Line 2,417: |
| |} | | |} |
| | | |
− | === FALCON_SCTL === | + | === TSEC_FALCON_SCTL === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 2,423: |
Line 2,423: |
| |- | | |- |
| | 0-1 | | | 0-1 |
− | | FALCON_SCTL_SEC_MODE | + | | TSEC_FALCON_SCTL_SEC_MODE |
| 0: Non-secure | | 0: Non-secure |
| 1: Light Secure | | 1: Light Secure |
Line 2,429: |
Line 2,429: |
| |- | | |- |
| | 4-5 | | | 4-5 |
− | | FALCON_SCTL_OLD_SEC_MODE | + | | TSEC_FALCON_SCTL_OLD_SEC_MODE |
| 0: Non-secure | | 0: Non-secure |
| 1: Light Secure | | 1: Light Secure |
Line 2,441: |
Line 2,441: |
| |} | | |} |
| | | |
− | === FALCON_SSTAT === | + | === TSEC_FALCON_SSTAT === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 2,450: |
Line 2,450: |
| |} | | |} |
| | | |
− | === FALCON_SPROT_IMEM === | + | === TSEC_FALCON_SPROT_IMEM === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 2,464: |
Line 2,464: |
| Controls accesses to Falcon IMEM. | | Controls accesses to Falcon IMEM. |
| | | |
− | === FALCON_SPROT_DMEM === | + | === TSEC_FALCON_SPROT_DMEM === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 2,478: |
Line 2,478: |
| Controls accesses to Falcon DMEM. | | Controls accesses to Falcon DMEM. |
| | | |
− | === FALCON_SPROT_CPUCTL === | + | === TSEC_FALCON_SPROT_CPUCTL === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 2,490: |
Line 2,490: |
| |} | | |} |
| | | |
− | Controls accesses to the [[#FALCON_CPUCTL|FALCON_CPUCTL]] register. | + | Controls accesses to the [[#TSEC_FALCON_CPUCTL|TSEC_FALCON_CPUCTL]] register. |
| | | |
− | === FALCON_SPROT_MISC === | + | === TSEC_FALCON_SPROT_MISC === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 2,505: |
Line 2,505: |
| | | |
| Controls accesses to the following registers: | | Controls accesses to the following registers: |
− | * FALCON_PRIVSTATE | + | * TSEC_FALCON_PRIVSTATE |
− | * FALCON_SFTRESET | + | * TSEC_FALCON_SFTRESET |
− | * FALCON_ADDR | + | * TSEC_FALCON_ADDR |
− | * [[#FALCON_DMACTL|FALCON_DMACTL]] | + | * [[#TSEC_FALCON_DMACTL|TSEC_FALCON_DMACTL]] |
− | * [[#FALCON_IMCTL|FALCON_IMCTL]] | + | * [[#TSEC_FALCON_IMCTL|TSEC_FALCON_IMCTL]] |
− | * [[#FALCON_IMSTAT|FALCON_IMSTAT]] | + | * [[#TSEC_FALCON_IMSTAT|TSEC_FALCON_IMSTAT]] |
− | * FALCON_UNK_250 | + | * TSEC_FALCON_UNK_250 |
− | * FALCON_DMAINFO_CTL | + | * TSEC_FALCON_DMAINFO_CTL |
| | | |
− | === FALCON_SPROT_IRQ === | + | === TSEC_FALCON_SPROT_IRQ === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 2,527: |
Line 2,527: |
| | | |
| Controls accesses to the following registers: | | Controls accesses to the following registers: |
− | * [[#FALCON_IRQMODE|FALCON_IRQMODE]] | + | * [[#TSEC_FALCON_IRQMODE|TSEC_FALCON_IRQMODE]] |
− | * [[#FALCON_IRQMSET|FALCON_IRQMSET]] | + | * [[#TSEC_FALCON_IRQMSET|TSEC_FALCON_IRQMSET]] |
− | * [[#FALCON_IRQMCLR|FALCON_IRQMCLR]] | + | * [[#TSEC_FALCON_IRQMCLR|TSEC_FALCON_IRQMCLR]] |
− | * [[#FALCON_IRQDEST|FALCON_IRQDEST]] | + | * [[#TSEC_FALCON_IRQDEST|TSEC_FALCON_IRQDEST]] |
− | * FALCON_GPTMRINT | + | * TSEC_FALCON_GPTMRINT |
− | * FALCON_GPTMRVAL | + | * TSEC_FALCON_GPTMRVAL |
− | * FALCON_GPTMRCTL | + | * TSEC_FALCON_GPTMRCTL |
− | * FALCON_IRQDEST2 | + | * TSEC_FALCON_IRQDEST2 |
− | * FALCON_UNK_E0 | + | * TSEC_FALCON_UNK_E0 |
| | | |
− | === FALCON_SPROT_MTHD === | + | === TSEC_FALCON_SPROT_MTHD === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 2,550: |
Line 2,550: |
| | | |
| Controls accesses to the following registers: | | Controls accesses to the following registers: |
− | * [[#FALCON_ITFEN|FALCON_ITFEN]] | + | * [[#TSEC_FALCON_ITFEN|TSEC_FALCON_ITFEN]] |
− | * FALCON_CURCTX | + | * TSEC_FALCON_CURCTX |
− | * FALCON_NXTCTX | + | * TSEC_FALCON_NXTCTX |
− | * FALCON_CTXACK | + | * TSEC_FALCON_CTXACK |
− | * FALCON_MTHDDATA | + | * TSEC_FALCON_MTHDDATA |
− | * FALCON_MTHDID | + | * TSEC_FALCON_MTHDID |
− | * FALCON_MTHDWDAT | + | * TSEC_FALCON_MTHDWDAT |
− | * FALCON_MTHDCOUNT | + | * TSEC_FALCON_MTHDCOUNT |
− | * FALCON_MTHDPOP | + | * TSEC_FALCON_MTHDPOP |
− | * FALCON_MTHDRAMSZ | + | * TSEC_FALCON_MTHDRAMSZ |
− | * [[#FALCON_DEBUG1|FALCON_DEBUG1]] | + | * [[#TSEC_FALCON_DEBUG1|TSEC_FALCON_DEBUG1]] |
| | | |
− | === FALCON_SPROT_SCTL === | + | === TSEC_FALCON_SPROT_SCTL === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 2,574: |
Line 2,574: |
| |} | | |} |
| | | |
− | Controls accesses to the [[#FALCON_SCTL|FALCON_SCTL]] register. | + | Controls accesses to the [[#TSEC_FALCON_SCTL|TSEC_FALCON_SCTL]] register. |
| | | |
− | === FALCON_SPROT_WDTMR === | + | === TSEC_FALCON_SPROT_WDTMR === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 2,589: |
Line 2,589: |
| | | |
| Controls accesses to the following registers: | | Controls accesses to the following registers: |
− | * FALCON_WDTMRVAL | + | * TSEC_FALCON_WDTMRVAL |
− | * FALCON_WDTMRCTL | + | * TSEC_FALCON_WDTMRCTL |
| | | |
| === TSEC_SCP_CTL0 === | | === TSEC_SCP_CTL0 === |