Line 950: |
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| | | |
| === TSEC_THI_METHOD0 === | | === TSEC_THI_METHOD0 === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-11 |
| + | | TSEC_THI_METHOD0_OFFSET |
| + | |} |
| + | |
| + | Used to encode and send a method's ID over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission. |
| + | |
| + | The following methods are available: |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! ID | | ! ID |
Line 1,138: |
Line 1,149: |
| |} | | |} |
| | | |
− | Used to encode and send a method's ID over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
| + | === TSEC_THI_METHOD1 === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-31 |
| + | | TSEC_THI_METHOD1_DATA |
| + | |} |
| | | |
− | === TSEC_THI_METHOD1 ===
| |
| Used to encode and send a method's data over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission. | | Used to encode and send a method's data over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission. |
| | | |
Line 1,504: |
Line 1,521: |
| | | |
| === FALCON_MAILBOX0 === | | === FALCON_MAILBOX0 === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-31 |
| + | | FALCON_MAILBOX0_DATA |
| + | |} |
| + | |
| Scratch register for reading/writing data to Falcon. | | Scratch register for reading/writing data to Falcon. |
| | | |
| === FALCON_MAILBOX1 === | | === FALCON_MAILBOX1 === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-31 |
| + | | FALCON_MAILBOX1_DATA |
| + | |} |
| + | |
| Scratch register for reading/writing data to Falcon. | | Scratch register for reading/writing data to Falcon. |
| | | |
Line 1,553: |
Line 1,586: |
| | | |
| === FALCON_DEBUGINFO === | | === FALCON_DEBUGINFO === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-31 |
| + | | FALCON_DEBUGINFO_DATA |
| + | |} |
| + | |
| Used for UCODE self revocation. This register takes the base address of the GSC carveout shifted right by 8. | | Used for UCODE self revocation. This register takes the base address of the GSC carveout shifted right by 8. |
| | | |
Line 1,590: |
Line 1,631: |
| | | |
| === FALCON_RSTAT0 === | | === FALCON_RSTAT0 === |
− | Mirror of the ICD status register 0. | + | Mirror of the [[#FALCON_ICD_RDATA|ICD status register 0]]. |
| | | |
| === FALCON_RSTAT3 === | | === FALCON_RSTAT3 === |
− | Mirror of the ICD status register 3. | + | Mirror of the [[#FALCON_ICD_RDATA|ICD status register 3]]. |
| | | |
| === FALCON_CPUCTL === | | === FALCON_CPUCTL === |
Line 1,625: |
Line 1,666: |
| | | |
| === FALCON_BOOTVEC === | | === FALCON_BOOTVEC === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-31 |
| + | | FALCON_BOOTVEC_VEC |
| + | |} |
| + | |
| Takes the Falcon's boot vector address. | | Takes the Falcon's boot vector address. |
| | | |
Line 1,669: |
Line 1,718: |
| | | |
| === FALCON_DMATRFBASE === | | === FALCON_DMATRFBASE === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-31 |
| + | | FALCON_DMATRFBASE_BASE |
| + | |} |
| + | |
| Base address of the external memory buffer, shifted right by 8. | | Base address of the external memory buffer, shifted right by 8. |
| | | |
Line 1,674: |
Line 1,731: |
| | | |
| === FALCON_DMATRFMOFFS === | | === FALCON_DMATRFMOFFS === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-15 |
| + | | FALCON_DMATRFMOFFS_OFFS |
| + | |} |
| + | |
| For transfers to DMEM: the destination address. | | For transfers to DMEM: the destination address. |
| For transfers to IMEM: the destination virtual IMEM page. | | For transfers to IMEM: the destination virtual IMEM page. |
Line 1,707: |
Line 1,772: |
| | | |
| === FALCON_DMATRFFBOFFS === | | === FALCON_DMATRFFBOFFS === |
− | For transfers to IMEM: the destination physical IMEM page. | + | {| class="wikitable" border="1" |
− | | + | ! Bits |
− | === FALCON_DMAPOLL_FB === | + | ! Description |
| + | |- |
| + | | 0-15 |
| + | | FALCON_DMATRFFBOFFS_OFFS |
| + | |} |
| + | |
| + | For transfers to IMEM: the destination physical IMEM page. |
| + | |
| + | === FALCON_DMAPOLL_FB === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 1,820: |
Line 1,893: |
| | | |
| === FALCON_IMSTAT === | | === FALCON_IMSTAT === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-31 |
| + | | FALCON_IMSTAT_VAL |
| + | |} |
| + | |
| Returns the result of the last command from [[#FALCON_IMCTL|FALCON_IMCTL]]. | | Returns the result of the last command from [[#FALCON_IMCTL|FALCON_IMCTL]]. |
| | | |
Line 1,840: |
Line 1,921: |
| | | |
| === FALCON_TRACEPC === | | === FALCON_TRACEPC === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-23 |
| + | | FALCON_TRACEPC_PC |
| + | |} |
| + | |
| Returns the PC of the last call or branch executed. | | Returns the PC of the last call or branch executed. |
| | | |
Line 1,875: |
Line 1,964: |
| | | |
| === FALCON_IMEMD0 === | | === FALCON_IMEMD0 === |
− | Returns or takes the value for an IMEM read/write operation.
| |
− |
| |
− | === FALCON_IMEMT0 ===
| |
− | Returns or takes the virtual page index for an IMEM read/write operation.
| |
− |
| |
− | === FALCON_DMEMC0 ===
| |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 2-7 | + | | 0-31 |
| + | | FALCON_IMEMD_DATA |
| + | |} |
| + | |
| + | Returns or takes the value for an IMEM read/write operation. |
| + | |
| + | === FALCON_IMEMT0 === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-15 |
| + | | FALCON_IMEMT_TAG |
| + | |} |
| + | |
| + | Returns or takes the virtual page index for an IMEM read/write operation. |
| + | |
| + | === FALCON_DMEMC0 === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 2-7 |
| | FALCON_DMEMC_OFFS | | | FALCON_DMEMC_OFFS |
| |- | | |- |
Line 1,901: |
Line 2,006: |
| | | |
| === FALCON_DMEMD0 === | | === FALCON_DMEMD0 === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-31 |
| + | | FALCON_DMEMD_DATA |
| + | |} |
| + | |
| Returns or takes the value for a DMEM read/write operation. | | Returns or takes the value for a DMEM read/write operation. |
| | | |
Line 1,997: |
Line 2,110: |
| | | |
| === FALCON_ICD_ADDR === | | === FALCON_ICD_ADDR === |
− | Takes the target address for the Falcon's in-chip debugger. | + | {| class="wikitable" border="1" |
− | | + | ! Bits |
− | === FALCON_ICD_WDATA === | + | ! Description |
| + | |- |
| + | | 0-31 |
| + | | FALCON_ICD_ADDR_ADDR |
| + | |} |
| + | |
| + | Takes the target address for the Falcon's in-chip debugger. |
| + | |
| + | === FALCON_ICD_WDATA === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-31 |
| + | | FALCON_ICD_WDATA_DATA |
| + | |} |
| + | |
| Takes the data for writing using the Falcon's in-chip debugger. | | Takes the data for writing using the Falcon's in-chip debugger. |
| | | |
| === FALCON_ICD_RDATA === | | === FALCON_ICD_RDATA === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-31 |
| + | | FALCON_ICD_RDATA_DATA |
| + | |} |
| + | |
| Returns the data read using the Falcon's in-chip debugger. | | Returns the data read using the Falcon's in-chip debugger. |
| | | |
Line 3,125: |
Line 3,262: |
| | | |
| === TSEC_TFBIF_ACTMON_ACTIVE_MASK === | | === TSEC_TFBIF_ACTMON_ACTIVE_MASK === |
− | Takes the memory access mask for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
| |
− |
| |
− | === TSEC_TFBIF_ACTMON_ACTIVE_BORPS ===
| |
− | Takes the billions of records per second count for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
| |
− |
| |
− | === TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT ===
| |
− | Controls the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
| |
− |
| |
− | === TSEC_CG ===
| |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-5 | + | | 0 |
− | | TSEC_CG_IDLE_CG_DLY_CNT | + | | TSEC_TFBIF_ACTMON_ACTIVE_MASK_STARVED_MC |
| + | |- |
| + | | 1 |
| + | | TSEC_TFBIF_ACTMON_ACTIVE_MASK_STALLED_MC |
| + | |- |
| + | | 2 |
| + | | TSEC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED_MC |
| + | |- |
| + | | 3 |
| + | | TSEC_TFBIF_ACTMON_ACTIVE_MASK_ACTIVE |
| + | |} |
| + | |
| + | Takes the memory access mask for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG. |
| + | |
| + | === TSEC_TFBIF_ACTMON_ACTIVE_BORPS === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0 |
| + | | TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STARVED_MC_POLARITY |
| + | |- |
| + | | 1 |
| + | | TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STARVED_MC_OPERATION |
| + | |- |
| + | | 2 |
| + | | TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STALLED_MC_POLARITY |
| + | |- |
| + | | 3 |
| + | | TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STALLED_MC_OPERATION |
| + | |- |
| + | | 4 |
| + | | TSEC_TFBIF_ACTMON_ACTIVE_BORPS_DELAYED_MC_POLARITY |
| + | |- |
| + | | 5 |
| + | | TSEC_TFBIF_ACTMON_ACTIVE_BORPS_DELAYED_MC_OPERATION |
| + | |- |
| + | | 6 |
| + | | TSEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE_POLARITY |
| + | |- |
| + | | 7 |
| + | | TSEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE_OPERATION |
| + | |} |
| + | |
| + | Takes the billions of records per second count for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG. |
| + | |
| + | === TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-31 |
| + | | TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT_VAL |
| + | |} |
| + | |
| + | Controls the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG. |
| + | |
| + | === TSEC_CG === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-5 |
| + | | TSEC_CG_IDLE_CG_DLY_CNT |
| + | |- |
| + | | 6 |
| + | | TSEC_CG_IDLE_CG_EN |
| + | |- |
| + | | 16-18 |
| + | | TSEC_CG_WAKEUP_DLY_CNT |
| + | |- |
| + | | 19 |
| + | | TSEC_CG_WAKEUP_DLY_EN |
| + | |} |
| + | |
| + | === TSEC_BAR0_CTL === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0 |
| + | | TSEC_BAR0_CTL_READ |
| + | |- |
| + | | 1 |
| + | | TSEC_BAR0_CTL_WRITE |
| + | |- |
| + | | 4-7 |
| + | | TSEC_BAR0_CTL_BYTE_MASK |
| + | |- |
| + | | 12-13 |
| + | | TSEC_BAR0_CTL_STATUS |
| + | 0: Idle |
| + | 1: Busy |
| + | 2: Error |
| + | 3: Disabled |
| + | |- |
| + | | 31 |
| + | | TSEC_BAR0_CTL_INIT |
| + | |} |
| + | |
| + | A BAR0 DMA read/write operation requires bits TSEC_BAR0_CTL_INIT and TSEC_BAR0_CTL_READ/TSEC_BAR0_CTL_WRITE to be set in TSEC_BAR0_CTL. |
| + | |
| + | During the transfer, TSEC_BAR0_CTL_STATUS is set to "Busy". |
| + | |
| + | Accessing an invalid address sets TSEC_BAR0_CTL_STATUS to "Error". |
| + | |
| + | === TSEC_BAR0_ADDR === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-31 |
| + | | TSEC_BAR0_ADDR_VAL |
| + | |} |
| + | |
| + | Takes the address for DMA transfers between TSEC and HOST1X (master and clients). |
| + | |
| + | === TSEC_BAR0_DATA === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| |- | | |- |
− | | 6 | + | | 0-31 |
− | | TSEC_CG_IDLE_CG_EN
| + | | TSEC_BAR0_DATA_VAL |
− | |-
| |
− | | 16-18
| |
− | | TSEC_CG_WAKEUP_DLY_CNT
| |
− | |-
| |
− | | 19
| |
− | | TSEC_CG_WAKEUP_DLY_EN | |
| |} | | |} |
| | | |
− | === TSEC_BAR0_CTL === | + | Takes the data for DMA transfers between TSEC and HOST1X (master and clients). |
| + | |
| + | === TSEC_BAR0_TIMEOUT === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0 | + | | 0-31 |
− | | TSEC_BAR0_CTL_READ
| + | | TSEC_BAR0_TIMEOUT_VAL |
− | |-
| |
− | | 1
| |
− | | TSEC_BAR0_CTL_WRITE
| |
− | |-
| |
− | | 4-7
| |
− | | TSEC_BAR0_CTL_BYTE_MASK
| |
− | |-
| |
− | | 12-13
| |
− | | TSEC_BAR0_CTL_STATUS
| |
− | 0: Idle
| |
− | 1: Busy
| |
− | 2: Error
| |
− | 3: Disabled
| |
− | |-
| |
− | | 31
| |
− | | TSEC_BAR0_CTL_INIT | |
| |} | | |} |
| | | |
− | A BAR0 DMA read/write operation requires bits TSEC_BAR0_CTL_INIT and TSEC_BAR0_CTL_READ/TSEC_BAR0_CTL_WRITE to be set in TSEC_BAR0_CTL.
| |
− |
| |
− | During the transfer, TSEC_BAR0_CTL_STATUS is set to "Busy".
| |
− |
| |
− | Accessing an invalid address sets TSEC_BAR0_CTL_STATUS to "Error".
| |
− |
| |
− | === TSEC_BAR0_ADDR ===
| |
− | Takes the address for DMA transfers between TSEC and HOST1X (master and clients).
| |
− |
| |
− | === TSEC_BAR0_DATA ===
| |
− | Takes the data for DMA transfers between TSEC and HOST1X (master and clients).
| |
− |
| |
− | === TSEC_BAR0_TIMEOUT ===
| |
| Takes the timeout value for DMA transfers between TSEC and HOST1X (master and clients). | | Takes the timeout value for DMA transfers between TSEC and HOST1X (master and clients). |
| | | |