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Fuses (view source)

Revision as of 19:47, 20 November 2019

4,060 bytes added ,  19:47, 20 November 2019
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| 0x7000F80C
 
| 0x7000F80C
 
|-
 
|-
−
| FUSE_FUSETIME_RD1
+
| [[#FUSE_FUSETIME_RD1|FUSE_FUSETIME_RD1]]
 
| 0x7000F810
 
| 0x7000F810
 
|-
 
|-
−
| FUSE_FUSETIME_RD2
+
| [[#FUSE_FUSETIME_RD2|FUSE_FUSETIME_RD2]]
 
| 0x7000F814
 
| 0x7000F814
 
|-
 
|-
−
| FUSE_FUSETIME_PGM1
+
| [[#FUSE_FUSETIME_PGM1|FUSE_FUSETIME_PGM1]]
 
| 0x7000F818
 
| 0x7000F818
 
|-
 
|-
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| 0x7000F820
 
| 0x7000F820
 
|-
 
|-
−
| FUSE_FUSEBYPASS
+
| [[#FUSE_FUSEBYPASS|FUSE_FUSEBYPASS]]
 
| 0x7000F824
 
| 0x7000F824
 
|-
 
|-
−
| FUSE_PRIVATEKEYDISABLE
+
| [[#FUSE_PRIVATEKEYDISABLE|FUSE_PRIVATEKEYDISABLE]]
 
| 0x7000F828
 
| 0x7000F828
 
|-
 
|-
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| 0x7000F830
 
| 0x7000F830
 
|-
 
|-
−
| FUSE_PWR_GOOD_SW
+
| [[#FUSE_PWR_GOOD_SW|FUSE_PWR_GOOD_SW]]
 
| 0x7000F834
 
| 0x7000F834
 
|-
 
|-
−
| FUSE_PRIV2RESHIFT
+
| [[#FUSE_PRIV2RESHIFT|FUSE_PRIV2RESHIFT]]
 
| 0x7000F83C
 
| 0x7000F83C
 
|-
 
|-
−
| FUSE_FUSETIME_RD3
+
| [[#FUSE_FUSETIME_RD3|FUSE_FUSETIME_RD3]]
 
| 0x7000F84C
 
| 0x7000F84C
 
|-
 
|-
−
| FUSE_PRIVATE_KEY0_NONZERO
+
| [[#FUSE_PRIVATE_KEY0_NONZERO|FUSE_PRIVATE_KEY0_NONZERO]]
 
| 0x7000F880
 
| 0x7000F880
 
|-
 
|-
−
| FUSE_PRIVATE_KEY1_NONZERO
+
| [[#FUSE_PRIVATE_KEY1_NONZERO|FUSE_PRIVATE_KEY1_NONZERO]]
 
| 0x7000F884
 
| 0x7000F884
 
|-
 
|-
−
| FUSE_PRIVATE_KEY2_NONZERO
+
| [[#FUSE_PRIVATE_KEY2_NONZERO|FUSE_PRIVATE_KEY2_NONZERO]]
 
| 0x7000F888
 
| 0x7000F888
 
|-
 
|-
−
| FUSE_PRIVATE_KEY3_NONZERO
+
| [[#FUSE_PRIVATE_KEY3_NONZERO|FUSE_PRIVATE_KEY3_NONZERO]]
 
| 0x7000F88C
 
| 0x7000F88C
 
|-
 
|-
−
| FUSE_PRIVATE_KEY4_NONZERO
+
| [[#FUSE_PRIVATE_KEY4_NONZERO|FUSE_PRIVATE_KEY4_NONZERO]]
 
| 0x7000F890
 
| 0x7000F890
 
|}
 
|}
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==== FUSE_FUSEADDR ====
 
==== FUSE_FUSEADDR ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-7
 +
| FUSE_FUSEADDR_VLDFLD
 +
|}
 +
 
This register takes the address of the fuse to be read/written/sensed.
 
This register takes the address of the fuse to be read/written/sensed.
    
==== FUSE_FUSERDATA ====
 
==== FUSE_FUSERDATA ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| FUSE_FUSERDATA_DATA
 +
|}
 +
 
This register receives the value read from the fuse.
 
This register receives the value read from the fuse.
    
==== FUSE_FUSEWDATA ====
 
==== FUSE_FUSEWDATA ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| FUSE_FUSEWDATA_DATA
 +
|}
 +
 
This register takes the value to be written to the fuse.
 
This register takes the value to be written to the fuse.
 +
 +
==== FUSE_FUSETIME_RD1 ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-7
 +
| FUSE_FUSETIME_RD1_TSUR_MAX
 +
|-
 +
| 8-15
 +
| FUSE_FUSETIME_RD1_TSUR_FUSEOUT
 +
|-
 +
| 16-23
 +
| FUSE_FUSETIME_RD1_THR_MAX
 +
|}
 +
 +
==== FUSE_FUSETIME_RD2 ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-15
 +
| FUSE_FUSETIME_RD2_TWIDTH_RD
 +
|}
 +
 +
==== FUSE_FUSETIME_PGM1 ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-7
 +
| FUSE_FUSETIME_PGM1_TSUP_MAX
 +
|-
 +
| 8-15
 +
| FUSE_FUSETIME_PGM1_TSUP_ADDR
 +
|-
 +
| 16-23
 +
| FUSE_FUSETIME_PGM1_THP_ADDR
 +
|-
 +
| 24-31
 +
| FUSE_FUSETIME_PGM1_THP_PS
 +
|}
    
==== FUSE_FUSETIME_PGM2 ====
 
==== FUSE_FUSETIME_PGM2 ====
−
This register takes the fuse programming pulse (0xC0 == 19200 kHz).
+
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-15
 +
| FUSE_FUSETIME_PGM2_TWIDTH_PGM
 +
|-
 +
| 16-23
 +
| FUSE_FUSETIME_PGM2_TSUP_PS
 +
|-
 +
| 24-31
 +
| FUSE_FUSETIME_PGM2_THP_CSPS
 +
|}
    
==== FUSE_PRIV2INTFC_START ====
 
==== FUSE_PRIV2INTFC_START ====
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|-
 
|-
 
| 1
 
| 1
−
| FUSE_PRIV2INTFC_START_SKIP_RECORDS
+
| FUSE_PRIV2INTFC_SKIP_RECORDS
 +
|}
 +
 
 +
==== FUSE_FUSEBYPASS ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| FUSE_FUSEBYPASS_VAL
 
|}
 
|}
 +
 +
If set, this register enables fuse bypass mode. This is only available in hardware where the [[Bitmap|bypass_fuses]] fuse remains unburnt.
 +
 +
==== FUSE_PRIVATEKEYDISABLE ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| FUSE_PRIVATEKEYDISABLE_VAL
 +
|-
 +
| 4
 +
| FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT_VAL
 +
|}
 +
 +
If set, this register hides the [[FUSE_PRIVATE_KEY|private_key]] fuses.
    
==== FUSE_DISABLEREGPROGRAM ====
 
==== FUSE_DISABLEREGPROGRAM ====
−
If set to 0x01, this register disables fuse programming.
+
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| FUSE_DISABLEREGPROGRAM_VAL
 +
|}
 +
 
 +
If set, this register disables fuse programming.
    
==== FUSE_WRITE_ACCESS_SW ====
 
==== FUSE_WRITE_ACCESS_SW ====
−
If set to 0x01, this register disables software writes to the fuse driver registers.
+
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| FUSE_WRITE_ACCESS_SW_CTRL
 +
|-
 +
| 16
 +
| FUSE_WRITE_ACCESS_SW_STATUS
 +
|}
 +
 
 +
If set, this register makes the fuse driver registers read-only.
 +
 
 +
==== FUSE_PWR_GOOD_SW ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| FUSE_PWR_GOOD_SW_VAL
 +
|}
 +
 
 +
This register is deprecated and has no effect.
 +
 
 +
==== FUSE_PRIV2RESHIFT ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| FUSE_PRIV2RESHIFT_TRIGENABLE_VAL
 +
|-
 +
| 1
 +
| FUSE_PRIV2RESHIFT_TRIG_1_FCPU0_VAL
 +
|-
 +
| 2
 +
| FUSE_PRIV2RESHIFT_TRIG_1_FCPU1_VAL
 +
|-
 +
| 3
 +
| FUSE_PRIV2RESHIFT_TRIG_1_FCPU2_VAL
 +
|-
 +
| 4
 +
| FUSE_PRIV2RESHIFT_TRIG_1_FCPU3_VAL
 +
|-
 +
| 5
 +
| FUSE_PRIV2RESHIFT_TRIG_1_FL2_TBANK0_VAL
 +
|-
 +
| 6
 +
| FUSE_PRIV2RESHIFT_TRIG_1_FL2_TBANK1_VAL
 +
|-
 +
| 7
 +
| FUSE_PRIV2RESHIFT_TRIG_1_FL2_TBANK2_VAL
 +
|-
 +
| 8
 +
| FUSE_PRIV2RESHIFT_TRIG_1_FL2_TBANK3_VAL
 +
|-
 +
| 9
 +
| FUSE_PRIV2RESHIFT_TRIG_1_SCPU_VAL
 +
|-
 +
| 10
 +
| FUSE_PRIV2RESHIFT_TRIG_1_SL2_TBANK_VAL
 +
|-
 +
| 11
 +
| FUSE_PRIV2RESHIFT_STATUS_1_FCPU0_VAL
 +
|-
 +
| 12
 +
| FUSE_PRIV2RESHIFT_STATUS_1_FCPU1_VAL
 +
|-
 +
| 13
 +
| FUSE_PRIV2RESHIFT_STATUS_1_FCPU2_VAL
 +
|-
 +
| 14
 +
| FUSE_PRIV2RESHIFT_STATUS_1_FCPU3_VAL
 +
|-
 +
| 15
 +
| FUSE_PRIV2RESHIFT_STATUS_1_FL2_TBANK0_VAL
 +
|-
 +
| 16
 +
| FUSE_PRIV2RESHIFT_STATUS_1_FL2_TBANK1_VAL
 +
|-
 +
| 17
 +
| FUSE_PRIV2RESHIFT_STATUS_1_FL2_TBANK2_VAL
 +
|-
 +
| 18
 +
| FUSE_PRIV2RESHIFT_STATUS_1_FL2_TBANK3_VAL
 +
|-
 +
| 19
 +
| FUSE_PRIV2RESHIFT_STATUS_1_SCPU_VAL
 +
|-
 +
| 20
 +
| FUSE_PRIV2RESHIFT_STATUS_1_SL2_TBANK_VAL
 +
|}
 +
 
 +
==== FUSE_FUSETIME_RD3 ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-15
 +
| FUSE_FUSETIME_RD3_TSUR_PDCS
 +
|}
 +
 
 +
==== FUSE_PRIVATE_KEY0_NONZERO ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| FUSE_PRIVATE_KEY0_NONZERO_DATA
 +
|}
 +
 
 +
==== FUSE_PRIVATE_KEY1_NONZERO ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| FUSE_PRIVATE_KEY1_NONZERO_DATA
 +
|}
 +
 
 +
==== FUSE_PRIVATE_KEY2_NONZERO ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| FUSE_PRIVATE_KEY2_NONZERO_DATA
 +
|}
 +
 
 +
==== FUSE_PRIVATE_KEY3_NONZERO ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| FUSE_PRIVATE_KEY3_NONZERO_DATA
 +
|}
 +
 
 +
==== FUSE_PRIVATE_KEY4_NONZERO ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| FUSE_PRIVATE_KEY4_NONZERO_DATA
 +
|}
    
=== Cache registers ===
 
=== Cache registers ===
Retrieved from "https://switchbrew.org/wiki/Special:MobileDiff/8369"

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