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no edit summary
| 0x04
| 0x04
|-
|-
| [[#TSEC_TFBIF_MMU_TRANSCFG|TSEC_TFBIF_MMU_TRANSCFG]]
| [[#TSEC_TFBIF_MMU_APERTURE_CTL|TSEC_TFBIF_MMU_APERTURE_CTL]]
| 0x54501648
| 0x54501648
| 0x04
| 0x04
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
=== TSEC_TFBIF_MMU_TRANSCFG ===
=== TSEC_TFBIF_MMU_APERTURE_CTL ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Bits
! Description
! Description
|-
|-
| 0-3
| 0-2
| Transfer configuration for CTXDMA port 0
| Aperture ID for CTXDMA port 0
|-
|-
| 4-7
| 4-6
| Transfer configuration for CTXDMA port 1
| Aperture ID for CTXDMA port 1
|-
|-
| 8-11
| 8-10
| Transfer configuration for CTXDMA port 2
| Aperture ID for CTXDMA port 2
|-
|-
| 12-15
| 12-14
| Transfer configuration for CTXDMA port 3
| Aperture ID for CTXDMA port 3
|-
|-
| 16-19
| 16-18
| Transfer configuration for CTXDMA port 4
| Aperture ID for CTXDMA port 4
|-
|-
| 20-23
| 20-22
| Transfer configuration for CTXDMA port 5
| Aperture ID for CTXDMA port 5
|-
|-
| 24-27
| 24-26
| Transfer configuration for CTXDMA port 6
| Aperture ID for CTXDMA port 6
|-
|-
| 28-31
| 28-30
| Transfer configuration for CTXDMA port 7
| Aperture ID for CTXDMA port 7
|}
|}
Controls external memory transfers' configuration at the MMU level. Accessible in HS mode only.
Controls the aperture ID of memory requests. Accessible in HS mode only.
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.