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no edit summary
Controls accesses to the following registers:
Controls accesses to the following registers:
* FALCON_VM_SUPERVISOR
* FALCON_PRIVSTATE
* FALCON_SUBENGINE_RESET
* FALCON_SFTRESET
* FALCON_HOST_IO_INDEX
* FALCON_ADDR
* [[#FALCON_DMACTL|FALCON_DMACTL]]
* [[#FALCON_DMACTL|FALCON_DMACTL]]
* [[#FALCON_IMCTL|FALCON_IMCTL]]
* [[#FALCON_IMCTL|FALCON_IMCTL]]
* [[#FALCON_IRQMCLR|FALCON_IRQMCLR]]
* [[#FALCON_IRQMCLR|FALCON_IRQMCLR]]
* [[#FALCON_IRQDEST|FALCON_IRQDEST]]
* [[#FALCON_IRQDEST|FALCON_IRQDEST]]
* FALCON_GPTMR_PERIOD
* FALCON_GPTMRINT
* FALCON_GPTMR_TIME
* FALCON_GPTMRVAL
* FALCON_GPTMR_ENABLE
* FALCON_GPTMRCTL
* FALCON_UNK_3C
* FALCON_UNK_3C
* FALCON_UNK_E0
* FALCON_UNK_E0
* FALCON_CURCTX
* FALCON_CURCTX
* FALCON_NXTCTX
* FALCON_NXTCTX
* FALCON_CMDCTX
* FALCON_CTXACK
* FALCON_MTHD_DATA
* FALCON_MTHDDATA
* FALCON_MTHD_CMD
* FALCON_MTHDID
* FALCON_MTHD_DATA_WR
* FALCON_MTHDWDAT
* FALCON_MTHD_OCCUPIED
* FALCON_MTHDCOUNT
* FALCON_MTHD_ACK
* FALCON_MTHDPOP
* FALCON_MTHD_LIMIT
* FALCON_MTHDRAMSZ
* [[#FALCON_DEBUG1|FALCON_DEBUG1]]
* [[#FALCON_DEBUG1|FALCON_DEBUG1]]
Controls accesses to the following registers:
Controls accesses to the following registers:
* FALCON_WDTMR_TIME
* FALCON_WDTMRVAL
* FALCON_WDTMR_ENABLE
* FALCON_WDTMRCTL
=== TSEC_SCP_CTL0 ===
=== TSEC_SCP_CTL0 ===