2,928
edits
Changes
Jump to navigation
Jump to search
Line 711:
Line 711: − + Line 719:
Line 719: − + − + − + − + Line 2,231:
Line 2,231: − + Line 2,243:
Line 2,243: − + Line 2,275:
Line 2,275: − Configures MMU physical mode.+ − + Line 2,309:
Line 2,309: − + + + + + + + + + +
no edit summary
| 0x04
| 0x04
|-
|-
| [[#TSEC_TFBIF_MMU_PHYS_PROT|TSEC_TFBIF_MMU_PHYS_PROT]]
| [[#TSEC_TFBIF_MMU_PROT|TSEC_TFBIF_MMU_PROT]]
| 0x54501640
| 0x54501640
| 0x04
| 0x04
| 0x04
| 0x04
|-
|-
| [[#TSEC_TFBIF_MMU_PHYS_TRANSCFG|TSEC_TFBIF_MMU_PHYS_TRANSCFG]]
| [[#TSEC_TFBIF_MMU_TRANSCFG|TSEC_TFBIF_MMU_TRANSCFG]]
| 0x54501648
| 0x54501648
| 0x04
| 0x04
|-
|-
| TSEC_TFBIF_ACTMON_MAMASK
| [[#TSEC_TFBIF_ACTMON_MAMASK|TSEC_TFBIF_ACTMON_MAMASK]]
| 0x5450164C
| 0x5450164C
| 0x04
| 0x04
|-
|-
| TSEC_TFBIF_ACTMON_BORPS
| [[#TSEC_TFBIF_ACTMON_BORPS|TSEC_TFBIF_ACTMON_BORPS]]
| 0x54501650
| 0x54501650
| 0x04
| 0x04
|-
|-
| TSEC_TFBIF_ACTMON_CTL
| [[#TSEC_TFBIF_ACTMON_CTL|TSEC_TFBIF_ACTMON_CTL]]
| 0x54501654
| 0x54501654
| 0x04
| 0x04
|}
|}
=== TSEC_TFBIF_MMU_PHYS_PROT ===
=== TSEC_TFBIF_MMU_PROT ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Bits
|}
|}
Controls accesses to external memory in MMU physical mode.
Controls accesses to external memory at the MMU level. Accessible in HS mode only.
=== TSEC_TFBIF_MMU_PHYS_SEC ===
=== TSEC_TFBIF_MMU_PHYS_SEC ===
|}
|}
Controls MMU bypass mode. Accessible in HS mode only.
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
=== TSEC_TFBIF_MMU_PHYS_TRANSCFG ===
=== TSEC_TFBIF_MMU_TRANSCFG ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Bits
|}
|}
Controls the transfer configuration for MMU physical mode.
Controls external memory transfers' configuration at the MMU level. Accessible in HS mode only.
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
=== TSEC_TFBIF_ACTMON_MAMASK ===
Takes the memory access mask for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
=== TSEC_TFBIF_ACTMON_BORPS ===
Takes the billions of records per second count for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
=== TSEC_TFBIF_ACTMON_CTL ===
Controls the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
=== TSEC_CG ===
=== TSEC_CG ===