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Line 10: − + Line 717:
Line 717: + + + + Line 2,220:
Line 2,224: + + + + + + + + + + + + + + + + + +
no edit summary
* 0x54501400 to 0x54501500: SCP (Secure Crypto Processor?).
* 0x54501400 to 0x54501500: SCP (Secure Crypto Processor?).
* 0x54501500 to 0x54501600: TRNG (True Random Number Generator).
* 0x54501500 to 0x54501600: TRNG (True Random Number Generator).
* 0x54501600 to 0x54501700: TFBIF (Tegra Framebuffer Interface).
* 0x54501600 to 0x54501700: TFBIF (Tegra Framebuffer Interface) and CG (Clock Gate).
* 0x54501700 to 0x54501800: DMA.
* 0x54501700 to 0x54501800: DMA.
* 0x54501800 to 0x54501900: TEGRA (miscellaneous interfaces).
* 0x54501800 to 0x54501900: TEGRA (miscellaneous interfaces).
| [[#TSEC_TFBIF_UNK_48|TSEC_TFBIF_UNK_48]]
| [[#TSEC_TFBIF_UNK_48|TSEC_TFBIF_UNK_48]]
| 0x54501648
| 0x54501648
| 0x04
|-
| [[#TSEC_CG|TSEC_CG]]
| 0x545016D0
| 0x04
| 0x04
|-
|-
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
=== TSEC_CG ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-5
| TSEC_CG_IDLE_CG_DLY_CNT
|-
| 6
| TSEC_CG_IDLE_CG_EN
|-
| 16-18
| TSEC_CG_WAKEUP_DLY_CNT
|-
| 19
| TSEC_CG_WAKEUP_DLY_EN
|}
=== TSEC_DMA_CMD ===
=== TSEC_DMA_CMD ===