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100 bytes added ,  20:07, 2 February 2018
Line 587: Line 587:  
| 12
 
| 12
 
| TSEC_DMA_CMD_BUSY
 
| TSEC_DMA_CMD_BUSY
 +
|-
 +
| 13
 +
| TSEC_DMA_CMD_ERROR
 
|-
 
|-
 
| 31
 
| 31
Line 596: Line 599:     
During the transfer, the TSEC_DMA_CMD_BUSY bit is set.
 
During the transfer, the TSEC_DMA_CMD_BUSY bit is set.
 +
 +
Accessing an invalid address causes bit TSEC_DMA_CMD_ERROR to be set.
    
=== TSEC_DMA_ADDR ===
 
=== TSEC_DMA_ADDR ===

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