Line 49: |
Line 49: |
| | [[#TSEC_THI_CONT_SYNCPT_L1|TSEC_THI_CONT_SYNCPT_L1]] | | | [[#TSEC_THI_CONT_SYNCPT_L1|TSEC_THI_CONT_SYNCPT_L1]] |
| | 0x5450002C | | | 0x5450002C |
− | | 0x04
| |
− | |-
| |
− | | [[#TSEC_THI_STREAMID0|TSEC_THI_STREAMID0]]
| |
− | | 0x54500030
| |
− | | 0x04
| |
− | |-
| |
− | | [[#TSEC_THI_STREAMID1|TSEC_THI_STREAMID1]]
| |
− | | 0x54500034
| |
− | | 0x04
| |
− | |-
| |
− | | [[#TSEC_THI_THI_SEC|TSEC_THI_THI_SEC]]
| |
− | | 0x54500038
| |
| | 0x04 | | | 0x04 |
| |- | | |- |
Line 307: |
Line 295: |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_FALCON_UNK_E0 | + | | [[#TSEC_FALCON_SIRQMASK|TSEC_FALCON_SIRQMASK]] |
| | 0x545010E0 | | | 0x545010E0 |
| | 0x04 | | | 0x04 |
Line 547: |
Line 535: |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | [[#TSEC_FALCON_SSTAT|TSEC_FALCON_SSTAT]] | + | | [[#TSEC_FALCON_SERRSTAT|TSEC_FALCON_SERRSTAT]] |
| | 0x54501244 | | | 0x54501244 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_FALCON_UNK_250 | + | | [[#TSEC_FALCON_SERRVAL|TSEC_FALCON_SERRVAL]] |
| + | | 0x54501248 |
| + | | 0x04 |
| + | |- |
| + | | [[#TSEC_FALCON_SERRADDR|TSEC_FALCON_SERRADDR]] |
| + | | 0x5450124C |
| + | | 0x04 |
| + | |- |
| + | | [[#TSEC_FALCON_SCTL1|TSEC_FALCON_SCTL1]] |
| | 0x54501250 | | | 0x54501250 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_FALCON_UNK_260 | + | | [[#TSEC_FALCON_STEST|TSEC_FALCON_STEST]] |
| + | | 0x54501258 |
| + | | 0x04 |
| + | |- |
| + | | [[#TSEC_FALCON_SICD|TSEC_FALCON_SICD]] |
| | 0x54501260 | | | 0x54501260 |
| | 0x04 | | | 0x04 |
Line 813: |
Line 813: |
| | [[#TSEC_TFBIF_MCCIF_FIFOCTRL1|TSEC_TFBIF_MCCIF_FIFOCTRL1]] | | | [[#TSEC_TFBIF_MCCIF_FIFOCTRL1|TSEC_TFBIF_MCCIF_FIFOCTRL1]] |
| | 0x54501634 | | | 0x54501634 |
− | | 0x04
| |
− | |-
| |
− | | [[#TSEC_TFBIF_WRR_RDP|TSEC_TFBIF_WRR_RDP]]
| |
− | | 0x54501638
| |
| | 0x04 | | | 0x04 |
| |- | | |- |
Line 829: |
Line 825: |
| | [[#TSEC_TFBIF_REGIONCFG|TSEC_TFBIF_REGIONCFG]] | | | [[#TSEC_TFBIF_REGIONCFG|TSEC_TFBIF_REGIONCFG]] |
| | 0x54501648 | | | 0x54501648 |
− | | 0x04
| |
− | |-
| |
− | | [[#TSEC_TFBIF_ACTMON_ACTIVE_MASK|TSEC_TFBIF_ACTMON_ACTIVE_MASK]]
| |
− | | 0x5450164C
| |
− | | 0x04
| |
− | |-
| |
− | | [[#TSEC_TFBIF_ACTMON_ACTIVE_BORPS|TSEC_TFBIF_ACTMON_ACTIVE_BORPS]]
| |
− | | 0x54501650
| |
− | | 0x04
| |
− | |-
| |
− | | [[#TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT|TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT]]
| |
− | | 0x54501654
| |
− | | 0x04
| |
− | |-
| |
− | | [[#TSEC_TFBIF_ACTMON_MCB_MASK|TSEC_TFBIF_ACTMON_MCB_MASK]]
| |
− | | 0x54501660
| |
− | | 0x04
| |
− | |-
| |
− | | [[#TSEC_TFBIF_ACTMON_MCB_BORPS|TSEC_TFBIF_ACTMON_MCB_BORPS]]
| |
− | | 0x54501664
| |
− | | 0x04
| |
− | |-
| |
− | | [[#TSEC_TFBIF_ACTMON_MCB_WEIGHT|TSEC_TFBIF_ACTMON_MCB_WEIGHT]]
| |
− | | 0x54501668
| |
− | | 0x04
| |
− | |-
| |
− | | [[#TSEC_TFBIF_THI_TRANSPROP|TSEC_TFBIF_THI_TRANSPROP]]
| |
− | | 0x54501670
| |
| | 0x04 | | | 0x04 |
| |- | | |- |
Line 879: |
Line 847: |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_TEGRA_UNK_00 | + | | [[#TSEC_VERSION|TSEC_VERSION]] |
| | 0x54501800 | | | 0x54501800 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_TEGRA_UNK_04 | + | | [[#TSEC_SCRATCH0|TSEC_SCRATCH0]] |
| | 0x54501804 | | | 0x54501804 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_TEGRA_UNK_08 | + | | [[#TSEC_SCRATCH1|TSEC_SCRATCH1]] |
| | 0x54501808 | | | 0x54501808 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_TEGRA_UNK_0C | + | | [[#TSEC_SCRATCH2|TSEC_SCRATCH2]] |
| | 0x5450180C | | | 0x5450180C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_TEGRA_UNK_10 | + | | [[#TSEC_SCRATCH3|TSEC_SCRATCH3]] |
| | 0x54501810 | | | 0x54501810 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_TEGRA_UNK_14 | + | | [[#TSEC_SCRATCH4|TSEC_SCRATCH4]] |
| | 0x54501814 | | | 0x54501814 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_TEGRA_UNK_18 | + | | [[#TSEC_SCRATCH5|TSEC_SCRATCH5]] |
| | 0x54501818 | | | 0x54501818 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_TEGRA_UNK_1C | + | | [[#TSEC_SCRATCH6|TSEC_SCRATCH6]] |
| | 0x5450181C | | | 0x5450181C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_TEGRA_UNK_20 | + | | [[#TSEC_SCRATCH7|TSEC_SCRATCH7]] |
| | 0x54501820 | | | 0x54501820 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_TEGRA_UNK_24 | + | | [[#TSEC_GPTMRINT|TSEC_GPTMRINT]] |
| | 0x54501824 | | | 0x54501824 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_TEGRA_UNK_28 | + | | [[#TSEC_GPTMRVAL|TSEC_GPTMRVAL]] |
| | 0x54501828 | | | 0x54501828 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_TEGRA_UNK_2C | + | | [[#TSEC_GPTMRCTL|TSEC_GPTMRCTL]] |
| | 0x5450182C | | | 0x5450182C |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_TEGRA_UNK_30 | + | | [[#TSEC_ITFEN|TSEC_ITFEN]] |
| | 0x54501830 | | | 0x54501830 |
| | 0x04 | | | 0x04 |
| |- | | |- |
− | | TSEC_TEGRA_UNK_34 | + | | [[#TSEC_ITFSTAT|TSEC_ITFSTAT]] |
| | 0x54501834 | | | 0x54501834 |
| | 0x04 | | | 0x04 |
Line 1,075: |
Line 1,043: |
| |} | | |} |
| | | |
− | === TSEC_THI_STREAMID0 === | + | === TSEC_THI_METHOD0 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-6 | + | | 0-11 |
− | | TSEC_THI_STREAMID0_ID | + | | TSEC_THI_METHOD0_OFFSET |
| |} | | |} |
| | | |
− | === TSEC_THI_STREAMID1 ===
| + | Used to encode and send a method's ID over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission. |
− | {| class="wikitable" border="1"
| |
− | ! Bits
| |
− | ! Description
| |
− | |-
| |
− | | 0-6
| |
− | | TSEC_THI_STREAMID1_ID
| |
− | |}
| |
| | | |
− | === TSEC_THI_THI_SEC ===
| + | The following methods are available: |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
− | ! Bits | + | ! ID |
− | ! Description | + | ! Method |
| |- | | |- |
− | | 0
| + | | 0x100 |
− | | TSEC_THI_THI_SEC_TZ_LOCK
| + | | NOP |
− | |-
| |
− | | 4
| |
− | | TSEC_THI_THI_SEC_TZ_AUTH
| |
− | |-
| |
− | | 8
| |
− | | TSEC_THI_THI_SEC_CH_LOCK
| |
− | |}
| |
− | | |
− | === TSEC_THI_METHOD0 ===
| |
− | {| class="wikitable" border="1"
| |
− | ! Bits
| |
− | ! Description
| |
− | |-
| |
− | | 0-11
| |
− | | TSEC_THI_METHOD0_OFFSET
| |
− | |}
| |
− | | |
− | Used to encode and send a method's ID over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
| |
− | | |
− | The following methods are available:
| |
− | {| class="wikitable" border="1"
| |
− | ! ID
| |
− | ! Method
| |
− | |-
| |
− | | 0x100 | |
− | | NOP | |
| |- | | |- |
| | 0x140 | | | 0x140 |
Line 2,054: |
Line 1,989: |
| | 16 | | | 16 |
| | TSEC_FALCON_DEBUG1_CTXSW_MODE | | | TSEC_FALCON_DEBUG1_CTXSW_MODE |
− | |-
| |
− | | 17
| |
− | | TSEC_FALCON_DEBUG1_TRACE_FORMAT
| |
| |} | | |} |
| | | |
Line 2,337: |
Line 2,269: |
| === TSEC_FALCON_RSTAT3 === | | === TSEC_FALCON_RSTAT3 === |
| Mirror of the [[#TSEC_FALCON_ICD_RDATA|ICD status register 3]]. | | Mirror of the [[#TSEC_FALCON_ICD_RDATA|ICD status register 3]]. |
| + | |
| + | === TSEC_FALCON_SIRQMASK === |
| + | Unofficial name. |
| + | |
| + | Same as [[#TSEC_FALCON_IRQMASK|TSEC_FALCON_IRQMASK]], but for LS mode. |
| | | |
| === TSEC_FALCON_CPUCTL === | | === TSEC_FALCON_CPUCTL === |
Line 3,308: |
Line 3,245: |
| |- | | |- |
| | 4-5 | | | 4-5 |
| + | | Current access level |
| + | |- |
| + | | 8-9 |
| + | | Unknown access level |
| + | |- |
| + | | 12 |
| | Unknown | | | Unknown |
| |- | | |- |
− | | 12-13 | + | | 13 |
| | Unknown | | | Unknown |
| |- | | |- |
Line 3,317: |
Line 3,260: |
| |} | | |} |
| | | |
− | === TSEC_FALCON_SSTAT === | + | === TSEC_FALCON_SERRSTAT === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| + | |- |
| + | | 0-23 |
| + | | Unknown |
| |- | | |- |
| | 30 | | | 30 |
Line 3,329: |
Line 3,275: |
| |} | | |} |
| | | |
− | === TSEC_FALCON_SPROT_IMEM === | + | Unofficial name. |
| + | |
| + | Used for detecting invalid CSB accesses in LS mode. |
| + | |
| + | === TSEC_FALCON_SERRVAL === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-3 | + | | 0-31 |
− | | Read access level | + | | Error code |
− | |-
| + | |} |
− | | 4-7
| + | |
− | | Write access level
| + | Unofficial name. |
− | |} | |
− | | |
− | Controls accesses to Falcon IMEM.
| |
| | | |
− | === TSEC_FALCON_SPROT_DMEM === | + | === TSEC_FALCON_SERRADDR === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-3 | + | | 0-31 |
− | | Read access level | + | | Error address |
− | |-
| |
− | | 4-7
| |
− | | Write access level
| |
| |} | | |} |
| | | |
− | Controls accesses to Falcon DMEM.
| + | Unofficial name. |
| | | |
− | === TSEC_FALCON_SPROT_CPUCTL === | + | === TSEC_FALCON_SCTL1 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-3 | + | | 0-1 |
− | | Read access level | + | | CSB access level |
| |- | | |- |
− | | 4-7 | + | | 2-3 |
− | | Write access level | + | | Unknown access level |
| |} | | |} |
| | | |
− | Controls accesses to the [[#TSEC_FALCON_CPUCTL|TSEC_FALCON_CPUCTL]] register.
| + | Unofficial name. |
| | | |
− | === TSEC_FALCON_SPROT_MISC === | + | === TSEC_FALCON_STEST === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-3 | + | | 0-31 |
− | | Read access level | + | | Unknown |
− | |-
| |
− | | 4-7
| |
− | | Write access level
| |
| |} | | |} |
| | | |
− | Controls accesses to the following registers:
| + | Unofficial name. |
− | * [[#TSEC_FALCON_PRIVSTATE|TSEC_FALCON_PRIVSTATE]]
| |
− | * [[#TSEC_FALCON_SFTRESET|TSEC_FALCON_SFTRESET]]
| |
− | * [[#TSEC_FALCON_ADDR|TSEC_FALCON_ADDR]]
| |
− | * [[#TSEC_FALCON_DMACTL|TSEC_FALCON_DMACTL]]
| |
− | * [[#TSEC_FALCON_IMCTL|TSEC_FALCON_IMCTL]]
| |
− | * [[#TSEC_FALCON_IMSTAT|TSEC_FALCON_IMSTAT]]
| |
− | * TSEC_FALCON_UNK_250
| |
− | * [[#TSEC_FALCON_DMAINFO_CTL|TSEC_FALCON_DMAINFO_CTL]]
| |
| | | |
− | === TSEC_FALCON_SPROT_IRQ === | + | === TSEC_FALCON_SICD === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-3 | + | | 0 |
− | | Read access level | + | | Enable access to ICD command STOP |
| + | |- |
| + | | 1 |
| + | | Enable access to ICD command RUN |
| |- | | |- |
− | | 4-7 | + | | 2 |
− | | Write access level | + | | Enable access to ICD command RUNB |
| + | |- |
| + | | 3 |
| + | | Enable access to ICD command STEP |
| + | |- |
| + | | 4 |
| + | | Enable access to ICD command EMASK |
| + | |- |
| + | | 5 |
| + | | Enable access to ICD command RREG (only for SPRs) |
| + | |- |
| + | | 6 |
| + | | Enable access to ICD command RSTAT |
| + | |- |
| + | | 7 |
| + | | Enable access to IBRKPT registers |
| + | |- |
| + | | 8 |
| + | | Enable access to ICD command RREG (only for GPRs) |
| + | |- |
| + | | 9 |
| + | | Enable access to ICD command RDM |
| |} | | |} |
| | | |
− | Controls accesses to the following registers: | + | Unofficial name. |
− | * [[#TSEC_FALCON_IRQMODE|TSEC_FALCON_IRQMODE]]
| + | |
− | * [[#TSEC_FALCON_IRQMSET|TSEC_FALCON_IRQMSET]]
| + | Controls access to the ICD in LS mode. |
− | * [[#TSEC_FALCON_IRQMCLR|TSEC_FALCON_IRQMCLR]]
| |
− | * [[#TSEC_FALCON_IRQDEST|TSEC_FALCON_IRQDEST]]
| |
− | * [[#TSEC_FALCON_GPTMRINT|TSEC_FALCON_GPTMRINT]]
| |
− | * [[#TSEC_FALCON_GPTMRVAL|TSEC_FALCON_GPTMRVAL]]
| |
− | * [[#TSEC_FALCON_GPTMRCTL|TSEC_FALCON_GPTMRCTL]]
| |
− | * [[#TSEC_FALCON_IRQDEST2|TSEC_FALCON_IRQDEST2]]
| |
− | * TSEC_FALCON_UNK_E0
| |
| | | |
− | === TSEC_FALCON_SPROT_MTHD === | + | === TSEC_FALCON_SPROT_IMEM === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-3 | + | | 0-2 |
| | Read access level | | | Read access level |
| |- | | |- |
− | | 4-7 | + | | 3 |
| + | | Set on memory read access violation |
| + | |- |
| + | | 4-6 |
| | Write access level | | | Write access level |
| + | |- |
| + | | 7 |
| + | | Set on memory write access violation |
| |} | | |} |
| | | |
− | Controls accesses to the following registers: | + | Unofficial name. |
− | * [[#TSEC_FALCON_ITFEN|TSEC_FALCON_ITFEN]]
| + | |
− | * [[#TSEC_FALCON_CURCTX|TSEC_FALCON_CURCTX]]
| + | Controls accesses to Falcon IMEM. |
− | * [[#TSEC_FALCON_NXTCTX|TSEC_FALCON_NXTCTX]]
| + | |
− | * [[#TSEC_FALCON_CTXACK|TSEC_FALCON_CTXACK]]
| + | === TSEC_FALCON_SPROT_DMEM === |
− | * [[#TSEC_FALCON_MTHDDATA|TSEC_FALCON_MTHDDATA]]
| + | {| class="wikitable" border="1" |
− | * [[#TSEC_FALCON_MTHDID|TSEC_FALCON_MTHDID]]
| |
− | * [[#TSEC_FALCON_MTHDWDAT|TSEC_FALCON_MTHDWDAT]]
| |
− | * [[#TSEC_FALCON_MTHDCOUNT|TSEC_FALCON_MTHDCOUNT]]
| |
− | * [[#TSEC_FALCON_MTHDPOP|TSEC_FALCON_MTHDPOP]]
| |
− | * [[#TSEC_FALCON_MTHDRAMSZ|TSEC_FALCON_MTHDRAMSZ]]
| |
− | * [[#TSEC_FALCON_DEBUG1|TSEC_FALCON_DEBUG1]]
| |
− | | |
− | === TSEC_FALCON_SPROT_SCTL === | |
− | {| class="wikitable" border="1" | |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-3 | + | | 0-2 |
| | Read access level | | | Read access level |
| |- | | |- |
− | | 4-7 | + | | 3 |
| + | | Set on memory read access violation |
| + | |- |
| + | | 4-6 |
| | Write access level | | | Write access level |
| + | |- |
| + | | 7 |
| + | | Set on memory write access violation |
| |} | | |} |
| | | |
− | Controls accesses to the [[#TSEC_FALCON_SCTL|TSEC_FALCON_SCTL]] register. | + | Unofficial name. |
| + | |
| + | Controls accesses to Falcon DMEM. |
| | | |
− | === TSEC_FALCON_SPROT_WDTMR === | + | === TSEC_FALCON_SPROT_CPUCTL === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-3 | + | | 0-2 |
| | Read access level | | | Read access level |
| |- | | |- |
− | | 4-7 | + | | 3 |
| + | | Set on memory read access violation |
| + | |- |
| + | | 4-6 |
| | Write access level | | | Write access level |
| + | |- |
| + | | 7 |
| + | | Set on memory write access violation |
| |} | | |} |
| | | |
− | Controls accesses to the following registers: | + | Unofficial name. |
− | * [[#TSEC_FALCON_WDTMRVAL|TSEC_FALCON_WDTMRVAL]]
| + | |
− | * [[#TSEC_FALCON_WDTMRCTL|TSEC_FALCON_WDTMRCTL]]
| + | Controls accesses to the [[#TSEC_FALCON_CPUCTL|TSEC_FALCON_CPUCTL]] register. |
| | | |
− | === TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW === | + | === TSEC_FALCON_SPROT_MISC === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-31 | + | | 0-2 |
− | | TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL | + | | Read access level |
− | |} | + | |- |
| + | | 3 |
| + | | Set on memory read access violation |
| + | |- |
| + | | 4-6 |
| + | | Write access level |
| + | |- |
| + | | 7 |
| + | | Set on memory write access violation |
| + | |} |
| | | |
− | === TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH === | + | Unofficial name. |
| + | |
| + | Controls accesses to the following registers: |
| + | * [[#TSEC_FALCON_PRIVSTATE|TSEC_FALCON_PRIVSTATE]] |
| + | * [[#TSEC_FALCON_SFTRESET|TSEC_FALCON_SFTRESET]] |
| + | * [[#TSEC_FALCON_ADDR|TSEC_FALCON_ADDR]] |
| + | * [[#TSEC_FALCON_DMACTL|TSEC_FALCON_DMACTL]] |
| + | * [[#TSEC_FALCON_IMCTL|TSEC_FALCON_IMCTL]] |
| + | * [[#TSEC_FALCON_IMSTAT|TSEC_FALCON_IMSTAT]] |
| + | * [[#TSEC_FALCON_SCTL1|TSEC_FALCON_SCTL1]] |
| + | * [[#TSEC_FALCON_DMAINFO_CTL|TSEC_FALCON_DMAINFO_CTL]] |
| + | |
| + | === TSEC_FALCON_SPROT_IRQ === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-30 | + | | 0-2 |
− | | TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL | + | | Read access level |
| + | |- |
| + | | 3 |
| + | | Set on memory read access violation |
| + | |- |
| + | | 4-6 |
| + | | Write access level |
| |- | | |- |
− | | 31 | + | | 7 |
− | | TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT | + | | Set on memory write access violation |
| |} | | |} |
| | | |
− | === TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW === | + | Unofficial name. |
| + | |
| + | Controls accesses to the following registers: |
| + | * [[#TSEC_FALCON_IRQMODE|TSEC_FALCON_IRQMODE]] |
| + | * [[#TSEC_FALCON_IRQMSET|TSEC_FALCON_IRQMSET]] |
| + | * [[#TSEC_FALCON_IRQMCLR|TSEC_FALCON_IRQMCLR]] |
| + | * [[#TSEC_FALCON_IRQDEST|TSEC_FALCON_IRQDEST]] |
| + | * [[#TSEC_FALCON_GPTMRINT|TSEC_FALCON_GPTMRINT]] |
| + | * [[#TSEC_FALCON_GPTMRVAL|TSEC_FALCON_GPTMRVAL]] |
| + | * [[#TSEC_FALCON_GPTMRCTL|TSEC_FALCON_GPTMRCTL]] |
| + | * [[#TSEC_FALCON_IRQDEST2|TSEC_FALCON_IRQDEST2]] |
| + | * [[#TSEC_FALCON_SIRQMASK|TSEC_FALCON_SIRQMASK]] |
| + | |
| + | === TSEC_FALCON_SPROT_MTHD === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-31 | + | | 0-2 |
− | | TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL | + | | Read access level |
| + | |- |
| + | | 3 |
| + | | Set on memory read access violation |
| + | |- |
| + | | 4-6 |
| + | | Write access level |
| + | |- |
| + | | 7 |
| + | | Set on memory write access violation |
| |} | | |} |
| | | |
− | === TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH === | + | Unofficial name. |
| + | |
| + | Controls accesses to the following registers: |
| + | * [[#TSEC_FALCON_ITFEN|TSEC_FALCON_ITFEN]] |
| + | * [[#TSEC_FALCON_CURCTX|TSEC_FALCON_CURCTX]] |
| + | * [[#TSEC_FALCON_NXTCTX|TSEC_FALCON_NXTCTX]] |
| + | * [[#TSEC_FALCON_CTXACK|TSEC_FALCON_CTXACK]] |
| + | * [[#TSEC_FALCON_MTHDDATA|TSEC_FALCON_MTHDDATA]] |
| + | * [[#TSEC_FALCON_MTHDID|TSEC_FALCON_MTHDID]] |
| + | * [[#TSEC_FALCON_MTHDWDAT|TSEC_FALCON_MTHDWDAT]] |
| + | * [[#TSEC_FALCON_MTHDCOUNT|TSEC_FALCON_MTHDCOUNT]] |
| + | * [[#TSEC_FALCON_MTHDPOP|TSEC_FALCON_MTHDPOP]] |
| + | * [[#TSEC_FALCON_MTHDRAMSZ|TSEC_FALCON_MTHDRAMSZ]] |
| + | * [[#TSEC_FALCON_DEBUG1|TSEC_FALCON_DEBUG1]] |
| + | |
| + | === TSEC_FALCON_SPROT_SCTL === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-30 | + | | 0-2 |
− | | TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL | + | | Read access level |
| + | |- |
| + | | 3 |
| + | | Set on memory read access violation |
| + | |- |
| + | | 4-6 |
| + | | Write access level |
| |- | | |- |
− | | 31 | + | | 7 |
− | | TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT | + | | Set on memory write access violation |
| |} | | |} |
| | | |
− | === TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW === | + | Unofficial name. |
| + | |
| + | Controls accesses to the [[#TSEC_FALCON_SCTL|TSEC_FALCON_SCTL]] register. |
| + | |
| + | === TSEC_FALCON_SPROT_WDTMR === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-31 | + | | 0-2 |
− | | TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL | + | | Read access level |
| + | |- |
| + | | 3 |
| + | | Set on memory read access violation |
| + | |- |
| + | | 4-6 |
| + | | Write access level |
| + | |- |
| + | | 7 |
| + | | Set on memory write access violation |
| + | |} |
| + | |
| + | Unofficial name. |
| + | |
| + | Controls accesses to the following registers: |
| + | * [[#TSEC_FALCON_WDTMRVAL|TSEC_FALCON_WDTMRVAL]] |
| + | * [[#TSEC_FALCON_WDTMRCTL|TSEC_FALCON_WDTMRCTL]] |
| + | |
| + | === TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-31 |
| + | | TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL |
| |} | | |} |
| | | |
− | === TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH === | + | === TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 3,528: |
Line 3,587: |
| |- | | |- |
| | 0-30 | | | 0-30 |
− | | TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL | + | | TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL |
| |- | | |- |
| | 31 | | | 31 |
− | | TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT | + | | TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT |
| |} | | |} |
| | | |
− | === TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW === | + | === TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 3,540: |
Line 3,599: |
| |- | | |- |
| | 0-31 | | | 0-31 |
− | | TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL | + | | TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL |
| |} | | |} |
| | | |
− | === TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH === | + | === TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 3,549: |
Line 3,608: |
| |- | | |- |
| | 0-30 | | | 0-30 |
− | | TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL | + | | TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL |
| |- | | |- |
| | 31 | | | 31 |
− | | TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT | + | | TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT |
| |} | | |} |
| | | |
− | === TSEC_FALCON_DMAINFO_CTL === | + | === TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0 | + | | 0-31 |
− | | TSEC_FALCON_DMAINFO_CTL_CLR_FBRD | + | | TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL |
| + | |} |
| + | |
| + | === TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-30 |
| + | | TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL |
| + | |- |
| + | | 31 |
| + | | TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT |
| + | |} |
| + | |
| + | === TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-31 |
| + | | TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL |
| + | |} |
| + | |
| + | === TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0-30 |
| + | | TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL |
| + | |- |
| + | | 31 |
| + | | TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT |
| + | |} |
| + | |
| + | === TSEC_FALCON_DMAINFO_CTL === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| + | |- |
| + | | 0 |
| + | | TSEC_FALCON_DMAINFO_CTL_CLR_FBRD |
| |- | | |- |
| | 1 | | | 1 |
Line 3,587: |
Line 3,688: |
| | Enable [[#CTL|CTL]] | | | Enable [[#CTL|CTL]] |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_CTL1 === | | === TSEC_SCP_CTL1 === |
Line 3,614: |
Line 3,717: |
| | Enable [[#STORE|Falcon<->STORE]] interface bypassing (all writes are dropped) | | | Enable [[#STORE|Falcon<->STORE]] interface bypassing (all writes are dropped) |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_CTL_STAT === | | === TSEC_SCP_CTL_STAT === |
Line 3,631: |
Line 3,736: |
| | 0 | | | 0 |
| | Enable lockdown mode (locks IMEM and DMEM) | | | Enable lockdown mode (locks IMEM and DMEM) |
| + | |- |
| + | | 1 |
| + | | Lockdown has pending exit request |
| + | |- |
| + | | 2 |
| + | | Lockdown has been enabled before |
| |- | | |- |
| | 4 | | | 4 |
− | | Lock [[#SCP|SCP]]'s MMIO register space | + | | Enable SCP lockdown mode (locks [[#SCP|SCP]]'s MMIO register space) |
| + | |- |
| + | | 6 |
| + | | SCP lockdown has been enabled before |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| Controls lockdown mode. Can only be cleared in HS mode. | | Controls lockdown mode. Can only be cleared in HS mode. |
Line 3,681: |
Line 3,797: |
| | [[#SCP|SCP]]'s internal pipeline stall timeout value | | | [[#SCP|SCP]]'s internal pipeline stall timeout value |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_CTL_SCP === | | === TSEC_SCP_CTL_SCP === |
Line 3,695: |
Line 3,813: |
| 1: External | | 1: External |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_CTL_PKEY === | | === TSEC_SCP_CTL_PKEY === |
Line 3,717: |
Line 3,837: |
| |- | | |- |
| | 8 | | | 8 |
− | | Disable locking of [[#SCP|SCP]]'s MMIO register space | + | | Disable SCP lockdown mode |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| Overrides lockdown mode. Can only be set in debug mode. | | Overrides lockdown mode. Can only be set in debug mode. |
Line 3,770: |
Line 3,892: |
| | [[#STORE|STORE]] is running in HS mode | | | [[#STORE|STORE]] is running in HS mode |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| Used for debugging the [[#LOAD|LOAD]], [[#STORE|STORE]] and [[#SEQ|SEQ]] blocks. | | Used for debugging the [[#LOAD|LOAD]], [[#STORE|STORE]] and [[#SEQ|SEQ]] blocks. |
Line 3,785: |
Line 3,909: |
| Bits 10-14: current instruction's opcode | | Bits 10-14: current instruction's opcode |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| Used for retrieving debug data. Contains information on the last crypto sequence created when debugging the [[#SEQ|SEQ]] block. | | Used for retrieving debug data. Contains information on the last crypto sequence created when debugging the [[#SEQ|SEQ]] block. |
Line 3,805: |
Line 3,931: |
| | Active crypto key register (ckeyreg) | | | Active crypto key register (ckeyreg) |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| Used for retrieving additional debug data associated with the [[#SEQ|SEQ]] block. | | Used for retrieving additional debug data associated with the [[#SEQ|SEQ]] block. |
Line 3,853: |
Line 3,981: |
| | [[#CMD|CMD]] is running in HS mode | | | [[#CMD|CMD]] is running in HS mode |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| Contains information on the last crypto command executed. | | Contains information on the last crypto command executed. |
Line 3,885: |
Line 4,015: |
| | [[#RNG|RNG]] is active | | | [[#RNG|RNG]] is active |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| Contains the statuses of hardware blocks. | | Contains the statuses of hardware blocks. |
Line 3,918: |
Line 4,050: |
| | [[#CMD|Falcon<->CMD]] interface received a valid instruction | | | [[#CMD|Falcon<->CMD]] interface received a valid instruction |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| Contains the statuses of hardware interfaces and the result of the last authentication attempt. | | Contains the statuses of hardware interfaces and the result of the last authentication attempt. |
Line 3,960: |
Line 4,094: |
| | [[#AES|AES]] is stalled | | | [[#AES|AES]] is stalled |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| Contains the status of crypto operations. | | Contains the status of crypto operations. |
Line 3,983: |
Line 4,119: |
| | Unknown | | | Unknown |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_RNG_STAT1 === | | === TSEC_SCP_RNG_STAT1 === |
Line 3,995: |
Line 4,133: |
| | Unknown | | | Unknown |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_IRQSTAT === | | === TSEC_SCP_IRQSTAT === |
Line 4,022: |
Line 4,162: |
| | Stall timeout | | | Stall timeout |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_IRQMASK === | | === TSEC_SCP_IRQMASK === |
Line 4,049: |
Line 4,191: |
| | Stall timeout | | | Stall timeout |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_ACL_ERR === | | === TSEC_SCP_ACL_ERR === |
Line 4,067: |
Line 4,211: |
| | ACL error occurred | | | ACL error occurred |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|ACL error]] IRQ. | | Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|ACL error]] IRQ. |
Line 4,118: |
Line 4,264: |
| | SEC error occurred | | | SEC error occurred |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|SEC error]] IRQ. | | Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|SEC error]] IRQ. |
Line 4,147: |
Line 4,295: |
| | Forbidden ACL change (cchmod in NS mode) | | | Forbidden ACL change (cchmod in NS mode) |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|CMD error]] IRQ. | | Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|CMD error]] IRQ. |
Line 4,158: |
Line 4,308: |
| | [[#RND|RND]] clock trigger's lower limit | | | [[#RND|RND]] clock trigger's lower limit |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_RND_CTL1 === | | === TSEC_SCP_RND_CTL1 === |
Line 4,170: |
Line 4,322: |
| | [[#RND|RND]] clock trigger's mask | | | [[#RND|RND]] clock trigger's mask |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_RND_CTL2 === | | === TSEC_SCP_RND_CTL2 === |
Line 4,179: |
Line 4,333: |
| | Unknown | | | Unknown |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_RND_CTL3 === | | === TSEC_SCP_RND_CTL3 === |
Line 4,191: |
Line 4,347: |
| | Trigger second LFSR | | | Trigger second LFSR |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_RND_CTL4 === | | === TSEC_SCP_RND_CTL4 === |
Line 4,200: |
Line 4,358: |
| | First LFSR's polynomial for [[#RNG|RNG]]'s test mode | | | First LFSR's polynomial for [[#RNG|RNG]]'s test mode |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_RND_CTL5 === | | === TSEC_SCP_RND_CTL5 === |
Line 4,209: |
Line 4,369: |
| | First LFSR's initial state for [[#RNG|RNG]]'s test mode | | | First LFSR's initial state for [[#RNG|RNG]]'s test mode |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_RND_CTL6 === | | === TSEC_SCP_RND_CTL6 === |
Line 4,218: |
Line 4,380: |
| | Second LFSR's polynomial for [[#RNG|RNG]]'s test mode | | | Second LFSR's polynomial for [[#RNG|RNG]]'s test mode |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_RND_CTL7 === | | === TSEC_SCP_RND_CTL7 === |
Line 4,227: |
Line 4,391: |
| | Second LFSR's initial state for [[#RNG|RNG]]'s test mode | | | Second LFSR's initial state for [[#RNG|RNG]]'s test mode |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_RND_CTL8 === | | === TSEC_SCP_RND_CTL8 === |
Line 4,239: |
Line 4,405: |
| | Unknown | | | Unknown |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_RND_CTL9 === | | === TSEC_SCP_RND_CTL9 === |
Line 4,251: |
Line 4,419: |
| | Unknown | | | Unknown |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_RND_CTL10 === | | === TSEC_SCP_RND_CTL10 === |
Line 4,263: |
Line 4,433: |
| | Unknown | | | Unknown |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_SCP_RND_CTL11 === | | === TSEC_SCP_RND_CTL11 === |
Line 4,313: |
Line 4,485: |
| | Unknown | | | Unknown |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| === TSEC_TFBIF_CTL === | | === TSEC_TFBIF_CTL === |
Line 4,548: |
Line 4,722: |
| |} | | |} |
| | | |
− | === TSEC_TFBIF_WRR_RDP === | + | === TSEC_TFBIF_SPROT_EMEM === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-15 | + | | 0-2 |
− | | TSEC_TFBIF_WRR_RDP_EXT_WEIGHT | + | | Read access level |
| + | |- |
| + | | 3 |
| + | | Set on memory read access violation |
| |- | | |- |
− | | 16-31 | + | | 4-6 |
− | | TSEC_TFBIF_WRR_RDP_INT_WEIGHT | + | | Write access level |
− | |}
| |
− | | |
− | === TSEC_TFBIF_SPROT_EMEM ===
| |
− | {| class="wikitable" border="1"
| |
− | ! Bits
| |
− | ! Description
| |
| |- | | |- |
− | | 0-3 | + | | 7 |
− | | Read access level
| + | | Set on memory write access violation |
− | |-
| |
− | | 4-7
| |
− | | Write access level | |
| |} | | |} |
| + | |
| + | Unofficial name. |
| | | |
| Controls accesses to external memory regions. Accessible in HS mode only. | | Controls accesses to external memory regions. Accessible in HS mode only. |
Line 4,666: |
Line 4,836: |
| [6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout. | | [6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout. |
| | | |
− | === TSEC_TFBIF_ACTMON_ACTIVE_MASK === | + | === TSEC_CG === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0 | + | | 0-5 |
− | | TSEC_TFBIF_ACTMON_ACTIVE_MASK_STARVED_MC | + | | TSEC_CG_IDLE_CG_DLY_CNT |
| |- | | |- |
− | | 1 | + | | 6 |
− | | TSEC_TFBIF_ACTMON_ACTIVE_MASK_STALLED_MC | + | | TSEC_CG_IDLE_CG_EN |
| |- | | |- |
− | | 2 | + | | 16-18 |
− | | TSEC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED_MC | + | | TSEC_CG_WAKEUP_DLY_CNT |
| |- | | |- |
− | | 3 | + | | 19 |
− | | TSEC_TFBIF_ACTMON_ACTIVE_MASK_ACTIVE | + | | TSEC_CG_WAKEUP_DLY_EN |
| |} | | |} |
| | | |
− | Takes the memory access mask for the Activity Monitor. Disconnected on the TSEC.
| + | === TSEC_BAR0_CTL === |
− | | |
− | === TSEC_TFBIF_ACTMON_ACTIVE_BORPS === | |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 4,692: |
Line 4,860: |
| |- | | |- |
| | 0 | | | 0 |
− | | TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STARVED_MC_POLARITY | + | | TSEC_BAR0_CTL_READ |
| |- | | |- |
| | 1 | | | 1 |
− | | TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STARVED_MC_OPERATION | + | | TSEC_BAR0_CTL_WRITE |
| |- | | |- |
− | | 2 | + | | 4-7 |
− | | TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STALLED_MC_POLARITY | + | | TSEC_BAR0_CTL_BYTE_MASK |
| |- | | |- |
− | | 3 | + | | 12-13 |
− | | TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STALLED_MC_OPERATION | + | | TSEC_BAR0_CTL_STATUS |
| + | 0: Idle |
| + | 1: Busy |
| + | 2: Error |
| + | 3: Disabled |
| |- | | |- |
− | | 4 | + | | 16-17 |
− | | TSEC_TFBIF_ACTMON_ACTIVE_BORPS_DELAYED_MC_POLARITY | + | | TSEC_BAR0_CTL_SEC_MODE |
− | |-
| + | 0: Non-secure |
− | | 5
| + | 1: Invalid |
− | | TSEC_TFBIF_ACTMON_ACTIVE_BORPS_DELAYED_MC_OPERATION
| + | 2: Light Secure |
| + | 3: Heavy Secure |
| |- | | |- |
− | | 6 | + | | 31 |
− | | TSEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE_POLARITY | + | | TSEC_BAR0_CTL_INIT |
| + | |} |
| + | |
| + | Unofficial name. |
| + | |
| + | Controls DMA transfers between TSEC and HOST1X (master and clients). |
| + | |
| + | Starting a transfer over BAR0 automatically sets TSEC_BAR0_CTL_SEC_MODE to the current Falcon security mode. Once set, any attempts to start a transfer from a lower security level will fail. |
| + | |
| + | === TSEC_BAR0_ADDR === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| |- | | |- |
− | | 7 | + | | 0-31 |
− | | TSEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE_OPERATION | + | | TSEC_BAR0_ADDR_VAL |
| |} | | |} |
| | | |
− | Takes the billions of records per second count for the Activity Monitor. Disconnected on the TSEC.
| + | Unofficial name. |
| | | |
− | === TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT === | + | Takes the address for DMA transfers between TSEC and HOST1X (master and clients). |
| + | |
| + | === TSEC_BAR0_DATA === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 4,724: |
Line 4,911: |
| |- | | |- |
| | 0-31 | | | 0-31 |
− | | TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT_VAL | + | | TSEC_BAR0_DATA_VAL |
| |} | | |} |
| | | |
− | Controls the Activity Monitor. Disconnected on the TSEC.
| + | Unofficial name. |
| + | |
| + | Takes the data for DMA transfers between TSEC and HOST1X (master and clients). |
| | | |
− | === TSEC_TFBIF_ACTMON_MCB_MASK === | + | === TSEC_BAR0_TIMEOUT === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0 | + | | 0-31 |
− | | TSEC_TFBIF_ACTMON_MCB_MASK_STARVED_MC | + | | TSEC_BAR0_TIMEOUT_VAL |
| + | |} |
| + | |
| + | Unofficial name. |
| + | |
| + | Takes the timeout value for DMA transfers between TSEC and HOST1X (master and clients). |
| + | |
| + | === TSEC_VERSION === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| |- | | |- |
− | | 1 | + | | 0-31 |
− | | TSEC_TFBIF_ACTMON_MCB_MASK_STALLED_MC
| + | | Version |
− | |-
| |
− | | 2 | |
− | | TSEC_TFBIF_ACTMON_MCB_MASK_DELAYED_MC
| |
− | |-
| |
− | | 3
| |
− | | TSEC_TFBIF_ACTMON_MCB_MASK_ACTIVE
| |
| |} | | |} |
| | | |
− | Disconnected on the TSEC.
| + | Unofficial name. |
| | | |
− | === TSEC_TFBIF_ACTMON_MCB_BORPS === | + | === TSEC_SCRATCH0 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0 | + | | 0-31 |
− | | TSEC_TFBIF_ACTMON_MCB_BORPS_STARVED_MC_POLARITY | + | | Value |
| + | |} |
| + | |
| + | Unofficial name. |
| + | |
| + | === TSEC_SCRATCH1 === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| |- | | |- |
− | | 1 | + | | 0-31 |
− | | TSEC_TFBIF_ACTMON_MCB_BORPS_STARVED_MC_OPERATION
| + | | Value |
− | |-
| |
− | | 2 | |
− | | TSEC_TFBIF_ACTMON_MCB_BORPS_STALLED_MC_POLARITY
| |
− | |-
| |
− | | 3
| |
− | | TSEC_TFBIF_ACTMON_MCB_BORPS_STALLED_MC_OPERATION
| |
− | |-
| |
− | | 4
| |
− | | TSEC_TFBIF_ACTMON_MCB_BORPS_DELAYED_MC_POLARITY
| |
− | |-
| |
− | | 5
| |
− | | TSEC_TFBIF_ACTMON_MCB_BORPS_DELAYED_MC_OPERATION
| |
− | |-
| |
− | | 6
| |
− | | TSEC_TFBIF_ACTMON_MCB_BORPS_ACTIVE_POLARITY
| |
− | |-
| |
− | | 7
| |
− | | TSEC_TFBIF_ACTMON_MCB_BORPS_ACTIVE_OPERATION
| |
| |} | | |} |
| | | |
− | Disconnected on the TSEC.
| + | Unofficial name. |
| | | |
− | === TSEC_TFBIF_ACTMON_MCB_WEIGHT === | + | === TSEC_SCRATCH2 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 4,787: |
Line 4,970: |
| |- | | |- |
| | 0-31 | | | 0-31 |
− | | TSEC_TFBIF_ACTMON_MCB_WEIGHT_VAL | + | | Value |
| |} | | |} |
| | | |
− | Disconnected on the TSEC.
| + | Unofficial name. |
| | | |
− | === TSEC_TFBIF_THI_TRANSPROP === | + | === TSEC_SCRATCH3 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-6 | + | | 0-31 |
− | | TSEC_TFBIF_THI_TRANSPROP_STREAMID0 | + | | Value |
− | |-
| |
− | | 8-14
| |
− | | TSEC_TFBIF_THI_TRANSPROP_STREAMID1
| |
− | |-
| |
− | | 16
| |
− | | TSEC_TFBIF_THI_TRANSPROP_TZ_AUTH
| |
| |} | | |} |
| | | |
− | === TSEC_CG === | + | Unofficial name. |
| + | |
| + | === TSEC_SCRATCH4 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-5 | + | | 0-31 |
− | | TSEC_CG_IDLE_CG_DLY_CNT | + | | Value |
− | |-
| |
− | | 6
| |
− | | TSEC_CG_IDLE_CG_EN
| |
− | |-
| |
− | | 16-18
| |
− | | TSEC_CG_WAKEUP_DLY_CNT
| |
− | |-
| |
− | | 19
| |
− | | TSEC_CG_WAKEUP_DLY_EN
| |
| |} | | |} |
| | | |
− | === TSEC_BAR0_CTL === | + | Unofficial name. |
| + | |
| + | === TSEC_SCRATCH5 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0 | + | | 0-31 |
− | | TSEC_BAR0_CTL_READ | + | | Value |
| + | |} |
| + | |
| + | Unofficial name. |
| + | |
| + | === TSEC_SCRATCH6 === |
| + | {| class="wikitable" border="1" |
| + | ! Bits |
| + | ! Description |
| |- | | |- |
− | | 1 | + | | 0-31 |
− | | TSEC_BAR0_CTL_WRITE
| + | | Value |
− | |-
| |
− | | 4-7
| |
− | | TSEC_BAR0_CTL_BYTE_MASK
| |
− | |-
| |
− | | 12-13
| |
− | | TSEC_BAR0_CTL_STATUS
| |
− | 0: Idle
| |
− | 1: Busy
| |
− | 2: Error
| |
− | 3: Disabled
| |
− | |-
| |
− | | 16-17
| |
− | | TSEC_BAR0_CTL_SEC_MODE
| |
− | 0: Non-secure
| |
− | 1: Invalid
| |
− | 2: Light Secure
| |
− | 3: Heavy Secure
| |
− | |-
| |
− | | 31
| |
− | | TSEC_BAR0_CTL_INIT | |
| |} | | |} |
| | | |
− | Controls DMA transfers between TSEC and HOST1X (master and clients).
| + | Unofficial name. |
− | | |
− | Starting a transfer over BAR0 automatically sets TSEC_BAR0_CTL_SEC_MODE to the current Falcon security mode. Once set, any attempts to start a transfer from a lower security level will fail.
| |
| | | |
− | === TSEC_BAR0_ADDR === | + | === TSEC_SCRATCH7 === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
Line 4,867: |
Line 5,025: |
| |- | | |- |
| | 0-31 | | | 0-31 |
− | | TSEC_BAR0_ADDR_VAL | + | | Value |
| |} | | |} |
| | | |
− | Takes the address for DMA transfers between TSEC and HOST1X (master and clients).
| + | Unofficial name. |
| + | |
| + | === TSEC_GPTMRINT === |
| + | Unofficial name. |
| + | |
| + | Same as [[#TSEC_FALCON_GPTMRINT|TSEC_FALCON_GPTMRINT]], but for an unknown hardware block. |
| + | |
| + | === TSEC_GPTMRVAL === |
| + | Unofficial name. |
| + | |
| + | Same as [[#TSEC_FALCON_GPTMRVAL|TSEC_FALCON_GPTMRVAL]], but for an unknown hardware block. |
| + | |
| + | === TSEC_GPTMRCTL === |
| + | Unofficial name. |
| + | |
| + | Same as [[#TSEC_FALCON_GPTMRCTL|TSEC_FALCON_GPTMRCTL]], but for an unknown hardware block. |
| | | |
− | === TSEC_BAR0_DATA === | + | === TSEC_ITFEN === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-31 | + | | 0 |
− | | TSEC_BAR0_DATA_VAL | + | | Enable [[#TSEC_GPTMRINT|TSEC_GPTMRINT]] |
| + | |- |
| + | | 1 |
| + | | Unknown |
| + | |- |
| + | | 2 |
| + | | Unknown |
| + | |- |
| + | | 3 |
| + | | Unknown |
| |} | | |} |
| | | |
− | Takes the data for DMA transfers between TSEC and HOST1X (master and clients).
| + | Unofficial name. |
| | | |
− | === TSEC_BAR0_TIMEOUT === | + | === TSEC_ITFSTAT === |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bits | | ! Bits |
| ! Description | | ! Description |
| |- | | |- |
− | | 0-31 | + | | 0 |
− | | TSEC_BAR0_TIMEOUT_VAL | + | | [[#TSEC_GPTMRINT|TSEC_GPTMRINT]] is enabled |
| + | |- |
| + | | 1 |
| + | | Unknown |
| + | |- |
| + | | 2 |
| + | | Unknown |
| + | |- |
| + | | 3 |
| + | | Unknown |
| |} | | |} |
| | | |
− | Takes the timeout value for DMA transfers between TSEC and HOST1X (master and clients).
| + | Unofficial name. |
| | | |
| === TSEC_TEGRA_CTL === | | === TSEC_TEGRA_CTL === |