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Line 2,517: − + − | + + + + + + + + + − + − + − | 3+ − | − |- − | 4 − | Lock the SCP and RND − |- − | 5 − | − |- − | 6 − | − |- − | 7 − | − |} − − Controls lockdown mode and can only be cleared in Heavy Secure mode. − − === TSEC_SCP_CTL_PKEY === − {| class="wikitable" border="1" − ! Bits − ! Description − |- − | 0 − | TSEC_SCP_CTL_PKEY_REQUEST_RELOAD − |- − Line 2,543:
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Line 3,533: − − === cauth === − $cauth is a special purpose register in the CPU. − − {| class="wikitable" border="1" − ! Bits − ! Description − |- − | 0-7 || Start of region to authenticate (in 0x100 pages) − |- − | 8-15 || Unknown − |- − | 16 || Use secret xfers − |- − | 17 || Region is encrypted − |- − | 18 || Unknown (set in HS mode) − |- − | 19 || Block traps and interrupts (set in HS mode) − |- − | 20-23 || Unknown − |- − | 24-31 || Size of region to authenticate (in 0x100 pages) − |} − − === cxset === − cxset instruction provides a way to change behavior of a variable amount of successively executed DMA-related instructions. − − for example: <code>000000de: f4 3c 02 cxset 0x2</code> − − can be read as: <code>dma_override(type=crypto_reg, count=2)</code> − − The argument to cxset specifies the type of behavior change in the top 3 bits, and the number of DMA-related instructions the effect lasts for in the lower 5 bits. − − {| class=wikitable − ! Bits || Description − |- − | 0-4 || Number of instructions it is valid for (0x1f is a special value meaning infinitely many instructions -- until overriden by another cxset) − |- − | 5 || Crypto destination/source select (0=crypto register, 1=crypto stream) − |- − | 6 || External memory override (0=Disabled, 1=Enabled) − |- − | 7 || Internal memory select (0=DMEM, 1=IMEM) − |} − − ==== DMA-Related Instructions ==== − At least the following instructions may have changed behavior, and count against the cxset "count" argument: <code>xdwait</code>, <code>xdst</code>, <code>xdld</code>. − − For example, if override type=0b000, then the "length" argument to <code>xdst</code> is instead treated as the index of the target $cX register. − +
no edit summary
The TSEC's MMIO space is divided as follows:
The TSEC's MMIO space is divided as follows:
* 0x54500000 to 0x54501000: THI (Tegra Host Interface)
* 0x54500000 to 0x54501000: THI (Tegra Host Interface)
* 0x54501000 to 0x54501400: FALCON (Falcon microcontroller)
* 0x54501000 to 0x54501400: [[#Falcon|FALCON (Falcon microcontroller)]]
* 0x54501400 to 0x54501500: SCP (Secure Co-processor)
* 0x54501400 to 0x54501500: [[#SCP|SCP (Secure Co-processor)]]
* 0x54501500 to 0x54501600: RND (Random Number Generator)
* 0x54501500 to 0x54501600: RND (Random Number Generator)
* 0x54501600 to 0x54501680: TFBIF (Tegra Framebuffer Interface)
* 0x54501600 to 0x54501680: TFBIF (Tegra Framebuffer Interface)
| [[#FALCON_SSTAT|FALCON_SSTAT]]
| [[#FALCON_SSTAT|FALCON_SSTAT]]
| 0x54501244
| 0x54501244
| 0x04
| 0x04
|-
|-
| 0x04
| 0x04
|-
|-
| TSEC_SCP_CFG
| [[#TSEC_SCP_CFG|TSEC_SCP_CFG]]
| 0x54501410
| 0x54501410
| 0x04
| 0x04
| 0x04
| 0x04
|-
|-
| TSEC_SCP_STAT0
| [[#TSEC_SCP_STAT0|TSEC_SCP_STAT0]]
| 0x54501450
| 0x54501450
| 0x04
| 0x04
| 0x04
| 0x04
|-
|-
| TSEC_SCP_RND_STAT0
| [[#TSEC_SCP_RND_STAT0|TSEC_SCP_RND_STAT0]]
| 0x54501470
| 0x54501470
| 0x04
| 0x04
| 0x04
| 0x04
|-
|-
| TSEC_RND_CTL0
| [[#TSEC_RND_CTL0|TSEC_RND_CTL0]]
| 0x54501500
| 0x54501500
| 0x04
| 0x04
|-
|-
| TSEC_RND_CTL1
| [[#TSEC_RND_CTL1|TSEC_RND_CTL1]]
| 0x54501504
| 0x54501504
| 0x04
| 0x04
| 6-7
| 6-7
| FALCON_ICD_CMD_SZ
| FALCON_ICD_CMD_SZ
0x00: B (byte
0x00: B (byte)
0x01: HW (half word)
0x01: HW (half word)
0x02: W (word)
0x02: W (word)
|-
|-
| 20
| 20
| Enable the [[#TSEC_SCP_CMD|TSEC_SCP_CMD]] register
|-
| 16
| Enable the SEQ controller
|-
| 14
| Enable the CMD interface
| Enable the CMD interface
|-
| 12
| Enable the STORE interface
|-
| 10
| Enable the LOAD interface
|}
|}
! Bits
! Bits
! Description
! Description
|-
| 0
| Flush SEQ controller
|-
|-
| 11
| 11
| Enable RND testing mode
| Enable RND test mode
|-
|-
| 12
| 12
| Enable the RND interface
| Enable the RND controller
|}
=== TSEC_SCP_CFG ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 16-31
| Timeout value
|}
|}
| Enable lockdown mode
| Enable lockdown mode
|-
|-
| 1
| 4
| Lock SCP and RND
|}
Controls lockdown mode and can only be cleared in Heavy Secure mode.
=== TSEC_SCP_CTL_PKEY ===
{| class="wikitable" border="1"
! Bits
! Description
|-
|-
| 2
| 0
|
| TSEC_SCP_CTL_PKEY_REQUEST_RELOAD
|-
|-
| 1
| 1
| TSEC_SCP_CTL_PKEY_LOADED
| TSEC_SCP_CTL_PKEY_LOADED
|}
|}
|-
|-
| 0-3
| 0-3
| Sequence's instruction index
| Index
|-
|-
| 4-7
| 4
| Target and control flags
| Automatic increment
|-
| 5-6
| Target
0: None
1: Unknown
2: Unknown
3: SEQ
|-
|-
| 8-11
| 8-12
| Sequence's size
| SEQ size
|}
|}
Used for debugging crypto controllers such as the SEQ (crypto sequence).
=== TSEC_SCP_DBG1 ===
=== TSEC_SCP_DBG1 ===
|-
|-
| 0-3
| 0-3
| Sequence instruction's first operand
| SEQ instruction's first operand
|-
|-
| 4-9
| 4-9
| Sequence instruction's second operand
| SEQ instruction's second operand
|-
|-
| 10-14
| 10-14
| Sequence instruction's opcode
| SEQ instruction's opcode
|}
|}
Contains information on the last crypto sequence (cs0 or cs1) created.
Used for retrieving debug data. Contains information on the last crypto sequence created when debugging the SEQ controller.
=== TSEC_SCP_DBG2 ===
=== TSEC_SCP_DBG2 ===
! Description
! Description
|-
|-
| 0
| 0-1
| Set if crypto sequence recording (cs0begin/cs1begin) is active
| SEQ state
0: Idle
1: Recording is active (cs0begin/cs1begin)
|-
|-
| 4-7
| 4-7
| Number of instructions left for the crypto sequence
| Number of SEQ instructions left
|-
|-
| 12-15
| 12-15
|}
|}
Used for retrieving additional debug data associated with the SEQ controller.
=== TSEC_SCP_CMD ===
=== TSEC_SCP_CMD ===
|-
|-
| 0-3
| 0-3
| Destination register or immediate value
| Destination register
|-
|-
| 8-13
| 8-13
|-
|-
| 20-24
| 20-24
| Operation
| Command opcode
0x0: nop (fuc5 opcode 0x00)
0x0: nop (fuc5 opcode 0x00)
0x1: cmov (fuc5 opcode 0x84)
0x1: cmov (fuc5 opcode 0x84)
Contains information on the last crypto command executed.
Contains information on the last crypto command executed.
=== TSEC_SCP_STAT1 ===
=== TSEC_SCP_STAT0 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Bits
! Description
! Description
|-
|-
| 0-1
| 0
| Signature comparison result (3=succeeded, 2=failed)
| SCP is active
|}
|-
| 2
| CMD interface is active
|-
| 6
| SEQ controller is active
|-
| 14
| AES controller is active
|-
| 16
| RND controller is active
|}
Contains information on the last authentication attempt.
Contains the status of the crypto controllers and interfaces.
=== TSEC_SCP_STAT1 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| Signature comparison result
0: None
1: Running
2: Failed
3: Succeeded
|}
Contains the status of the last authentication attempt.
=== TSEC_SCP_STAT2 ===
=== TSEC_SCP_STAT2 ===
|-
|-
| 0-4
| 0-4
| First opcode
| Current SEQ opcode
|-
|-
| 5-9
| 5-9
| Second opcode
| Current CMD opcode
|-
| 10-14
| Pending CMD opcode
|-
|-
| 15-16
| 15-16
2: Key expansion
2: Key expansion
3: Key reverse expansion
3: Key reverse expansion
|-
| 25
| STORE operation is stalled
|-
| 26
| LOAD operation is stalled
|-
| 27
| RND operation is stalled
|-
| 29
| AES operation is stalled
|}
|}
Contains information on the last AES sequence executed.
Contains the status of crypto operations.
=== TSEC_SCP_RND_STAT0 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| RND is ready
|}
Contains the status of the RND controller.
=== TSEC_SCP_IRQSTAT ===
=== TSEC_SCP_IRQSTAT ===
|-
|-
| 24
| 24
|
| RND called
|-
|-
| 28
| 28
|
| Timeout
|}
|}
|-
|-
| 24
| 24
|
| RND called
|-
|-
| 28
| 28
|
| Timeout
|}
|}
|-
|-
| 0
| 0
| Set when writing to a crypto register without the correct ACL
| Writing to a crypto register without the correct ACL
|-
|-
| 4
| 4
| Set when reading from a crypto register without the correct ACL
| Reading from a crypto register without the correct ACL
|-
|-
| 8
| 8
| Set on an invalid ACL change (cchmod)
| Invalid ACL change (cchmod)
|-
|-
| 31
| 31
| An ACL error occurred
| ACL error occurred
|}
|}
Contains information on the status generated by the [[#TSEC_SCP_IRQSTAT|ACL error]] IRQ.
Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|ACL error]] IRQ.
=== TSEC_SCP_CMD_ERR ===
=== TSEC_SCP_CMD_ERR ===
|}
|}
Contains information on crypto errors generated by the [[#TSEC_SCP_IRQSTAT|CMD error]] IRQ.
Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|CMD error]] IRQ.
=== TSEC_RND_CTL0 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| RND clock trigger lower limit
|}
=== TSEC_RND_CTL1 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| RND clock trigger upper limit
|-
| 16-31
| RND clock trigger mask
|}
=== TSEC_TFBIF_CTL ===
=== TSEC_TFBIF_CTL ===
|-
|-
| 26
| 26
| TSEC_TEGRA_CTL_TMPI_RESTART_FSM_APB
| TSEC_TEGRA_CTL_TMPI_RESTART_FSM_APB
|-
|-
| 27
| 27
| TSEC_TEGRA_CTL_TMPI_DISABLE_OUTPUT_I2C
| TSEC_TEGRA_CTL_TMPI_DISABLE_OUTPUT_I2C
|}
|}
== Falcon ==
"Falcon" (FAst Logic CONtroller) is a proprietary general purpose CPU which can be found inside various hardware blocks that require some sort of logic processing such as TSEC (TSECA and TSECB), NVDEC, NVENC, NVJPG, VIC, GPU PMU and XUSB.
=== Processor Registers ===
A total of 32 processor registers are available in the Falcon CPU.
==== REG0-REG15 ====
These are 16 32-bit GPRs (general purpose registers).
==== IV0 ====
This is a SPR (special purpose register) that holds the address for interrupt vector 0.
==== IV1 ====
This is a SPR (special purpose register) that holds the address for interrupt vector 1.
==== IV2 ====
This is a SPR (special purpose register) that holds the address for interrupt vector 2. This register is considered "UNDEFINED" and appears to be unused.
==== EV ====
This is a SPR (special purpose register) that holds the address for the exception vector.
Alternative name (envytools): "tv".
==== SP ====
This is a SPR (special purpose register) that holds the current stack pointer.
==== PC ====
This is a SPR (special purpose register) that holds the current program counter.
==== IMB ====
This is a SPR (special purpose register) that holds the external base address for IMEM transfers.
Alternative name (envytools): "xcbase".
==== DMB ====
This is a SPR (special purpose register) that holds the external base address for DMEM transfers.
Alternative name (envytools): "xdbase".
==== CSW ====
This is a SPR (special purpose register) that holds various flag bits.
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7 || General purpose predicates
|-
| 8 || ALU carry flag
|-
| 9 || ALU signed overflow flag
|-
| 10 || ALU sign flag
|-
| 11 || ALU zero flag
|-
| 12-15 || Unused
|-
| 16 || Interrupt 0 enable
|-
| 17 || Interrupt 1 enable
|-
| 18 || Interrupt 2 enable (undefined)
|-
| 19 || Unused
|-
| 20 || Interrupt 0 saved enable
|-
| 21 || Interrupt 1 saved enable
|-
| 22 || Interrupt 2 saved enable (undefined)
|-
| 23 || Unused
|-
| 24 || Exception active
|-
| 25 || Unused
|-
| 26 || Unknown
|-
| 27-28 || Unused
|-
| 29 || Unknown
|-
| 30-31 || Unused
|}
Alternative name (envytools): "flags".
==== CCR ====
This is a SPR (special purpose register) that holds configuration bits for the SCP DMA override functionality. The value of this register is set using the "cxset" instruction which provides a way to change the behavior of a variable amount of successively executed DMA-related instructions ("xdwait", "xdst" and "xdld").
{| class=wikitable
! Bits || Description
|-
| 0-4 || Number of instructions the override is valid for (0x1F means infinite)
|-
| 5 || Crypto destination/source select
0: Crypto register
1: Crypto stream
|-
| 6 || External memory override
0: Disabled
1: Enabled
|-
| 7 || Internal memory select
0: DMEM
1: IMEM
|-
| 8-31 || Unused
|}
Alternative name (envytools): "cx".
==== SEC ====
This is a SPR (special purpose register) that holds configuration bits for the SCP authentication process.
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7 || Start of region to authenticate (in 0x100 pages)
|-
| 8-15 || Unused
|-
| 16 || Mark all subsequent code transfers as secret
|-
| 17 || Region is encrypted
|-
| 18 || Unknown (set in HS mode)
|-
| 19 || Block traps and interrupts (set in HS mode)
|-
| 20-23 || Unused
|-
| 24-31 || Size of region to authenticate (in 0x100 pages)
|}
Alternative name (envytools): "cauth".
==== CTX ====
This is a SPR (special purpose register) that holds configuration bits for the CTXDMA ports.
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2 || CTXDMA port for code loads (xcld)
|-
| 3 || Unused
|-
| 4-6 || CTXDMA port for code stores (invalid)
|-
| 7 || Unused
|-
| 8-10 || CTXDMA port for data loads (xdld)
|-
| 11 || Unused
|-
| 12-14 || CTXDMA port for data stores (xdst)
|-
| 15-31 || Unused
|}
Alternative name (envytools): "xtargets".
==== EXCI ====
This is a SPR (special purpose register) that holds information on raised exceptions.
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19 || Exception PC
|-
| 20-23 || Exception cause
|-
| 24-31 || Unused
|}
Alternative name (envytools): "tstatus".
==== SEC1 ====
Unknown. Marked as "RESERVED".
==== IMB1 ====
Unknown. Marked as "RESERVED".
==== DMB1 ====
Unknown. Marked as "RESERVED".
== SCP ==
== SCP ==
Part of the information here (which hasn't made it into envytools documentation yet) was shared by [https://wiki.0x04.net/wiki/Marcin_Ko%C5%9Bcielnicki mwk] from reverse engineering falcon processors over the years.
Part of the information here (which hasn't made it into envytools documentation yet) was shared by [https://wiki.0x04.net/wiki/Marcin_Ko%C5%9Bcielnicki mwk] from reverse engineering falcon processors over the years.
=== Authenticated Mode ===
=== Heavy Secure Mode ===
==== Entry ====
==== Entry ====
From non-secure mode, upon jumping to a page marked as secret, a secret fault occurs. This causes the CPU to verify the region specified in $cauth against the MAC loaded in $c6. If the comparison is successful, the valid bit (bit0) is set on all pages in the $cauth region, and $pc is set to the base of the $cauth region. If the comparsion fails, the CPU is halted.
From non-secure mode, upon jumping to a page marked as secret, a secret fault occurs. This causes the CPU to verify the region specified in $cauth against the MAC loaded in $c6. If the comparison is successful, the valid bit (bit0) is set on all pages in the $cauth region, and $pc is set to the base of the $cauth region. If the comparsion fails, the CPU is halted.
==== Implementation ====
==== Implementation ====
Under certain circumstances, it is possible to observe [[#csigauth|csigauth]] being briefly written to [[#TSEC_SCP_CMD|TSEC_SCP_CMD]] as "csigauth $c4 $c6" while the opcodes in [[#TSEC_SCP_STAT2|TSEC_SCP_STAT2]] are set to "cxsin" and "csigauth", respectively.
Under certain circumstances, it is possible to observe [[#sigauth|sigauth]] being briefly written to [[#TSEC_SCP_CMD|TSEC_SCP_CMD]] as "csigauth $c4 $c6" while the opcodes in [[#TSEC_SCP_STAT2|TSEC_SCP_STAT2]] are set to "cxsin" and "csigauth", respectively.
Via [[#TSEC_SCP_DBG0|TSEC_SCP_DBG0]] it can be observed that a 3-sized macro sequence is loaded into cs0 during a secure mode transition.
Via [[#TSEC_SCP_DBG0|TSEC_SCP_DBG0]] it can be observed that a 3-sized macro sequence is loaded into cs0 during a secure mode transition.
| 3 || sout || $cX || N/A || <code>write_stream($cX);</code> || ?
| 3 || sout || $cX || N/A || <code>write_stream($cX);</code> || ?
|-
|-
| 4 || rnd || $cX || N/A || <code>$cX = read_trng(); ACL(X) = ???;</code> ||
| 4 || [[#rnd|rnd]] || $cX || N/A || <code>$cX = read_rnd(); ACL(X) = ???;</code> ||
|-
|-
| 5 || s0begin || immX || N/A || <code>record_macro_for_N_instructions(0, immX);</code> ||
| 5 || s0begin || immX || N/A || <code>record_macro_for_N_instructions(0, immX);</code> ||
| 9 || <invalid> || || || ||
| 9 || <invalid> || || || ||
|-
|-
| 0xA || chmod || $cX || immY || Complicated, see [[#ACL|ACL]]. ||
| 0xA || [[#chmod|chmod]] || $cX || immY || Complicated, see [[#ACL|ACL]]. ||
|-
|-
| 0xB || xor || $cX || $cY || <code>$cX ^= $cY;</code> || <code>(ACL(X) & 2) && (ACL(Y) & 2)</code>
| 0xB || xor || $cX || $cY || <code>$cX ^= $cY;</code> || <code>(ACL(X) & 2) && (ACL(Y) & 2)</code>
| 0x15 || dec || $cX || $cY || <code>$cX = aes_dec(active_key_idx, $cY); ACL(X) = ACL(active_key_idx) & ACL(Y);</code> ||
| 0x15 || dec || $cX || $cY || <code>$cX = aes_dec(active_key_idx, $cY); ACL(X) = ACL(active_key_idx) & ACL(Y);</code> ||
|-
|-
| 0x16 || csigauth || $cX || $cY || <code>if (hash_verify($cX, $cY)) { has_sig = true; current_sig = $cX; }</code> || ?
| 0x16 || [[#sigauth|sigauth]] || $cX || $cY || <code>if (hash_verify($cX, $cY)) { has_sig = true; current_sig = $cX; }</code> || ?
|-
|-
| 0x17 || csigclr || N/A || N/A || <code>has_sig = false;</code> ||
| 0x17 || [[#sigclr|sigclr]] || N/A || N/A || <code>has_sig = false;</code> ||
|-
|-
| 0x18 || csigenc || $cX || $cY || <code>if (has_sig) { $cX = aes_enc($cY, current_sig); ACL(X) = 0x13; }</code> ||
| 0x18 || sigenc || $cX || $cY || <code>if (has_sig) { $cX = aes_enc($cY, current_sig); ACL(X) = 0x13; }</code> ||
|}
|}
==== csigauth ====
==== sigauth ====
<code>00000000: f5 3c XY d8 csigauth $cY $cX</code>
<code>00000000: f5 3c XY d8 csigauth $cY $cX</code>
Takes 2 crypto registers as operands and is automatically executed when jumping to a code region previously uploaded as secret. This instruction does not work in secure mode.
Takes 2 crypto registers as operands and is automatically executed when jumping to a code region previously uploaded as secret. This instruction does not work in secure mode.
==== csigclr ====
==== sigclr ====
<code>00000000: f5 3c 00 e0 csigclr</code>
<code>00000000: f5 3c 00 e0 csigclr</code>
This instruction takes no operands and appears to clear the saved cauth signature used by the csigenc instruction.
This instruction takes no operands and clears the saved cauth signature used by the csigenc instruction.
==== cchmod ====
==== chmod ====
<code>00000000: f5 3c XY a8 cchmod $cY 0X</code> or <code>00000000: f5 3c XY a9 cchmod $cY 1X</code>
<code>00000000: f5 3c XY a8 cchmod $cY 0X</code> or <code>00000000: f5 3c XY a9 cchmod $cY 1X</code>
This instruction takes a crypto register and a 5 bit immediate value which represents the [[#ACL|ACL]] mask to set.
This instruction takes a crypto register and a 5 bit immediate value which represents the [[#ACL|ACL]] mask to set.
==== crnd ====
==== rnd ====
<code>00000000: f5 3c 0X 90 crnd $cX</code>
<code>00000000: f5 3c 0X 90 crnd $cX</code>
This instruction initializes a crypto register with random data.
This instruction initializes a crypto register with random data.
Executing this instruction only succeeds if the TRNG is enabled for the SCP, which requires taking the following steps:
Executing this instruction only succeeds if the RND interface is enabled for the SCP, which requires taking the following steps:
* Write 0x7FFF to TSEC_RND_CTL0.
* Write 0x7FFF to [[#TSEC_RND_CTL0|TSEC_RND_CTL0]].
* Write 0x3FF0000 to TSEC_RND_CTL1.
* Write 0x3FF0000 to [[#TSEC_RND_CTL1|TSEC_RND_CTL1]].
* Write 0xFF00 to TSEC_RND_CTL11.
* Write 0xFF00 to TSEC_RND_CTL11.
* Write 0x1000 to [[#TSEC_SCP_CTL1|TSEC_SCP_CTL1]].
* Write 0x1000 to [[#TSEC_SCP_CTL1|TSEC_SCP_CTL1]].
Loading a secret into $cX sets a per-secret ACL, unconditionally.
Loading a secret into $cX sets a per-secret ACL, unconditionally.
=== Secrets ===
=== Secrets ===
Falcon's Authenticated Mode has access to 64 128-bit keys which are burned at factory. These keys can be loaded by using the $csecret instruction which takes the target crypto register and the key index as arguments.
Falcon's Heavy Secure Mode has access to 64 128-bit keys which are burned at factory. These keys can be loaded using the $csecret instruction which takes the target crypto register and the key index as arguments.
Secrets are specific to each Falcon unit with the exception of secret 0x3F. This secret is effectively empty (all zeros), but is configured to be overwritten with the KFUSE private key once the KFUSE clock is enabled. The KFUSE private key is console-unique.
Secrets are specific to each Falcon unit with the exception of secret 0x3F. This secret is effectively empty (all zeros), but is configured to be overwritten with the KFUSE private key once the KFUSE clock is enabled. The KFUSE private key is console-unique.