Nintendo Switch Brew

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TSEC (view source)

Revision as of 15:25, 12 August 2017

773 bytes added ,  15:25, 12 August 2017
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Like most Tegra based devices, the Switch's GPU also includes a Falcon microprocessor.
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TSEC (Tegra Security Engine Controller) is a NVIDIA Falcon microprocessor with crypto extensions. Therefore, all information in this page related to Falcon is identical for TSEC and vice versa.
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TSEC is a NVIDIA Falcon microprocessor with crypto extensions.
      
= Driver =
 
= Driver =
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= Boot Process =
 
= Boot Process =
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The Falcon is configured and initialized by the first bootloader during key generation (sub_400114FC).
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TSEC is configured and initialized by the first bootloader during key generation (sub_400114FC).
    
== Initialization ==
 
== Initialization ==
 
During this stage several clocks are programmed.
 
During this stage several clocks are programmed.
 
  // Program the HOST1X clock and resets
 
  // Program the HOST1X clock and resets
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  set_host1x_clkrst();
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  // Uses RST_DEVICES_L, CLK_OUT_ENB_L, CLK_SOURCE_HOST1X and CLK_L_HOST1X
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enable_host1x_clkrst();
 
   
 
   
 
  // Program the TSEC clock and resets
 
  // Program the TSEC clock and resets
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  set_tsec_clkrst();
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  // Uses RST_DEVICES_U, CLK_OUT_ENB_U, CLK_SOURCE_TSEC and CLK_U_TSEC
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enable_tsec_clkrst();
 
   
 
   
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  // Program the QSPI clock and resets (no source)
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  // Program the SOR_SAFE clock and resets
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  set_qspi_clkrst();
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  // Uses RST_DEVICES_Y, CLK_OUT_ENB_Y and CLK_Y_SOR_SAFE
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enable_sor_safe_clkrst();
 
   
 
   
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  // Program the SOR1 clock and resets (no source)
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  // Program the SOR0 clock and resets
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  set_sor1_clkrst0();
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  // Uses RST_DEVICES_X, CLK_OUT_ENB_X and CLK_X_SOR0
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enable_sor0_clkrst();
 
   
 
   
 
  // Program the SOR1 clock and resets
 
  // Program the SOR1 clock and resets
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  set_sor1_clkrst1();
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  // Uses RST_DEVICES_X, CLK_OUT_ENB_X, CLK_SOURCE_SOR1 and CLK_X_SOR1
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enable_sor1_clkrst();
 
   
 
   
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  // Enable clock and resets for H group
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  // Program the KFUSE clock resets
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  set_h_clkrst();
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// Uses RST_DEVICES_H, CLK_OUT_ENB_H and CLK_H_KFUSE
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  enable_kfuse_clkrst();
    
== Configuration ==
 
== Configuration ==
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  // Copy back the Falcon key
 
  // Copy back the Falcon key
 
  memcpy(out_buf, falcon_device_key, out_size);
 
  memcpy(out_buf, falcon_device_key, out_size);
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  // Deprogram UARTC and I2C5 clock and resets
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  // Deprogram KFUSE clock and resets
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  unset_uartc_i2c5_clkrst();
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  // Uses RST_DEVICES_H, CLK_OUT_ENB_H and CLK_H_KFUSE
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disable_kfuse_clkrst();
 
   
 
   
 
  // Deprogram SOR1 clock and resets
 
  // Deprogram SOR1 clock and resets
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  unset_sor1_clkrst1();
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  // Uses RST_DEVICES_X, CLK_OUT_ENB_X, CLK_SOURCE_SOR1 and CLK_X_SOR1
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disable_sor1_clkrst();
 
   
 
   
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  // Deprogram SOR1 clock and resets (no source)
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  // Deprogram SOR0 clock and resets
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  unset_sor1_clkrst0();
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  // Uses RST_DEVICES_X, CLK_OUT_ENB_X and CLK_X_SOR0
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disable_sor0_clkrst();
 
   
 
   
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  // Deprogram QSPI clock and resets (no source)
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  // Deprogram SOR_SAFE clock and resets
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  unset_qspi_clkrst();
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  // Uses RST_DEVICES_Y, CLK_OUT_ENB_Y and CLK_Y_SOR_SAFE
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disable_sor_safe_clkrst();
 
   
 
   
 
  // Deprogram TSEC clock and resets
 
  // Deprogram TSEC clock and resets
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  unset_tsec_clkrst();
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  // Uses RST_DEVICES_U, CLK_OUT_ENB_U, CLK_SOURCE_TSEC and CLK_U_TSEC
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disable_tsec_clkrst();
 
   
 
   
 
  // Deprogram HOST1X clock and resets
 
  // Deprogram HOST1X clock and resets
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  unset_host1x_clkrst()
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  // Uses RST_DEVICES_L, CLK_OUT_ENB_L, CLK_SOURCE_HOST1X and CLK_L_HOST1X
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disable_host1x_clkrst();
 
   
 
   
 
  return;
 
  return;
Retrieved from "https://switchbrew.org/wiki/Special:MobileDiff/2054"