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Line 1:
Line 1: − Like most Tegra based devices, the Switch's GPU also includes a Falcon microprocessor.+ − TSEC is a NVIDIA Falcon microprocessor with crypto extensions. Line 146:
Line 145: − The Falcon is configured and initialized by the first bootloader during key generation (sub_400114FC).+ − set_host1x_clkrst(); + + − set_tsec_clkrst(); + + − + − set_qspi_clkrst(); + + − + − set_sor1_clkrst0(); + + − set_sor1_clkrst1(); + + − + − set_h_clkrst(); + + Line 265:
Line 270: − + − + − unset_uartc_i2c5_clkrst(); + + − unset_sor1_clkrst1(); + + − + − unset_sor1_clkrst0(); + + − + − unset_qspi_clkrst(); + + − unset_tsec_clkrst(); + + − unset_host1x_clkrst() + +
no edit summary
TSEC (Tegra Security Engine Controller) is a NVIDIA Falcon microprocessor with crypto extensions. Therefore, all information in this page related to Falcon is identical for TSEC and vice versa.
= Driver =
= Driver =
= Boot Process =
= Boot Process =
TSEC is configured and initialized by the first bootloader during key generation (sub_400114FC).
== Initialization ==
== Initialization ==
During this stage several clocks are programmed.
During this stage several clocks are programmed.
// Program the HOST1X clock and resets
// Program the HOST1X clock and resets
// Uses RST_DEVICES_L, CLK_OUT_ENB_L, CLK_SOURCE_HOST1X and CLK_L_HOST1X
enable_host1x_clkrst();
// Program the TSEC clock and resets
// Program the TSEC clock and resets
// Uses RST_DEVICES_U, CLK_OUT_ENB_U, CLK_SOURCE_TSEC and CLK_U_TSEC
enable_tsec_clkrst();
// Program the QSPI clock and resets (no source)
// Program the SOR_SAFE clock and resets
// Uses RST_DEVICES_Y, CLK_OUT_ENB_Y and CLK_Y_SOR_SAFE
enable_sor_safe_clkrst();
// Program the SOR1 clock and resets (no source)
// Program the SOR0 clock and resets
// Uses RST_DEVICES_X, CLK_OUT_ENB_X and CLK_X_SOR0
enable_sor0_clkrst();
// Program the SOR1 clock and resets
// Program the SOR1 clock and resets
// Uses RST_DEVICES_X, CLK_OUT_ENB_X, CLK_SOURCE_SOR1 and CLK_X_SOR1
enable_sor1_clkrst();
// Enable clock and resets for H group
// Program the KFUSE clock resets
// Uses RST_DEVICES_H, CLK_OUT_ENB_H and CLK_H_KFUSE
enable_kfuse_clkrst();
== Configuration ==
== Configuration ==
// Copy back the Falcon key
// Copy back the Falcon key
memcpy(out_buf, falcon_device_key, out_size);
memcpy(out_buf, falcon_device_key, out_size);
// Deprogram UARTC and I2C5 clock and resets
// Deprogram KFUSE clock and resets
// Uses RST_DEVICES_H, CLK_OUT_ENB_H and CLK_H_KFUSE
disable_kfuse_clkrst();
// Deprogram SOR1 clock and resets
// Deprogram SOR1 clock and resets
// Uses RST_DEVICES_X, CLK_OUT_ENB_X, CLK_SOURCE_SOR1 and CLK_X_SOR1
disable_sor1_clkrst();
// Deprogram SOR1 clock and resets (no source)
// Deprogram SOR0 clock and resets
// Uses RST_DEVICES_X, CLK_OUT_ENB_X and CLK_X_SOR0
disable_sor0_clkrst();
// Deprogram QSPI clock and resets (no source)
// Deprogram SOR_SAFE clock and resets
// Uses RST_DEVICES_Y, CLK_OUT_ENB_Y and CLK_Y_SOR_SAFE
disable_sor_safe_clkrst();
// Deprogram TSEC clock and resets
// Deprogram TSEC clock and resets
// Uses RST_DEVICES_U, CLK_OUT_ENB_U, CLK_SOURCE_TSEC and CLK_U_TSEC
disable_tsec_clkrst();
// Deprogram HOST1X clock and resets
// Deprogram HOST1X clock and resets
// Uses RST_DEVICES_L, CLK_OUT_ENB_L, CLK_SOURCE_HOST1X and CLK_L_HOST1X
disable_host1x_clkrst();
return;
return;