Changes

Memory layout (view source)

Revision as of 03:48, 21 August 2017

315 bytes removed , 03:48, 21 August 2017

→‎TLS

Line 50: Line 50:

this->MapBaseAddr = BaseAddr + min(rnd0, rnd1)

this->HeapRegionBaseAddr = this->MapBaseAddr + MapRegionSize + max(rnd0, rnd1) - min(rnd0, rnd1)

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~~==TLS==~~

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~~This is the 0x200-byte thread-local-storage, the base address is loaded via ARM threadid register tpidrro_el0.~~

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~~{| class="wikitable" border="1"~~

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|-

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~~! Offset~~

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~~! Size~~

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~~! Description~~

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|-

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~~| 0x0~~

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~~| 0x100~~

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~~| [[IPC_Marshalling|IPC]] command buffer~~

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|-

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~~| 0x100~~

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~~| 0xF8~~

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~~| ?~~

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|-

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~~| 0x1F8~~

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~~| 0x8~~

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~~| Address of threadctx+0x58.~~

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|}

==Thread context==

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