Changes

Testpads (view source)

446 bytes added , 08:15, 15 May 2021

Notes on JTAG and lockout

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=== Cluster C ===

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The JTAG pins are multiplexed between NV_JTAG and ARM_JTAG by the TRST pin:

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* NV_JTAG contains a single TAP (ID 0x221173D7) for boundary scan board verification.

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* ARM_JTAG contains two debugging TAPs for CoreSight (ID 0x5BA00477) and BPMP (ID 0x4F1F0F0F).

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Note: NV_JTAG and ARM_JTAG are locked out by [[Fuses#Cache|FUSE_ARM_JTAG_DIS]] on production devices.

{| class=wikitable

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| 4 || JTAG_TCK || || 0-1.8V || || ||

|-

−

| 5 || JTAG_RTCK || || 0-1.8V || || ||

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| 5 || JTAG_RTCK || || 0-1.8V || || || Unused for NV_JTAG

|-

| 6 || UART1_RTS || || 0-1.8V || || || UART-A RTS Flow control

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| 9 || JTAG_TMS || || 0-1.8V || || ||

|-

−

| 10 || JTAG_TRST_N || || 0-1.8V || || ||

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| 10 || JTAG_TRST_N || || 0-1.8V || || || Not a TAP reset; Multiplexes between NV_JTAG (HI) and ARM_JTAG (LO)

|-

| 11 || +1.8V || || 0-1.8V || || ||

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