Memory layout: Difference between revisions
m →Kernel |
5.0.0 tz memory layout |
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| TZRAM | | TZRAM | ||
|} | |||
== [[5.0.0]] == | |||
5.0.0 modified the address map to have R-X, R--, and RW- segments, instead of a single RWX segment. | |||
Because the same L3 page is shared for all mappings, this required modifying segment layout significantly to prevent clashes. | |||
{| class="wikitable" border="1" | |||
|- | |||
! Vmem | |||
! Physmem | |||
! Size | |||
! Descriptor ORR-value | |||
! Description | |||
|- | |||
| 0x7C010000 | |||
| 0x7C010000 | |||
| 0x10000 | |||
| 0x300 | |||
| TZRAM Identity RWX (for init) | |||
|- | |||
| 0x40020000 | |||
| 0x40020000 | |||
| 0x20000 | |||
| 0x300 | |||
| IRAM Identity RWX (for init) | |||
|- | |||
| 0x1F0080000 | |||
| 0x50041000 | |||
| 0x1000 | |||
| 0x40000000000304 | |||
| ARM Interrupt Distributor | |||
|- | |||
| 0x1F0082000 | |||
| 0x50042000 | |||
| 0x2000 | |||
| 0x40000000000304 | |||
| Interrupt Controller Physical CPU | |||
|- | |||
| 0x1F0085000 | |||
| 0x70006000 | |||
| 0x1000 | |||
| 0x40000000000324 | |||
| UART-A | |||
|- | |||
| 0x1F0087000 | |||
| 0x60006000 | |||
| 0x1000 | |||
| 0x40000000000324 | |||
| Clock and Reset | |||
|- | |||
| 0x1F0089000 | |||
| 0x7000E000 | |||
| 0x1000 | |||
| 0x40000000000304 | |||
| PMC | |||
|- | |||
| 0x1F008B000 | |||
| 0x60005000 | |||
| 0x1000 | |||
| 0x40000000000304 | |||
| Timers | |||
|- | |||
| 0x1F008D000 | |||
| 0x6000C000 | |||
| 0x1000 | |||
| 0x40000000000304 | |||
| System Registers | |||
|- | |||
| 0x1F008F000 | |||
| 0x70012000 | |||
| 0x2000 | |||
| 0x40000000000304 | |||
| Security Engine | |||
|- | |||
| 0x1F00AD000 | |||
| 0x70412000 | |||
| 0x2000 | |||
| 0x40000000000304 | |||
| Undocumented/Not Present (Security Engine for Mariko?) | |||
|- | |||
| 0x1F0092000 | |||
| 0x700F0000 | |||
| 0x1000 | |||
| 0x40000000000304 | |||
| SYSCTR0 | |||
|- | |||
| 0x1F0094000 | |||
| 0x70019000 | |||
| 0x1000 | |||
| 0x40000000000304 | |||
| Memory Controller | |||
|- | |||
| 0x1F0096000 | |||
| 0x7000F000 | |||
| 0x1000 | |||
| 0x40000000000304 | |||
| Fuse Registers | |||
|- | |||
| 0x1F0098000 | |||
| 0x70000000 | |||
| 0x4000 | |||
| 0x40000000000304 | |||
| MISC Registers | |||
|- | |||
| 0x1F009D000 | |||
| 0x60007000 | |||
| 0x1000 | |||
| 0x40000000000304 | |||
| Flow Controller | |||
|- | |||
| 0x1F009F000 | |||
| 0x40002000 | |||
| 0x1000 | |||
| 0x40000000000304 | |||
| IRAM | |||
|- | |||
| 0x1F00A1000 | |||
| 0x7000D000 | |||
| 0x1000 | |||
| 0x40000000000304 | |||
| I2C-5 | |||
|- | |||
| 0x1F00A3000 | |||
| 0x6000D000 | |||
| 0x1000 | |||
| 0x40000000000304 | |||
| GPIO-1 | |||
|- | |||
| 0x1F00A5000 | |||
| 0x7000C000 | |||
| 0x1000 | |||
| 0x40000000000304 | |||
| I2C | |||
|- | |||
| 0x1F00A7000 | |||
| 0x6000F000 | |||
| 0x1000 | |||
| 0x40000000000304 | |||
| BPMP Exception Vectors | |||
|- | |||
| 0x1F00A9000 | |||
| 0x7001C000 | |||
| 0x1000 | |||
| 0x40000000000304 | |||
| MC0 | |||
|- | |||
| 0x1F00AB000 | |||
| 0x7001D000 | |||
| 0x1000 | |||
| 0x40000000000304 | |||
| MC1 | |||
|- | |||
| 0x1F0100000 | |||
| 0x7C010000 | |||
| 0x10000 | |||
| 0x40000000000380 | |||
| TZRAM (R-- for context save) | |||
|- | |||
| 0x1F0140000 | |||
| 0x7C012000 | |||
| 0x9000 | |||
| 0x300 | |||
| TZRAM (R-X .text) | |||
|- | |||
| 0x1F0149000 | |||
| 0x7C01B000 | |||
| 0x1000 | |||
| 0x40000000000300 | |||
| TZRAM (R-- .rodata) | |||
|- | |||
| 0x1F014A000 | |||
| 0x7C01C000 | |||
| 0x2000 | |||
| 0x40000000000300 | |||
| TZRAM (RW- .rwdata) | |||
|- | |||
| 0x1F01A0000 | |||
| 0x40020000 | |||
| 0x10000 | |||
| 0x40000000000324 | |||
| IRAM (RW- for context save) | |||
|- | |||
| 0x1F01B0000 | |||
| 0x40003000 | |||
| 0x1000 | |||
| 0x40000000000324 | |||
| IRAM (BPMP firmware destination) | |||
|- | |||
| 0x1F01C7000 | |||
| 0x8000F000 | |||
| 0x1000 | |||
| 0x40000000000324 | |||
| DRAM (SE Context Save destination) | |||
|- | |||
| 0x1F01E0000 | |||
| 0x7C010000 | |||
| 0x2000 | |||
| 0x300 | |||
| TZRAM (RWX pk2ldr for init) | |||
|- | |||
| 0x1F01F4000 | |||
| X | |||
| 0x1000 | |||
| 0x40000000000723 | |||
| DRAM (SPL .bss buffer visible to the Security Engine) | |||
|- | |||
| 0x1F01F6000 | |||
| 0x7C010000 | |||
| 0x1000 | |||
| 0x40000000000300 | |||
| TZRAM (stacks) | |||
|- | |||
| 0x1F01F8000 | |||
| 0x7C011000 | |||
| 0x1000 | |||
| 0x40000000000300 | |||
| TZRAM (stacks) | |||
|- | |||
| 0x1F01FA000 | |||
| 0x7C01D000 | |||
| 0x1000 | |||
| 0x40000000000300 | |||
| TZRAM (stacks, warmboot crt0) | |||
|- | |||
| 0x1F01FC000 | |||
| 0x7C01E000 | |||
| 0x1000 | |||
| 0x40000000000300 | |||
| TZRAM (L2 Page Table) | |||
|- | |||
| 0x1F01FE000 | |||
| 0x7C01F000 | |||
| 0x1000 | |||
| 0x40000000000300 | |||
| TZRAM (L3 Page Table) | |||
|- | |||
|} | |} | ||