@@ Line 243: / Line 243: @@
 | 0xFFFFFFF7FFDF9000
 | 0x800XX000
+|}
+= Secure Monitor =
+== [[2.0.0]] ==
+{| class="wikitable" border="1"
+|-
+! Vmem
+! Physmem
+! Size
+! Descriptor ORR-value
+! Permissions
+! Description
+|-
+| 0x7C010000
+| 0x7C010000
+| 0x10000
+| 0x300
+|
+| TZRAM
+|-
+| 0x40020000
+| 0x40020000
+| 0x20000
+| 0x300
+|
+| iRAM-C
+|-
+| 0x1F0080000
+| 0x50041000
+| 0x1000
+| 0x40000000000304
+|
+| ARM Interrupt Distributor
+|-
+| 0x1F0082000
+| 0x50042000
+| 0x2000
+| 0x40000000000304
+|
+| Interrupt Controller Physical CPU interface
+|-
+| 0x1F0085000
+| 0x70006000
+| 0x1000
+| 0x40000000000324
+|
+| UART-A
+|-
+| 0x1F0087000
+| 0x60006000
+| 0x1000
+| 0x40000000000324
+|
+| Clock and Reset
+|-
+| 0x1F0089000
+| 0x7000E000
+| 0x1000
+| 0x40000000000304
+|
+| RTC
+|-
+| 0x1F008B000
+| 0x60005000
+| 0x1000
+| 0x40000000000304
+|
+| TMR
+|-
+| 0x1F008D000
+| 0x6000C000
+| 0x1000
+| 0x40000000000304
+|
+| System Registers
+|-
+| 0x1F008F000
+| 0x70012000
+| 0x2000
+| 0x40000000000304
+|
+| SE
+|-
+| 0x1F0092000
+| 0x700F0000
+| 0x1000
+| 0x40000000000304
+|
+| SYSCTR0
+|-
+| 0x1F0094000
+| 0x70019000
+| 0x1000
+| 0x40000000000304
+|
+| MC
+|-
+| 0x1F0096000
+| 0x7000F000
+| 0x1000
+| 0x40000000000304
+|
+| FUSE (0x7000F800)
+|-
+| 0x1F0098000
+| 0x70000000
+| 0x4000
+| 0x40000000000304
+|
+| MISC
+|-
+| 0x1F009D000
+| 0x60007000
+| 0x1000
+| 0x40000000000304
+|
+| Flow Controller
+|-
+| 0x1F009F000
+| 0x40002000
+| 0x1000
+| 0x40000000000304
+|
+| iRAM-A
+|-
+| 0x1F00A1000
+| 0x7000D000
+| 0x1000
+| 0x40000000000304
+|
+| I2C5 - SPI 2B-6
+|-
+| 0x1F00A3000
+| 0x6000D000
+| 0x1000
+| 0x40000000000304
+|
+| GPIO-1 - GPIO-8
+|-
+| 0x1F00A5000
+| 0x7000C000
+| 0x1000
+| 0x40000000000304
+|
+| I2C-I2C4
+|-
+| 0x1F00A7000
+| 0x6000F000
+| 0x1000
+| 0x40000000000304
+|
+| Exception vectors
+|-
+| 0x1F0180000
+| 0x40020000
+| 0x10000
+| 0x40000000000324
+|
+| iRAM-C
+|-
+| 0x1F0190000
+| 0x40003000
+| 0x1000
+| 0x40000000000324
+|
+| iRAM-A
+|-
+| 0x1F01A0000
+| 0x7C010000
+| 0x10000
+| 0x40000000000380
+|
+| TZRAM
+|-
+| 0x1F01C3000
+| 0x80010000
+| 0x10000
+| 0x40000000000324
+|
+| EMEM
+|-
+| 0x1F01C2000
+| 0x8000F000
+| 0x1000
+| 0x40000000000324
+|
+| EMEM
+|-
+| 0x1F01E0000
+| 0x7C013000
+| 0xB000
+| 0x300
+|
+| TZRAM (Secure Monitor)
+|-
+| 0x1F01F0000
+| 0x7C01E000
+| 0x2000
+| 0x300
+|
+| TZRAM (Secure Monitor init)
+|-
+| 0x1F01F6000
+| 0x7C01E000
+| 0x1000
+| 0x40000000000300
+|
+| TZRAM
+|-
+| 0x1F01F8000
+| 0x7C01F000
+| 0x1000
+| 0x40000000000300
+|
+| TZRAM
+|-
+| 0x1F01FA000
+| 0x7C010000
+| 0x1000
+| 0x300
+|
+| TZRAM (Secure Monitor exception vectors)
+|-
+| 0x1F01FC000
+| 0x7C011000
+| 0x1000
+| 0x40000000000300
+|
+| TZRAM
+|-
+| 0x1F01FE000
+| 0x7C012000
+| 0x1000
+| 0x40000000000300
+|
+| TZRAM
 |}

Memory layout: Difference between revisions