GPU: Difference between revisions
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! Bits || Description | ! Bits || Description | ||
|- | |- | ||
| | | 0-11 || Method address | ||
|- | |||
| 12 || Reserved | |||
|- | |- | ||
| 13-15 || Method subchannel | | 13-15 || Method subchannel | ||
| Line 41: | Line 43: | ||
| 1 || [[#INC_METHOD|INC_METHOD]] | | 1 || [[#INC_METHOD|INC_METHOD]] | ||
|- | |- | ||
| 2 || | | 2 || [[#GRP2_USE_TERT|GRP2_USE_TERT]] | ||
|- | |- | ||
| 3 || [[#NON_INC_METHOD|NON_INC_METHOD]] | | 3 || [[#NON_INC_METHOD|NON_INC_METHOD]] | ||
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==== INC_METHOD ==== | ==== INC_METHOD ==== | ||
Tells PFIFO to read as much arguments as specified by '''method count''', while automatically incrementing the '''method address''' value. This means that each argument will be written to a different method location. | Tells PFIFO to read as much arguments as specified by '''method count''', while automatically incrementing the '''method address''' value. This means that each argument will be written to a different method location. | ||
==== GRP2_USE_TERT ==== | |||
Tells PFIFO to read [[#Tertiary opcode|tertiary opcode]] from bits 16-17 of the command word. | |||
==== NON_INC_METHOD ==== | ==== NON_INC_METHOD ==== | ||
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|- | |- | ||
! Mode || Description | ! Mode || Description | ||
|- | |||
| 0 || GRP0_INC_METHOD or GRP2_NON_INC_METHOD | |||
|- | |- | ||
| 1 || GRP0_SET_SUB_DEV_MASK | | 1 || GRP0_SET_SUB_DEV_MASK | ||
| Line 182: | Line 189: | ||
| 7 || FLOAT | | 7 || FLOAT | ||
|} | |} | ||
= Shaders = | |||
See [[GPU_Shaders|GPU Shaders]]. | |||
= References = | = References = | ||