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Line 3,325:
Line 3,325: + + + Line 4,710:
Line 4,713: + + + + + + + Line 4,715:
Line 4,725: − A BAR0 DMA read/write operation requires bits TSEC_BAR0_CTL_INIT and TSEC_BAR0_CTL_READ/TSEC_BAR0_CTL_WRITE to be set in TSEC_BAR0_CTL.+ − − During the transfer, TSEC_BAR0_CTL_STATUS is set to "Busy". − − Accessing an invalid address sets TSEC_BAR0_CTL_STATUS to "Error".
no edit summary
! Bits
! Bits
! Description
! Description
|-
| 30
| Unknown
|-
|-
| 31
| 31
2: Error
2: Error
3: Disabled
3: Disabled
|-
| 16-17
| TSEC_BAR0_CTL_SEC_MODE
0: None
1: Invalid
2: Light Secure
3: Heavy Secure
|-
|-
| 31
| 31
|}
|}
Controls DMA transfers between TSEC and HOST1X (master and clients).
=== TSEC_BAR0_ADDR ===
=== TSEC_BAR0_ADDR ===