2,928
edits
Changes
Jump to navigation
Jump to search
Line 4,787:
Line 4,787: − + − + Line 4,796:
Line 4,796: − + Line 4,832:
Line 4,832: − |- − | 12-15 || Unused Line 4,840:
Line 4,838: − |- − | 19 || Unused Line 4,848:
Line 4,844: − |- − | 23 || Unused − | 25 || Unused+ − |- − − |- − | 27-28 || Unused − |- − | 29 || Unknown − |- − | 30-31 || Unused Line 4,885:
Line 4,871: − |- − | 8-31 || Unused Line 4,899:
Line 4,883: − |- − | 8-15 || Unused Line 4,909:
Line 4,891: − |- − | 20-23 || Unused Line 4,925:
Line 4,905: − |- − | 3 || Unused − |- − | 7 || Unused − |- − | 11 || Unused − |- − | 15-31 || Unused Line 4,950:
Line 4,922: − + − |- − | 24-31 || Unused
no edit summary
==== IV0 ====
==== IV0 ====
This is a SPR (special purpose register) that holds the address for interrupt vector 0.
This is a SPR (special purpose register) that holds the address for interrupt vector 0. Only bits 0 to 15 are used.
==== IV1 ====
==== IV1 ====
This is a SPR (special purpose register) that holds the address for interrupt vector 1.
This is a SPR (special purpose register) that holds the address for interrupt vector 1. Only bits 0 to 15 are used.
==== IV2 ====
==== IV2 ====
==== EV ====
==== EV ====
This is a SPR (special purpose register) that holds the address for the exception vector.
This is a SPR (special purpose register) that holds the address for the exception vector. Only bits 0 to 15 are used.
Alternative name (envytools): "tv".
Alternative name (envytools): "tv".
|-
|-
| 11 || ALU zero flag
| 11 || ALU zero flag
|-
|-
| 16 || Interrupt 0 enable
| 16 || Interrupt 0 enable
|-
|-
| 18 || Interrupt 2 enable (undefined)
| 18 || Interrupt 2 enable (undefined)
|-
|-
| 20 || Interrupt 0 saved enable
| 20 || Interrupt 0 saved enable
|-
|-
| 22 || Interrupt 2 saved enable (undefined)
| 22 || Interrupt 2 saved enable (undefined)
|-
|-
| 24 || Exception active
| 24 || Exception active
|-
|-
| 26-31 || Unknown
| 26 || Unknown
|}
|}
0: DMEM
0: DMEM
1: IMEM
1: IMEM
|}
|}
|-
|-
| 0-7 || Start of region to authenticate (in 0x100 pages)
| 0-7 || Start of region to authenticate (in 0x100 pages)
|-
|-
| 16 || Mark all subsequent code transfers as secret
| 16 || Mark all subsequent code transfers as secret
|-
|-
| 19 || Block traps and interrupts (set in HS mode)
| 19 || Block traps and interrupts (set in HS mode)
|-
|-
| 24-31 || Size of region to authenticate (in 0x100 pages)
| 24-31 || Size of region to authenticate (in 0x100 pages)
|-
|-
| 0-2 || CTXDMA port for code loads (xcld)
| 0-2 || CTXDMA port for code loads (xcld)
|-
|-
| 4-6 || CTXDMA port for code stores (invalid)
| 4-6 || CTXDMA port for code stores (invalid)
|-
|-
| 8-10 || CTXDMA port for data loads (xdld)
| 8-10 || CTXDMA port for data loads (xdld)
|-
|-
| 12-14 || CTXDMA port for data stores (xdst)
| 12-14 || CTXDMA port for data stores (xdst)
|}
|}
! Description
! Description
|-
|-
| 0-19 || Exception PC
| 0-15 || Exception PC
|-
|-
| 20-23 || Exception cause
| 20-23 || Exception cause
|}
|}