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1,341 bytes added ,  06:17, 31 August 2019
Line 201: Line 201:  
     attribute = 0x60000000000708;
 
     attribute = 0x60000000000708;
 
     ttbr0_page_table.Map(page_tables_base, page_tables_size, page_tables_base, &attribute, allocator);
 
     ttbr0_page_table.Map(page_tables_base, page_tables_size, page_tables_base, &attribute, allocator);
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</pre>
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 +
Next, this sets some system registers.
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<pre>
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    // Set TTBR0/TTBR1 with initial page tables.
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    TTBR0_EL1 = ttbr0_page_table.GetL1Table();
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    TTBR1_EL1 = ttbr1_page_table.GetL1Table();
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    // Configure MAIR, TCR. TODO: Document here what bits these are.
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    MAIR_EL1 = 0x44FF0400;
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    TCR_EL1  = 0x11B5193519;
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    // Check what CPU we're running on to configure CPUECTLR, CPUACTLR appropriately.
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    manufacture_id = MIDR_EL1;
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    implemeter = manufacturer_id >> 24) & 0xFF;
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    if (implementer == 0x41) {
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        // Implementer ID is 0x41 (ARM Limited).
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        architecture = (manufacture_id >> 4)  & 0x0FFF;
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        hw_variant  = (manufacture_id >> 20) & 0xF;
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        hw_revision  = (manufacture_id >> 0)  & 0xF;
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        if (architecture == 0xD07) {
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            // Architecture is 0xD07 (Cortex-A57).
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            cpuactlr_value = 0x1000000;    // Non-cacheable load forwarding enabled
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            cpuectlr_value = 0x1B00000040; // TODO: What is this?
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            if (hw_variant == 0 || (hw_variant == 1 && hw_revision <= 1)) {
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                // If supported, disable load-pass DMB.
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                cpuactlr_value |= 0x800000000000000;
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            }
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            CPUACTLR_EL1 = cpuactlr_value;
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            if (CPUECTLR_EL1 != cpuectlr_value) {
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                CPUECTLR_EL1 = cpuectlr_value;
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            }
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        }
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    }
 
</pre>
 
</pre>
  

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