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138 bytes added ,  18:33, 17 July 2019
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* 0x54501500 to 0x54501600: TRNG (True Random Number Generator).
* 0x54501600 to 0x54501700: TFBIF (Tegra Framebuffer Interface) and CG (Clock Gate).
* 0x54501700 to 0x54501800: DMABAR0.
* 0x54501800 to 0x54501900: TEGRA (miscellaneous interfaces).
| 0x04
|-
| FALCON_EXTERRWINFALCON_CMEMBASE
| 0x54501160
| 0x04
|-
| FALCON_EXTERRCFGFALCON_DMEMAPERT
| 0x54501164
| 0x04
| 0x04
|-
| [[#TSEC_DMA_CMDTSEC_BAR0_CTL|TSEC_DMA_CMDTSEC_BAR0_CTL]]
| 0x54501700
| 0x04
|-
| [[#TSEC_DMA_ADDRTSEC_BAR0_ADDR|TSEC_DMA_ADDRTSEC_BAR0_ADDR]]
| 0x54501704
| 0x04
|-
| [[#TSEC_DMA_DATATSEC_BAR0_DATA|TSEC_DMA_DATATSEC_BAR0_DATA]]
| 0x54501708
| 0x04
|-
| [[#TSEC_DMA_TIMEOUTTSEC_BAR0_TIMEOUT|TSEC_DMA_TIMEOUTTSEC_BAR0_TIMEOUT]]
| 0x5450170C
| 0x04
|-
| 0
| FALCON_IRQMODE_GPTMRFALCON_IRQMODE_LVL_GPTMR
|-
| 1
| FALCON_IRQMODE_WDTMRFALCON_IRQMODE_LVL_WDTMR
|-
| 2
| FALCON_IRQMODE_MTHDFALCON_IRQMODE_LVL_MTHD
|-
| 3
| FALCON_IRQMODE_CTXSWFALCON_IRQMODE_LVL_CTXSW
|-
| 4
| FALCON_IRQMODE_HALTFALCON_IRQMODE_LVL_HALT
|-
| 5
| FALCON_IRQMODE_EXTERRFALCON_IRQMODE_LVL_EXTERR
|-
| 6
| FALCON_IRQMODE_SWGEN0FALCON_IRQMODE_LVL_SWGEN0
|-
| 7
| FALCON_IRQMODE_SWGEN1FALCON_IRQMODE_LVL_SWGEN1
|-
| 8-15
| FALCON_IRQMODE_EXTFALCON_IRQMODE_LVL_EXT
|}
|}
=== TSEC_DMA_CMD TSEC_BAR0_CTL ===
{| class="wikitable" border="1"
! Bits
|-
| 0
| TSEC_DMA_CMD_READTSEC_BAR0_CTL_READ
|-
| 1
| TSEC_DMA_CMD_WRITETSEC_BAR0_CTL_WRITE
|-
| 4-7
| TSEC_DMA_CMD_BYTE_MASKTSEC_BAR0_CTL_BYTE_MASK
|-
| 12-13
| TSEC_DMA_CMD_STATUSTSEC_BAR0_CTL_STATUS
0: Idle
1: Busy
|-
| 31
| TSEC_DMA_CMD_INITTSEC_BAR0_CTL_INIT
|}
A BAR0 DMA read/write operation requires bits TSEC_DMA_CMD_INIT TSEC_BAR0_CTL_INIT and TSEC_DMA_CMD_READTSEC_BAR0_CTL_READ/TSEC_DMA_CMD_WRITE TSEC_BAR0_CTL_WRITE to be set in TSEC_DMA_CMDTSEC_BAR0_CTL.
During the transfer, TSEC_DMA_CMD_STATUS TSEC_BAR0_CTL_STATUS is set to "Busy".
Accessing an invalid address sets TSEC_DMA_CMD_STATUS TSEC_BAR0_CTL_STATUS to "Error".
=== TSEC_DMA_ADDR TSEC_BAR0_ADDR ===
Takes the address for DMA transfers between TSEC and HOST1X (master and clients).
=== TSEC_DMA_DATA TSEC_BAR0_DATA ===
Takes the data for DMA transfers between TSEC and HOST1X (master and clients).
=== TSEC_DMA_TIMEOUT TSEC_BAR0_TIMEOUT ===Always 0xFFFTakes the timeout value for DMA transfers between TSEC and HOST1X (master and clients).
=== TSEC_TEGRA_CTL ===

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