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Line 2,233: − + − + − + − |-+ − | 13+ − | TSEC_DMA_CMD_ERROR+ + Line 2,230:
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no edit summary
| 0x04
| 0x04
|-
|-
| [[#TSEC_SCP_RES|TSEC_SCP_RES]]
| [[#TSEC_SCP_ACL_ERR|TSEC_SCP_ACL_ERR]]
| 0x54501490
| 0x54501490
| 0x04
| 0x04
| 0x04
| 0x04
|-
|-
| [[#TSEC_SCP_ERR|TSEC_SCP_ERR]]
| [[#TSEC_SCP_INSN_ERR|TSEC_SCP_INSN_ERR]]
| 0x54501498
| 0x54501498
| 0x04
| 0x04
|-
|-
| TSEC_TRNG_CLKDIV
| TSEC_TRNG_CLK_LIMIT_LOW
| 0x54501500
| 0x54501500
| 0x04
| 0x04
|-
|-
| TSEC_TRNG_UNK_04
| TSEC_TRNG_CLK_LIMIT_HIGH
| 0x54501504
| 0x54501504
| 0x04
| 0x04
| TSEC_TRNG_TEST_SEED1
| TSEC_TRNG_TEST_SEED1
| 0x5450151C
| 0x5450151C
| 0x04
|-
| TSEC_TRNG_UNK_20
| 0x54501520
| 0x04
|-
| TSEC_TRNG_UNK_24
| 0x54501524
| 0x04
| 0x04
|-
|-
| 0x04
| 0x04
|-
|-
| TSEC_TRNG_UNK_2C
| TSEC_TRNG_CTL
| 0x5450152C
| 0x5450152C
| 0x04
| 0x04
| 0x04
| 0x04
|-
|-
| [[#TSEC_DMA_VAL|TSEC_DMA_VAL]]
| [[#TSEC_DMA_DATA|TSEC_DMA_DATA]]
| 0x54501708
| 0x54501708
| 0x04
| 0x04
|-
|-
| [[#TSEC_DMA_CFG|TSEC_DMA_CFG]]
| [[#TSEC_DMA_TIMEOUT|TSEC_DMA_TIMEOUT]]
| 0x5450170C
| 0x5450170C
| 0x04
| 0x04
|-
|-
| 0
| 0
| Disable reads for the TRNG register block
| Disable reads for the SCP and TRNG register blocks
|-
|-
| 1
| 1
|-
|-
| 4
| 4
| Disable writes for the TRNG register block
| Disable writes for the SCP and TRNG register blocks
|-
|-
| 5
| 5
|}
|}
Locks accesses to the other sub-engines and can only be cleared in Heavy Secure mode.
Locks accesses to sub-engines and can only be cleared in Heavy Secure mode.
=== TSEC_SCP_CTL_PKEY ===
=== TSEC_SCP_CTL_PKEY ===
|-
|-
| 28
| 28
| Unknown
| Set if the instruction is valid
|-
|-
| 31
| 31
| Set if running in secure mode (cauth)
| Set if running in HS mode
|}
|}
|-
|-
| 8
| 8
| TSEC_SCP_IRQSTAT_HALT
| TSEC_SCP_IRQSTAT_ACL_ERROR
|-
|-
| 12
| 12
|-
|-
| 8
| 8
| TSEC_SCP_IRQMASK_HALT
| TSEC_SCP_IRQMASK_ACL_ERROR
|-
|-
| 12
| 12
Used for getting the value of the mask for crypto IRQs.
Used for getting the value of the mask for crypto IRQs.
=== TSEC_SCP_RES ===
=== TSEC_SCP_ACL_ERR ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Bits
! Description
! Description
|-
| 0
| Set when writing to a crypto register without the correct ACL
|-
| 4
| Set when reading from a crypto register without the correct ACL
|-
| 8
| Set on an invalid ACL change (cchmod)
|-
|-
| 31
| 31
| SCP is halted
| An ACL error occurred
|}
|}
Contains information on the status generated by the [[#TSEC_SCP_IRQSTAT|TSEC_SCP_IRQSTAT_HALT]] IRQ.
Contains information on the status generated by the [[#TSEC_SCP_IRQSTAT|TSEC_SCP_IRQSTAT_ACL_ERROR]] IRQ.
=== TSEC_SCP_ERR ===
=== TSEC_SCP_INSN_ERR ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Bits
|-
|-
| 16
| 16
| Invalid cauth signature (during csigenc, csigclr or csigauth)
| Insecure signature (csigenc, csigclr or csigauth)
|-
|-
| 20
| 20
| Wrong access level (during csigauth in HS mode)
| Invalid signature (csigauth in HS mode)
|-
|-
| 24
| 24
| Forbidden instruction (during cchmod in NS mode)
| Forbidden ACL change (cchmod in NS mode)
|}
|}
|-
|-
| 4-7
| 4-7
| TSEC_DMA_CMD_UNK
| TSEC_DMA_CMD_BYTE_MASK
|-
|-
| 12
| 12-13
| TSEC_DMA_CMD_BUSY
| TSEC_DMA_CMD_STATUS
0: Idle
1: Busy
2: Error
3: Disabled
|-
|-
| 31
| 31
A DMA read/write operation requires bits TSEC_DMA_CMD_INIT and TSEC_DMA_CMD_READ/TSEC_DMA_CMD_WRITE to be set in TSEC_DMA_CMD.
A DMA read/write operation requires bits TSEC_DMA_CMD_INIT and TSEC_DMA_CMD_READ/TSEC_DMA_CMD_WRITE to be set in TSEC_DMA_CMD.
During the transfer, the TSEC_DMA_CMD_BUSY bit is set.
During the transfer, TSEC_DMA_CMD_STATUS is set to "Busy".
Accessing an invalid address causes bit TSEC_DMA_CMD_ERROR to be set.
Accessing an invalid address sets TSEC_DMA_CMD_STATUS to "Error".
=== TSEC_DMA_ADDR ===
=== TSEC_DMA_ADDR ===
Takes the address for DMA transfers between TSEC and HOST1X (master and clients).
Takes the address for DMA transfers between TSEC and HOST1X (master and clients).
=== TSEC_DMA_VAL ===
=== TSEC_DMA_DATA ===
Takes the value for DMA transfers between TSEC and HOST1X (master and clients).
Takes the data for DMA transfers between TSEC and HOST1X (master and clients).
=== TSEC_DMA_CFG ===
=== TSEC_DMA_TIMEOUT ===
Always 0xFFF.
Always 0xFFF.
Executing this instruction only succeeds if the TRNG is enabled for the SCP, which requires taking the following steps:
Executing this instruction only succeeds if the TRNG is enabled for the SCP, which requires taking the following steps:
* Write 0x7FFF to TSEC_TRNG_CLKDIV.
* Write 0x7FFF to TSEC_TRNG_CLK_LIMIT_LOW.
* Write 0x3FF0000 to TSEC_TRNG_UNK_00.
* Write 0x3FF0000 to TSEC_TRNG_CLK_LIMIT_HIGH.
* Write 0xFF00 to TSEC_TRNG_UNK_2C.
* Write 0xFF00 to TSEC_TRNG_CTL.
* Write 0x1000 to [[#TSEC_SCP_CTL1|TSEC_SCP_CTL1]].
* Write 0x1000 to [[#TSEC_SCP_CTL1|TSEC_SCP_CTL1]].