Line 66: |
Line 66: |
| QueryEvent is only supported on (and implemented differently on): | | QueryEvent is only supported on (and implemented differently on): |
| * /dev/nvhost-gpu | | * /dev/nvhost-gpu |
− | ** 1: SmException_BptIntReport | + | ** EvtId=1: SmException_BptIntReport |
− | ** 2: SmException_BptPauseReport | + | ** EvtId=2: SmException_BptPauseReport |
− | ** 3: ErrorNotifierEvent | + | ** EvtId=3: ErrorNotifierEvent |
− | * /dev/nvhost-ctrl: Used to get events for SyncPts. | + | * /dev/nvhost-ctrl: Used to get events for syncpts. |
− | ** If bit31-28 is 1, then lower 16-bits contain event_slot, bit27-16 contain syncpt_number. | + | ** EvtId=(event_slot | ((syncpt_id & 0xFFF) << 16) | (is_valid << 28)): New format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]/[[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]]. |
− | ** If bit31-28 is 0, then lower 4-bits contain event_slot, bit31-4 contains syncpt_number. | + | ** EvtId=(event_slot | (syncpt_id << 4)): Old format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAITEX|NVHOST_IOCTL_CTRL_SYNCPT_WAITEX]]. |
| * /dev/nvhost-ctrl-gpu | | * /dev/nvhost-ctrl-gpu |
− | ** 1: Returns error_event_handle. | + | ** EvtId=1: Returns error_event_handle. |
− | ** 2: Returns unknown event. | + | ** EvtId=2: Returns unknown event. |
| * /dev/nvhost-dbg-gpu | | * /dev/nvhost-dbg-gpu |
− | ** Ignores event_id. | + | ** Ignores EvtId. |
| | | |
| == MapSharedMem == | | == MapSharedMem == |
Line 187: |
Line 187: |
| | 6 || [[#Reset|Reset]] | | | 6 || [[#Reset|Reset]] |
| |- | | |- |
− | | 7 || [3.0.0+] | + | | 7 || [3.0.0+] [[#GetAruid2|GetAruid2]] |
| |} | | |} |
| | | |
Line 210: |
Line 210: |
| == Reset == | | == Reset == |
| No input. Returns an output u32 '''Err'''. | | No input. Returns an output u32 '''Err'''. |
| + | |
| + | == GetAruid2 == |
| + | Unofficial name. |
| + | |
| + | No input. Returns an output u64 '''Aruid''', an output bool '''IsCoreDumpEnabled''' and an output u32 '''Err'''. |
| | | |
| = nvgem:cd = | | = nvgem:cd = |
Line 224: |
Line 229: |
| | 2 || [1.0.0-8.1.0] [[#ReadNextBlock|ReadNextBlock]] | | | 2 || [1.0.0-8.1.0] [[#ReadNextBlock|ReadNextBlock]] |
| |- | | |- |
− | | 3 || [8.0.0+] | + | | 3 || [8.0.0+] [[#GetNextBlockSize|GetNextBlockSize]] |
| |- | | |- |
− | | 4 || [8.0.0+] | + | | 4 || [8.0.0+] [[#ReadNextBlock2|ReadNextBlock2]] |
| |} | | |} |
| | | |
Line 237: |
Line 242: |
| == ReadNextBlock == | | == ReadNextBlock == |
| Takes a type-0x6 output buffer. Returns an output u32 '''Err'''. | | Takes a type-0x6 output buffer. Returns an output u32 '''Err'''. |
| + | |
| + | == GetNextBlockSize == |
| + | Unofficial name. |
| + | |
| + | No input. Returns an output u64 '''Size''' and an output u32 '''Err'''. |
| + | |
| + | == ReadNextBlock2 == |
| + | Unofficial name. |
| + | |
| + | Takes a type-0x6 output buffer and two input u64s '''Size''' and '''Offset'''. Returns an output u64 '''OutSize''' and an output u32 '''Err'''. |
| | | |
| = nvdbg:d = | | = nvdbg:d = |
Line 273: |
Line 288: |
| | 0xC004001C || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_CLEAR_EVENT_WAIT]] | | | 0xC004001C || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_CLEAR_EVENT_WAIT]] |
| |- | | |- |
− | | 0xC010001D || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_EVENT_WAIT]] | + | | 0xC010001D || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]] |
| |- | | |- |
− | | 0xC010001E || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_EVENT_WAIT_ASYNC]] | + | | 0xC010001E || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]] |
| |- | | |- |
− | | 0xC004001F || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_REGISTER_EVENT]] | + | | 0xC004001F || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_ALLOC_EVENT]] |
| |- | | |- |
− | | 0xC0040020 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_UNREGISTER_EVENT]] | + | | 0xC0040020 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT]] |
| |- | | |- |
− | | 0x40080021 || In || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENTS]] | + | | 0x40080021 || In || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT_BATCH]] |
| |- | | |- |
− | | 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_GET_MAX_EVENT_FIFO_CHANNEL]] | + | | 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT]] |
| |} | | |} |
| | | |
Line 315: |
Line 330: |
| struct { | | struct { |
| __in u32 id; | | __in u32 id; |
− | __in u32 lock; // (0==unlock; 1==lock) | + | __in u32 lock; // 0=unlock, 1=lock |
| }; | | }; |
| | | |
Line 352: |
Line 367: |
| | | |
| struct { | | struct { |
− | __in char domain_str[0x41]; // "nv" | + | __in char name[0x41]; // "nv" |
− | __in char param_str[0x41]; | + | __in char key[0x41]; |
− | __out char config_str[0x101]; | + | __out char value[0x101]; |
| }; | | }; |
| | | |
| === NVHOST_IOCTL_CTRL_SYNCPT_CLEAR_EVENT_WAIT === | | === NVHOST_IOCTL_CTRL_SYNCPT_CLEAR_EVENT_WAIT === |
− | Clears the wait signal of an event. Exclusive to the Switch. | + | Clears the wait signal of a syncpt event. |
| | | |
| struct { | | struct { |
− | __in u32 event_slot; // ranges from 0x00 to 0x3F | + | __in u32 event_slot; // 0x00 to 0x3F |
| }; | | }; |
| | | |
− | === NVHOST_IOCTL_CTRL_SYNCPT_EVENT_WAIT === | + | === NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT === |
− | Waits on an event. If waiting fails, returns error code 0x05 (Timeout) and sets '''value''' to (('''syncpt_id''' << 0x10) | 0x10000000). | + | Waits on a syncpt using events. If waiting fails, returns error code 0x05 (Timeout) and sets '''value''' to ('''event_slot''' | (('''syncpt_id''' & 0xFFF) << 16) | ('''is_valid''' << 28)). |
− | | |
− | Depending on '''threshold''', an '''event_slot''' may be returned for using with other event ioctls.
| |
| | | |
| struct { | | struct { |
− | __in u32 syncpt_id; | + | __in u32 id; |
− | __in u32 threshold; | + | __in u32 thresh; |
− | __in s32 timeout; | + | __in s32 timeout; |
− | __inout u32 value; // in=event_slot (ignored); out=syncpt_value or event_slot | + | __out u32 value; |
| }; | | }; |
| | | |
− | === NVHOST_IOCTL_CTRL_SYNCPT_EVENT_WAIT_ASYNC === | + | === NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX === |
− | Waits on an event (async version). If waiting fails, returns error code 0x0B (BadValue). | + | Waits on a syncpt using a specific event. If waiting fails, returns error code 0x05 (Timeout) and sets '''value''' to ('''event_slot''' | ('''syncpt_id''' << 4)). |
− | | |
− | Depending on '''threshold''', an '''event_slot''' may be returned for using with other event ioctls.
| |
| | | |
| struct { | | struct { |
− | __in u32 syncpt_id; | + | __in u32 id; |
− | __in u32 threshold; | + | __in u32 thresh; |
− | __in u32 timeout; | + | __in s32 timeout; |
− | __inout u32 value; // in=event_slot (ignored); out=syncpt_value or event_slot | + | __inout u32 value; // in=event_slot; out=syncpt_value |
| }; | | }; |
| | | |
− | === NVHOST_IOCTL_CTRL_SYNCPT_REGISTER_EVENT === | + | === NVHOST_IOCTL_CTRL_SYNCPT_ALLOC_EVENT === |
− | Registers an event. Exclusive to the Switch.
| + | Allocates a new syncpt event. |
| | | |
| struct { | | struct { |
− | __in u32 event_slot; // ranges from 0x00 to 0x3F | + | __in u32 event_slot; // 0x00 to 0x3F |
| }; | | }; |
| | | |
− | === NVHOST_IOCTL_CTRL_SYNCPT_UNREGISTER_EVENT === | + | === NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT === |
− | Unregisters an event. Exclusive to the Switch.
| + | Frees an existing syncpt event. |
| | | |
| struct { | | struct { |
− | __in u32 event_slot; // ranges from 0x00 to 0x3F | + | __in u32 event_slot; // 0x00 to 0x3F |
| }; | | }; |
| | | |
− | === NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENTS === | + | === NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT_BATCH === |
− | Frees events. Exclusive to the Switch. | + | Frees multiple syncpt events. |
| | | |
| struct { | | struct { |
− | __in u64 events; // 64-bit bitfield where each bit represents one event | + | __in u64 event_slot_mask; // 64-bit bitfield where each bit represents one event |
| }; | | }; |
| | | |
− | === NVHOST_IOCTL_CTRL_GET_MAX_EVENT_FIFO_CHANNEL === | + | === NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT === |
− | If event FIFO is enabled, returns the maximum channel number. Exclusive to the Switch.
| + | Returns the syncpt shift value. |
| | | |
| struct { | | struct { |
− | __out u32 max_channel; // 0x00 (FIFO disabled) or 0x60 (FIFO enabled) | + | __out u32 syncpt_shift; // 0x00 (FIFO disabled) or 0x60 (FIFO enabled) |
| }; | | }; |
| | | |
Line 499: |
Line 510: |
| __in u32 handle; | | __in u32 handle; |
| u32 pad; | | u32 pad; |
− | __out u64 address; | + | __out u64 address; // 0 if the handle wasn't yet freed |
| __out u32 size; | | __out u32 size; |
− | __out u32 flags; // 1=NOT_FREED_YET | + | __out u32 flags; // 1=WAS_UNCACHED (if flags bit 1 was set when NVMAP_IOC_ALLOC was called) |
| }; | | }; |
| | | |
Line 598: |
Line 609: |
| | 0xC0040220 || Inout || 4 || NVDISP_CTRL_SUSPEND | | | 0xC0040220 || Inout || 4 || NVDISP_CTRL_SUSPEND |
| |- | | |- |
− | | 0x80010224 || Out || 1 || [11.0.0+] | + | | 0x80010224 || Out || 1 || [11.0.0+] NVDISP_CTRL_IS_DISPLAY_OLED |
| |} | | |} |
| | | |
Line 655: |
Line 666: |
| | 0x80080221 || Out || 8 || [10.0.0+] [[#NVDISP_GET_BACKLIGHT_RANGE]] | | | 0x80080221 || Out || 8 || [10.0.0+] [[#NVDISP_GET_BACKLIGHT_RANGE]] |
| |- | | |- |
− | | 0x40040222 || In || 4 || [10.0.0+] [[#NVDISP_SET_BACKLIGHT]] | + | | 0x40040222 || In || 4 || [10.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MAX]] |
| |- | | |- |
− | | 0x40040223 || In || 4 || [11.0.0+] | + | | 0x40040223 || In || 4 || [11.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MIN]] |
| |- | | |- |
| | 0x401C0225 || In || 28 || [11.0.0+] [[#NVDISP_SEND_PANEL_MSG]] | | | 0x401C0225 || In || 28 || [11.0.0+] [[#NVDISP_SEND_PANEL_MSG]] |
Line 672: |
Line 683: |
| }; | | }; |
| | | |
− | === NVDISP_SET_BACKLIGHT === | + | === NVDISP_SET_BACKLIGHT_RANGE_MAX === |
− | Sets the value for the intensity of the display's backlight. | + | Sets the maximum value for the intensity of the display's backlight. |
| | | |
| struct { | | struct { |
− | __in u32 val; | + | __in u32 max; |
| + | }; |
| + | |
| + | === NVDISP_SET_BACKLIGHT_RANGE_MIN === |
| + | Sets the minimum value for the intensity of the display's backlight. |
| + | |
| + | struct { |
| + | __in u32 min; |
| }; | | }; |
| | | |
Line 904: |
Line 922: |
| struct { | | struct { |
| __in u32 fence_id; | | __in u32 fence_id; |
− | __in u32 fence_thresh; | + | __in u32 fence_value; |
| __in u32 swap_interval; | | __in u32 swap_interval; |
| }; | | }; |
Line 1,006: |
Line 1,024: |
| | 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX]] | | | 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX]] |
| |- | | |- |
− | | 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MODIFY]] | + | | 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX2]] |
| |- | | |- |
| | 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]] | | | 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]] |
Line 1,042: |
Line 1,060: |
| | | |
| === NVGPU_AS_IOCTL_MAP_BUFFER === | | === NVGPU_AS_IOCTL_MAP_BUFFER === |
− | Maps a memory region in the device address space. Identical to Linux driver pretty much. | + | Maps a memory region in the device address space. |
| + | |
| + | Unaligned size will cause a [[#Panic]]. |
| | | |
| On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute. | | On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute. |
Line 1,048: |
Line 1,068: |
| struct { | | struct { |
| __in u32 flags; // bit0: fixed_offset, bit2: cacheable | | __in u32 flags; // bit0: fixed_offset, bit2: cacheable |
− | u32 reserved; | + | u32 reserved0; |
− | __in u32 dmabuf_fd; // nvmap handle | + | __in u32 mem_id; // nvmap handle |
− | __inout u32 page_size; // 0 means don't care | + | u32 reserved1; |
| union { | | union { |
| __out u64 offset; | | __out u64 offset; |
Line 1,066: |
Line 1,086: |
| struct { | | struct { |
| __in u32 flags; // bit0: fixed_offset, bit2: cacheable | | __in u32 flags; // bit0: fixed_offset, bit2: cacheable |
− | __in u32 kind; // -1 is default | + | __inout u32 kind; // -1 is default |
− | __in u32 dmabuf_fd; // nvmap handle | + | __in u32 mem_id; // nvmap handle |
− | __inout u32 page_size; // 0 means don't care | + | u32 reserved; |
| __in u64 buffer_offset; | | __in u64 buffer_offset; |
| __in u64 mapping_size; | | __in u64 mapping_size; |
− | __inout u64 offset; | + | union { |
| + | __out u64 offset; |
| + | __in u64 align; |
| + | }; |
| }; | | }; |
| | | |
Line 1,092: |
Line 1,115: |
| === NVGPU_AS_IOCTL_GET_VA_REGIONS === | | === NVGPU_AS_IOCTL_GET_VA_REGIONS === |
| Nintendo's custom implementation to get rid of pointer in struct. | | Nintendo's custom implementation to get rid of pointer in struct. |
| + | |
| + | Uses [[#Ioctl3|Ioctl3]]. |
| | | |
| struct va_region { | | struct va_region { |
Line 1,120: |
Line 1,145: |
| }; | | }; |
| | | |
− | === NVGPU_AS_IOCTL_MODIFY === | + | === NVGPU_AS_IOCTL_MAP_BUFFER_EX2 === |
− | Modifies a memory region in the device address space.
| + | Maps a memory region in the device address space with extra params. |
| | | |
− | struct {
| + | Unaligned size will cause a [[#Panic]]. |
| + | |
| + | On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute. |
| + | |
| + | struct { |
| __in u32 flags; // bit0: fixed_offset, bit2: cacheable | | __in u32 flags; // bit0: fixed_offset, bit2: cacheable |
− | __in u32 kind; // -1 is default | + | __inout u32 kind; // -1 is default |
− | __in u32 dmabuf_fd; // nvmap handle | + | __in u32 mem_id; // nvmap handle |
− | __inout u32 page_size; // 0 means don't care | + | u32 reserved0; |
| __in u64 buffer_offset; | | __in u64 buffer_offset; |
| __in u64 mapping_size; | | __in u64 mapping_size; |
− | __inout u64 offset; | + | union { |
− | __in u64 unk0; | + | __out u64 offset; |
− | __in u32 unk1; | + | __in u64 align; |
− | u32 reserved; | + | }; |
| + | __in u64 vma_addr; |
| + | __in u32 pages; |
| + | u32 reserved1; |
| }; | | }; |
| | | |
Line 1,140: |
Line 1,172: |
| | | |
| struct remap_op { | | struct remap_op { |
− | __in u16 flags; // bit2: cacheable | + | __in u16 flags; // bit2: cacheable |
| __in u16 kind; | | __in u16 kind; |
| __in u32 mem_handle; | | __in u32 mem_handle; |
− | __in u32 mem_offset_in_big_pages; | + | __in u32 mem_offset_in_pages; |
− | __in u32 virt_offset_in_big_pages; // (alloc_space_offset >> 0x10) | + | __in u32 virt_offset_in_pages; // (alloc_space_offset >> 0x10) |
− | __in u32 num_pages; // alloc_space_pages | + | __in u32 num_pages; // alloc_space_pages |
| }; | | }; |
| | | |
Line 1,210: |
Line 1,242: |
| | 0xC018441A || Inout || 24 || NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA | | | 0xC018441A || Inout || 24 || NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA |
| |- | | |- |
− | | 0xC020441B || Inout || 32 || [11.0.0+] | + | | 0xC020441B || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA_EX |
| |- | | |- |
− | | 0xC084441C || Inout || 132 || [11.0.0+] | + | | 0xC084441C || Inout || 132 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SETTINGS |
| |- | | |- |
− | | 0xC018441D || Inout || 24 || [11.0.0+] | + | | 0xC018441D || Inout || 24 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SERIAL_NUMBER |
| |- | | |- |
− | | 0xC020441E || Inout || 32 || [11.0.0+] | + | | 0xC020441E || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PAGES |
| |} | | |} |
| | | |
Line 1,579: |
Line 1,611: |
| |- | | |- |
| | /dev/nvhost-display || Display | | | /dev/nvhost-display || Display |
| + | |- |
| + | | /dev/nvhost-tsec || TSEC |
| |} | | |} |
| | | |
Line 1,689: |
Line 1,723: |
| u32 syncpt_id; | | u32 syncpt_id; |
| u32 syncpt_incrs; | | u32 syncpt_incrs; |
− | };
| + | u32 reserved[3]; |
− |
| |
− | struct fence {
| |
− | u32 id; | |
− | u32 thresh;
| |
| }; | | }; |
| | | |
Line 1,705: |
Line 1,735: |
| __in struct reloc_shift reloc_shifts[]; // depends on num_relocs | | __in struct reloc_shift reloc_shifts[]; // depends on num_relocs |
| __in struct syncpt_incr syncpt_incrs[]; // depends on num_syncpt_incrs | | __in struct syncpt_incr syncpt_incrs[]; // depends on num_syncpt_incrs |
− | __out struct fence fences[]; // depends on num_fences | + | __out u32 fence_thresholds[]; // depends on num_fences |
| }; | | }; |
| | | |
Line 1,818: |
Line 1,848: |
| struct { | | struct { |
| __in u32 num_entries; | | __in u32 num_entries; |
− | __in u32 flags; | + | __in u32 flags; // bit0: vpr_enabled |
| }; | | }; |
| | | |
Line 1,845: |
Line 1,875: |
| struct fence { | | struct fence { |
| u32 id; | | u32 id; |
− | u32 thresh; | + | u32 value; |
| }; | | }; |
| | | |
| struct gpfifo_entry { | | struct gpfifo_entry { |
− | u64 entry; // gpu_iova | (unk_2bits << 40) | (size << 42) | (unk_flag << 63) | + | u32 entry0; // gpu_iova_lo |
| + | u32 entry1; // gpu_iova_hi | (allow_flush << 8) | (is_push_buf << 9) | (size << 10) | (sync << 31) |
| }; | | }; |
| | | |
Line 1,855: |
Line 1,886: |
| __in u64 gpfifo; // (ignored) pointer to gpfifo fence structs | | __in u64 gpfifo; // (ignored) pointer to gpfifo fence structs |
| __in u32 num_entries; // number of fence objects being submitted | | __in u32 num_entries; // number of fence objects being submitted |
− | __in u32 flags; | + | union { |
| + | __out u32 detailed_error; |
| + | __in u32 flags; // bit0: fence_wait, bit1: fence_get, bit2: hw_format, bit3: sync_fence, bit4: suppress_wfi, bit5: skip_buffer_refcounting |
| + | }; |
| __inout struct fence fence_out; // returned new fence object for others to wait on | | __inout struct fence fence_out; // returned new fence object for others to wait on |
| __in struct gpfifo_entry entries[]; // depends on num_entries | | __in struct gpfifo_entry entries[]; // depends on num_entries |
Line 1,938: |
Line 1,972: |
| | | |
| struct { | | struct { |
− | __out u32 error_info[32]; // first word is an error code (0=no_error, 1=gr_error, 2=gr_error, 3=invalid, 4=invalid) | + | __out u32 error_info[32]; // first word is an error code (0=no_error, 1=mmu_error, 2=gr_error, 3=pbdma_error, 4=timeout) |
| }; | | }; |
| | | |
Line 1,956: |
Line 1,990: |
| struct fence { | | struct fence { |
| u32 id; | | u32 id; |
− | u32 thresh; | + | u32 value; |
| }; | | }; |
| | | |
Line 1,962: |
Line 1,996: |
| __in u32 num_entries; | | __in u32 num_entries; |
| __in u32 num_jobs; | | __in u32 num_jobs; |
− | __in u32 flags; | + | __in u32 flags; // bit0: vpr_enabled |
| __out struct fence fence_out; // returned new fence object for others to wait on | | __out struct fence fence_out; // returned new fence object for others to wait on |
| __in u32 reserved[3]; // ignored | | __in u32 reserved[3]; // ignored |
Line 2,062: |
Line 2,096: |
| | 13 | | | 13 |
| | | | | |
− | | | + | | Can use the GPU virtual address range 0xC0000 to 0x580000 instead of 0x0 to 0xC0000. |
| |- | | |- |
| | 14 | | | 14 |
Line 2,070: |
Line 2,104: |
| | 15 | | | 15 |
| | | | | |
− | | | + | | Can use the virtual address ranges 0x0 to 0x100000000 (GPU) and 0x0 to 0xE0000000 (non-GPU) instead of 0x100000000 to 0x11FA50000 (GPU) and 0xE0000000 to 0xFFFE0000 (non-GPU). |
| |} | | |} |
| | | |
Line 2,225: |
Line 2,259: |
| | | |
| When the gpfifo data in the gpu_va buffers specified by the submitted gpfifo entries is invalid(?), eventually the user-process will be force-terminated after using the submit-gpfifo ioctl. It's unknown how exactly this is done. | | When the gpfifo data in the gpu_va buffers specified by the submitted gpfifo entries is invalid(?), eventually the user-process will be force-terminated after using the submit-gpfifo ioctl. It's unknown how exactly this is done. |
| + | |
| + | GPU rendering (GPFIFO) is only used by applets/Applications. All sysmodules doing any gfx-display uses software rendering. During system-boot, GPU GPFIFO is not used until the applets are launched. |
| | | |
| [[Category:Services]] | | [[Category:Services]] |