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no edit summary
This is the 0x200-byte TLS (thread local storage). It's base address is loaded via ARM threadid register tpidrro_el0. TLS for multiple threads are stored in the same page, with the first TLS normally(?) located at page+0x200.
This is the 0x200-byte TLS (thread local storage). It's base address is loaded via ARM threadid register tpidrro_el0. TLS for multiple threads are stored in the same page, with the first TLS normally located at page+0x200, because the first TLS spot is reserved for usermode exception handling.
= Structure =
= Structure =
| [[IPC_Marshalling|IPC]] command buffer.
| [[IPC_Marshalling|IPC]] command buffer.
|-
|-
| 0x100
| [8.0.0+] 0x100
| 0xF8
| 0x4
| Preemption State
|-
| 0x104
| 0xF4
| Unknown.
| Unknown.
|-
|-
| 0x08
| 0x08
| 0x08
| 0x08
| Unknown.
| Pointer to [[Thread_Local_Storage#Thread_context|thread context]]
|-
|-
| 0x10
| 0x10
| 0x60
| 0x60
| 0x08
| 0x08
| Unknown.
| Thread stub pointer.
|-
|-
| 0x68
| 0x68
| 0x08
| 0x08
| Unknown.
| Thread ID.
|-
|-
| 0x70
| 0x70
| 0x88
| 0x88
| 0x100
| 0x100
| Initially empty (contains unknown pointers).
| TLS slots.
|-
|-
| 0x188
| 0x188
| 0x1B0
| 0x1B0
| 0x04
| 0x04
| Always 0.
| Critical Section.
|-
|-
| 0x1B4
| 0x1B4
| 0x04
| 0x04
| Always 0.
| Conditional Variable.
|-
|-
| 0x1B8
| 0x1B8