2,781
edits
Changes
Jump to navigation
Jump to search
Line 551:
Line 551: − + Line 819:
Line 819: − + Line 831:
Line 831: − + − + − + Line 2,307:
Line 2,307: − + Line 2,932:
Line 2,932: − + Line 2,946:
Line 2,946: − + Line 2,952:
Line 2,952: − + − + − + − + − + − + − + − + − Controls VPR request mode (which bypasses MMU). Accessible in HS mode only.+ − + Line 2,986:
Line 2,986: − + + + + − + + + + − + + + + − + + + + − + + + + − + + + + − + + + + − + + + + − Controls the aperture ID of memory requests. Accessible in HS mode only.+
no edit summary
| 0x04
| 0x04
|-
|-
| [[#FALCON_SCTL_STAT|FALCON_SCTL_STAT]]
| [[#FALCON_SSTAT|FALCON_SSTAT]]
| 0x54501244
| 0x54501244
| 0x04
| 0x04
| 0x04
| 0x04
|-
|-
| TSEC_TFBIF_TRANSCFG
| TSEC_TFBIF_UNK_30
| 0x54501630
| 0x54501630
| 0x04
| 0x04
| 0x04
| 0x04
|-
|-
| [[#TSEC_TFBIF_SPROT_REGION|TSEC_TFBIF_SPROT_REGION]]
| [[#TSEC_TFBIF_SPROT_EMEM|TSEC_TFBIF_SPROT_EMEM]]
| 0x54501640
| 0x54501640
| 0x04
| 0x04
|-
|-
| [[#TSEC_TFBIF_REGIONCFG|TSEC_TFBIF_REGIONCFG]]
| [[#TSEC_TFBIF_TRANSCFG|TSEC_TFBIF_TRANSCFG]]
| 0x54501644
| 0x54501644
| 0x04
| 0x04
|-
|-
| [[#TSEC_TFBIF_REGIONCFG1|TSEC_TFBIF_REGIONCFG1]]
| [[#TSEC_TFBIF_REGIONCFG|TSEC_TFBIF_REGIONCFG]]
| 0x54501648
| 0x54501648
| 0x04
| 0x04
|}
|}
=== FALCON_SCTL_STAT ===
=== FALCON_SSTAT ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Bits
|}
|}
=== TSEC_TFBIF_SPROT_REGION ===
=== TSEC_TFBIF_SPROT_EMEM ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Bits
Controls accesses to external memory regions. Accessible in HS mode only.
Controls accesses to external memory regions. Accessible in HS mode only.
=== TSEC_TFBIF_REGIONCFG ===
=== TSEC_TFBIF_TRANSCFG ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Bits
|-
|-
| 0
| 0
| TSEC_TFBIF_REGIONCFG_T0_VPR
| TSEC_TFBIF_TRANSCFG_ATT0_SWID
|-
|-
| 4
| 4
| TSEC_TFBIF_REGIONCFG_T1_VPR
| TSEC_TFBIF_TRANSCFG_ATT1_SWID
|-
|-
| 8
| 8
| TSEC_TFBIF_REGIONCFG_T2_VPR
| TSEC_TFBIF_TRANSCFG_ATT2_SWID
|-
|-
| 12
| 12
| TSEC_TFBIF_REGIONCFG_T3_VPR
| TSEC_TFBIF_TRANSCFG_ATT3_SWID
|-
|-
| 16
| 16
| TSEC_TFBIF_REGIONCFG_T4_VPR
| TSEC_TFBIF_TRANSCFG_ATT4_SWID
|-
|-
| 20
| 20
| TSEC_TFBIF_REGIONCFG_T5_VPR
| TSEC_TFBIF_TRANSCFG_ATT5_SWID
|-
|-
| 24
| 24
| TSEC_TFBIF_REGIONCFG_T6_VPR
| TSEC_TFBIF_TRANSCFG_ATT6_SWID
|-
|-
| 28
| 28
| TSEC_TFBIF_REGIONCFG_T7_VPR
| TSEC_TFBIF_TRANSCFG_ATT7_SWID
|}
|}
Configures the software ID per CTXDMA port for memory transactions. Software ID 0 (HW_SWID) forces all transactions to go through the SMMU while software ID 1 (PHY_SWID) bypasses it. Accessible in HS mode only.
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
=== TSEC_TFBIF_REGIONCFG1 ===
=== TSEC_TFBIF_REGIONCFG ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Bits
|-
|-
| 0-2
| 0-2
| TSEC_TFBIF_REGIONCFG1_T0_APERT_ID
| TSEC_TFBIF_REGIONCFG_T0_APERT_ID
|-
| 3
| TSEC_TFBIF_REGIONCFG_T0_VPR
|-
|-
| 4-6
| 4-6
| TSEC_TFBIF_REGIONCFG1_T1_APERT_ID
| TSEC_TFBIF_REGIONCFG_T1_APERT_ID
|-
| 7
| TSEC_TFBIF_REGIONCFG_T1_VPR
|-
|-
| 8-10
| 8-10
| TSEC_TFBIF_REGIONCFG1_T2_APERT_ID
| TSEC_TFBIF_REGIONCFG_T2_APERT_ID
|-
| 11
| TSEC_TFBIF_REGIONCFG_T2_VPR
|-
|-
| 12-14
| 12-14
| TSEC_TFBIF_REGIONCFG1_T3_APERT_ID
| TSEC_TFBIF_REGIONCFG_T3_APERT_ID
|-
| 15
| TSEC_TFBIF_REGIONCFG_T3_VPR
|-
|-
| 16-18
| 16-18
| TSEC_TFBIF_REGIONCFG1_T4_APERT_ID
| TSEC_TFBIF_REGIONCFG_T4_APERT_ID
|-
| 17
| TSEC_TFBIF_REGIONCFG_T4_VPR
|-
|-
| 20-22
| 20-22
| TSEC_TFBIF_REGIONCFG1_T5_APERT_ID
| TSEC_TFBIF_REGIONCFG_T5_APERT_ID
|-
| 23
| TSEC_TFBIF_REGIONCFG_T5_VPR
|-
|-
| 24-26
| 24-26
| TSEC_TFBIF_REGIONCFG1_T6_APERT_ID
| TSEC_TFBIF_REGIONCFG_T6_APERT_ID
|-
| 27
| TSEC_TFBIF_REGIONCFG_T6_VPR
|-
|-
| 28-30
| 28-30
| TSEC_TFBIF_REGIONCFG1_T7_APERT_ID
| TSEC_TFBIF_REGIONCFG_T7_APERT_ID
|-
| 31
| TSEC_TFBIF_REGIONCFG_T7_VPR
|}
|}
Configures the aperture ID and VPR mode per CTXDMA port for memory region accessing. Accessible in HS mode only.
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.