Difference between revisions of "TSEC"

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== Registers ==
 
== Registers ==
Registers from 0x54500000 to 0x54501000 are used to configure the host interface (HOST1X).
+
The TSEC's MMIO space is divided as follows:
 
+
* 0x54500000 to 0x54501000: THI (Tegra Host Interface)
Registers from 0x54501000 to 0x54502000 are a MMIO window for communicating with the Falcon microprocessor. From this range, the subset of registers from 0x54501400 to 0x54501FE8 are specific to the TSEC and are subdivided into:
+
* 0x54501000 to 0x54501400: [[#Falcon|FALCON (Falcon microcontroller)]]
* 0x54501400 to 0x54501500: SCP (Secure Co-Processor).
+
* 0x54501400 to 0x54501600: [[#SCP|SCP (Secure coprocessor)]]
* 0x54501500 to 0x54501600: TRNG (True Random Number Generator).
+
* 0x54501600 to 0x54501680: TFBIF (Tegra Framebuffer Interface)
* 0x54501600 to 0x54501700: TFBIF (Tegra Framebuffer Interface) and CG (Clock Gate).
+
* 0x54501680 to 0x54501700: CG (Clock Gate)
* 0x54501700 to 0x54501800: BAR0.
+
* 0x54501700 to 0x54501800: BAR0 (HOST1X device DMA)
* 0x54501800 to 0x54501900: TEGRA (miscellaneous interfaces).
+
* 0x54501800 to 0x54501900: TEGRA (Miscellaneous interfaces)
  
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
Line 19: Line 19:
 
!  Width
 
!  Width
 
|-
 
|-
| TSEC_THI_INCR_SYNCPT
+
| [[#TSEC_THI_INCR_SYNCPT|TSEC_THI_INCR_SYNCPT]]
 
| 0x54500000
 
| 0x54500000
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_INCR_SYNCPT_ERR
+
| [[#TSEC_THI_INCR_SYNCPT_CTRL|TSEC_THI_INCR_SYNCPT_CTRL]]
 +
| 0x54500004
 +
| 0x04
 +
|-
 +
| [[#TSEC_THI_INCR_SYNCPT_ERR|TSEC_THI_INCR_SYNCPT_ERR]]
 
| 0x54500008
 
| 0x54500008
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_CTXSW_INCR_SYNCPT
+
| [[#TSEC_THI_CTXSW_INCR_SYNCPT|TSEC_THI_CTXSW_INCR_SYNCPT]]
 
| 0x5450000C
 
| 0x5450000C
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_CTXSW
+
| [[#TSEC_THI_CTXSW|TSEC_THI_CTXSW]]
 
| 0x54500020
 
| 0x54500020
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_CONT_SYNCPT_EOF
+
| [[#TSEC_THI_CTXSW_NEXT|TSEC_THI_CTXSW_NEXT]]
 +
| 0x54500024
 +
| 0x04
 +
|-
 +
| [[#TSEC_THI_CONT_SYNCPT_EOF|TSEC_THI_CONT_SYNCPT_EOF]]
 
| 0x54500028
 
| 0x54500028
 +
| 0x04
 +
|-
 +
| [[#TSEC_THI_CONT_SYNCPT_L1|TSEC_THI_CONT_SYNCPT_L1]]
 +
| 0x5450002C
 +
| 0x04
 +
|-
 +
| [[#TSEC_THI_STREAMID0|TSEC_THI_STREAMID0]]
 +
| 0x54500030
 +
| 0x04
 +
|-
 +
| [[#TSEC_THI_STREAMID1|TSEC_THI_STREAMID1]]
 +
| 0x54500034
 +
| 0x04
 +
|-
 +
| [[#TSEC_THI_THI_SEC|TSEC_THI_THI_SEC]]
 +
| 0x54500038
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 45: Line 69:
 
| [[#TSEC_THI_METHOD1|TSEC_THI_METHOD1]]
 
| [[#TSEC_THI_METHOD1|TSEC_THI_METHOD1]]
 
| 0x54500044
 
| 0x54500044
 +
| 0x04
 +
|-
 +
| [[#TSEC_THI_CONTEXT_SWITCH|TSEC_THI_CONTEXT_SWITCH]]
 +
| 0x54500060
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 55: Line 83:
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_INT_CLEAR
+
| [[#TSEC_THI_CONFIG0|TSEC_THI_CONFIG0]]
 
| 0x54500080
 
| 0x54500080
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_INT_ENABLE
+
| [[#TSEC_THI_DBG_MISC|TSEC_THI_DBG_MISC]]
 
| 0x54500084
 
| 0x54500084
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_SLCG_OVERRIDE_HIGH_A
+
| [[#TSEC_THI_SLCG_OVERRIDE_HIGH_A|TSEC_THI_SLCG_OVERRIDE_HIGH_A]]
 
| 0x54500088
 
| 0x54500088
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_SLCG_OVERRIDE_LOW_A
+
| [[#TSEC_THI_SLCG_OVERRIDE_LOW_A|TSEC_THI_SLCG_OVERRIDE_LOW_A]]
 
| 0x5450008C
 
| 0x5450008C
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_THI_CLK_OVERRIDE
+
| [[#TSEC_THI_CLK_OVERRIDE|TSEC_THI_CLK_OVERRIDE]]
 
| 0x54500E00
 
| 0x54500E00
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_IRQSSET|FALCON_IRQSSET]]
+
| [[#TSEC_FALCON_IRQSSET|TSEC_FALCON_IRQSSET]]
 
| 0x54501000
 
| 0x54501000
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_IRQSCLR|FALCON_IRQSCLR]]
+
| [[#TSEC_FALCON_IRQSCLR|TSEC_FALCON_IRQSCLR]]
 
| 0x54501004
 
| 0x54501004
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_IRQSTAT|FALCON_IRQSTAT]]
+
| [[#TSEC_FALCON_IRQSTAT|TSEC_FALCON_IRQSTAT]]
 
| 0x54501008
 
| 0x54501008
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_IRQMODE|FALCON_IRQMODE]]
+
| [[#TSEC_FALCON_IRQMODE|TSEC_FALCON_IRQMODE]]
 
| 0x5450100C
 
| 0x5450100C
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_IRQMSET|FALCON_IRQMSET]]
+
| [[#TSEC_FALCON_IRQMSET|TSEC_FALCON_IRQMSET]]
 
| 0x54501010
 
| 0x54501010
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_IRQMCLR|FALCON_IRQMCLR]]
+
| [[#TSEC_FALCON_IRQMCLR|TSEC_FALCON_IRQMCLR]]
 
| 0x54501014
 
| 0x54501014
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_IRQMASK|FALCON_IRQMASK]]
+
| [[#TSEC_FALCON_IRQMASK|TSEC_FALCON_IRQMASK]]
 
| 0x54501018
 
| 0x54501018
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_IRQDEST|FALCON_IRQDEST]]
+
| [[#TSEC_FALCON_IRQDEST|TSEC_FALCON_IRQDEST]]
 
| 0x5450101C
 
| 0x5450101C
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_GPTMRINT
+
| [[#TSEC_FALCON_GPTMRINT|TSEC_FALCON_GPTMRINT]]
 
| 0x54501020
 
| 0x54501020
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_GPTMRVAL
+
| [[#TSEC_FALCON_GPTMRVAL|TSEC_FALCON_GPTMRVAL]]
 
| 0x54501024
 
| 0x54501024
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_GPTMRCTL
+
| [[#TSEC_FALCON_GPTMRCTL|TSEC_FALCON_GPTMRCTL]]
 
| 0x54501028
 
| 0x54501028
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_PTIMER0
+
| [[#TSEC_FALCON_PTIMER0|TSEC_FALCON_PTIMER0]]
 
| 0x5450102C
 
| 0x5450102C
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_PTIMER1
+
| [[#TSEC_FALCON_PTIMER1|TSEC_FALCON_PTIMER1]]
 
| 0x54501030
 
| 0x54501030
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_WDTMRVAL
+
| [[#TSEC_FALCON_WDTMRVAL|TSEC_FALCON_WDTMRVAL]]
 
| 0x54501034
 
| 0x54501034
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_WDTMRCTL
+
| [[#TSEC_FALCON_WDTMRCTL|TSEC_FALCON_WDTMRCTL]]
 
| 0x54501038
 
| 0x54501038
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_UNK_3C
+
| [[#TSEC_FALCON_IRQDEST2|TSEC_FALCON_IRQDEST2]]
 
| 0x5450103C
 
| 0x5450103C
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_MAILBOX0|FALCON_MAILBOX0]]
+
| [[#TSEC_FALCON_MAILBOX0|TSEC_FALCON_MAILBOX0]]
 
| 0x54501040
 
| 0x54501040
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_MAILBOX1|FALCON_MAILBOX1]]
+
| [[#TSEC_FALCON_MAILBOX1|TSEC_FALCON_MAILBOX1]]
 
| 0x54501044
 
| 0x54501044
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_ITFEN|FALCON_ITFEN]]
+
| [[#TSEC_FALCON_ITFEN|TSEC_FALCON_ITFEN]]
 
| 0x54501048
 
| 0x54501048
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_IDLESTATE|FALCON_IDLESTATE]]
+
| [[#TSEC_FALCON_IDLESTATE|TSEC_FALCON_IDLESTATE]]
 
| 0x5450104C
 
| 0x5450104C
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_CURCTX
+
| [[#TSEC_FALCON_CURCTX|TSEC_FALCON_CURCTX]]
 
| 0x54501050
 
| 0x54501050
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_NXTCTX
+
| [[#TSEC_FALCON_NXTCTX|TSEC_FALCON_NXTCTX]]
 
| 0x54501054
 
| 0x54501054
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_CTXACK
+
| [[#TSEC_FALCON_CTXACK|TSEC_FALCON_CTXACK]]
 
| 0x54501058
 
| 0x54501058
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_FHSTATE
+
| [[#TSEC_FALCON_FHSTATE|TSEC_FALCON_FHSTATE]]
 
| 0x5450105C
 
| 0x5450105C
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_PRIVSTATE
+
| [[#TSEC_FALCON_PRIVSTATE|TSEC_FALCON_PRIVSTATE]]
 
| 0x54501060
 
| 0x54501060
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_MTHDDATA
+
| [[#TSEC_FALCON_MTHDDATA|TSEC_FALCON_MTHDDATA]]
 
| 0x54501064
 
| 0x54501064
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_MTHDID
+
| [[#TSEC_FALCON_MTHDID|TSEC_FALCON_MTHDID]]
 
| 0x54501068
 
| 0x54501068
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_MTHDWDAT
+
| [[#TSEC_FALCON_MTHDWDAT|TSEC_FALCON_MTHDWDAT]]
 
| 0x5450106C
 
| 0x5450106C
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_MTHDCOUNT
+
| [[#TSEC_FALCON_MTHDCOUNT|TSEC_FALCON_MTHDCOUNT]]
 
| 0x54501070
 
| 0x54501070
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_MTHDPOP
+
| [[#TSEC_FALCON_MTHDPOP|TSEC_FALCON_MTHDPOP]]
 
| 0x54501074
 
| 0x54501074
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_MTHDRAMSZ
+
| [[#TSEC_FALCON_MTHDRAMSZ|TSEC_FALCON_MTHDRAMSZ]]
 
| 0x54501078
 
| 0x54501078
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_SFTRESET
+
| [[#TSEC_FALCON_SFTRESET|TSEC_FALCON_SFTRESET]]
 
| 0x5450107C
 
| 0x5450107C
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_OS
+
| [[#TSEC_FALCON_OS|TSEC_FALCON_OS]]
 
| 0x54501080
 
| 0x54501080
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_RM
+
| [[#TSEC_FALCON_RM|TSEC_FALCON_RM]]
 
| 0x54501084
 
| 0x54501084
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_SOFT_PM
+
| [[#TSEC_FALCON_SOFT_PM|TSEC_FALCON_SOFT_PM]]
 
| 0x54501088
 
| 0x54501088
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_SOFT_MODE
+
| [[#TSEC_FALCON_SOFT_MODE|TSEC_FALCON_SOFT_MODE]]
 
| 0x5450108C
 
| 0x5450108C
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_DEBUG1|FALCON_DEBUG1]]
+
| [[#TSEC_FALCON_DEBUG1|TSEC_FALCON_DEBUG1]]
 
| 0x54501090
 
| 0x54501090
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_DEBUGINFO|FALCON_DEBUGINFO]]
+
| [[#TSEC_FALCON_DEBUGINFO|TSEC_FALCON_DEBUGINFO]]
 
| 0x54501094
 
| 0x54501094
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_IBRKPT1
+
| [[#TSEC_FALCON_IBRKPT1|TSEC_FALCON_IBRKPT1]]
 
| 0x54501098
 
| 0x54501098
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_IBRKPT2
+
| [[#TSEC_FALCON_IBRKPT2|TSEC_FALCON_IBRKPT2]]
 
| 0x5450109C
 
| 0x5450109C
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_CGCTL
+
| [[#TSEC_FALCON_CGCTL|TSEC_FALCON_CGCTL]]
 
| 0x545010A0
 
| 0x545010A0
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_ENGCTL
+
| [[#TSEC_FALCON_ENGCTL|TSEC_FALCON_ENGCTL]]
 
| 0x545010A4
 
| 0x545010A4
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_PMM
+
| [[#TSEC_FALCON_PMM|TSEC_FALCON_PMM]]
 
| 0x545010A8
 
| 0x545010A8
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_ADDR
+
| [[#TSEC_FALCON_ADDR|TSEC_FALCON_ADDR]]
 
| 0x545010AC
 
| 0x545010AC
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_IBRKPT3
+
| [[#TSEC_FALCON_IBRKPT3|TSEC_FALCON_IBRKPT3]]
 
| 0x545010B0
 
| 0x545010B0
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_IBRKPT4
+
| [[#TSEC_FALCON_IBRKPT4|TSEC_FALCON_IBRKPT4]]
 
| 0x545010B4
 
| 0x545010B4
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_IBRKPT5
+
| [[#TSEC_FALCON_IBRKPT5|TSEC_FALCON_IBRKPT5]]
 
| 0x545010B8
 
| 0x545010B8
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_EXCI|FALCON_EXCI]]
+
| [[#TSEC_FALCON_EXCI|TSEC_FALCON_EXCI]]
 
| 0x545010D0
 
| 0x545010D0
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_UNK_D4
+
| [[#TSEC_FALCON_SVEC_SPR|TSEC_FALCON_SVEC_SPR]]
 
| 0x545010D4
 
| 0x545010D4
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_UNK_D8
+
| [[#TSEC_FALCON_RSTAT0|TSEC_FALCON_RSTAT0]]
 
| 0x545010D8
 
| 0x545010D8
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_UNK_DC
+
| [[#TSEC_FALCON_RSTAT3|TSEC_FALCON_RSTAT3]]
 
| 0x545010DC
 
| 0x545010DC
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_UNK_E0
+
| TSEC_FALCON_UNK_E0
 
| 0x545010E0
 
| 0x545010E0
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_CPUCTL|FALCON_CPUCTL]]
+
| [[#TSEC_FALCON_CPUCTL|TSEC_FALCON_CPUCTL]]
 
| 0x54501100
 
| 0x54501100
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_BOOTVEC|FALCON_BOOTVEC]]
+
| [[#TSEC_FALCON_BOOTVEC|TSEC_FALCON_BOOTVEC]]
 
| 0x54501104
 
| 0x54501104
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_HWCFG|FALCON_HWCFG]]
+
| [[#TSEC_FALCON_HWCFG|TSEC_FALCON_HWCFG]]
 
| 0x54501108
 
| 0x54501108
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_DMACTL|FALCON_DMACTL]]
+
| [[#TSEC_FALCON_DMACTL|TSEC_FALCON_DMACTL]]
 
| 0x5450110C
 
| 0x5450110C
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_DMATRFBASE|FALCON_DMATRFBASE]]
+
| [[#TSEC_FALCON_DMATRFBASE|TSEC_FALCON_DMATRFBASE]]
 
| 0x54501110
 
| 0x54501110
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_DMATRFMOFFS|FALCON_DMATRFMOFFS]]
+
| [[#TSEC_FALCON_DMATRFMOFFS|TSEC_FALCON_DMATRFMOFFS]]
 
| 0x54501114
 
| 0x54501114
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_DMATRFCMD|FALCON_DMATRFCMD]]
+
| [[#TSEC_FALCON_DMATRFCMD|TSEC_FALCON_DMATRFCMD]]
 
| 0x54501118
 
| 0x54501118
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_DMATRFFBOFFS|FALCON_DMATRFFBOFFS]]
+
| [[#TSEC_FALCON_DMATRFFBOFFS|TSEC_FALCON_DMATRFFBOFFS]]
 
| 0x5450111C
 
| 0x5450111C
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_DMAPOLL_FB|FALCON_DMAPOLL_FB]]
+
| [[#TSEC_FALCON_DMAPOLL_FB|TSEC_FALCON_DMAPOLL_FB]]
 
| 0x54501120
 
| 0x54501120
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_DMAPOLL_CP|FALCON_DMAPOLL_CP]]
+
| [[#TSEC_FALCON_DMAPOLL_CP|TSEC_FALCON_DMAPOLL_CP]]
 
| 0x54501124
 
| 0x54501124
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_CPUSTAT
+
| [[#TSEC_FALCON_HWCFG1|TSEC_FALCON_HWCFG1]]
| 0x54501128
+
| 0x5450112C
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_HWCFG1|FALCON_HWCFG1]]
+
| [[#TSEC_FALCON_CPUCTL_ALIAS|TSEC_FALCON_CPUCTL_ALIAS]]
| 0x5450112C
+
| 0x54501130
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_CPUCTL_ALIAS
+
| [[#TSEC_FALCON_STACKCFG|TSEC_FALCON_STACKCFG]]
| 0x54501130
+
| 0x54501138
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_IMCTL|FALCON_IMCTL]]
+
| [[#TSEC_FALCON_IMCTL|TSEC_FALCON_IMCTL]]
 
| 0x54501140
 
| 0x54501140
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_IMSTAT|FALCON_IMSTAT]]
+
| [[#TSEC_FALCON_IMSTAT|TSEC_FALCON_IMSTAT]]
 
| 0x54501144
 
| 0x54501144
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_TRACEIDX|FALCON_TRACEIDX]]
+
| [[#TSEC_FALCON_TRACEIDX|TSEC_FALCON_TRACEIDX]]
 
| 0x54501148
 
| 0x54501148
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_TRACEPC|FALCON_TRACEPC]]
+
| [[#TSEC_FALCON_TRACEPC|TSEC_FALCON_TRACEPC]]
 
| 0x5450114C
 
| 0x5450114C
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_IMFILLRNG0
+
| [[#TSEC_FALCON_IMFILLRNG0|TSEC_FALCON_IMFILLRNG0]]
 
| 0x54501150
 
| 0x54501150
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_IMFILLRNG1
+
| [[#TSEC_FALCON_IMFILLRNG1|TSEC_FALCON_IMFILLRNG1]]
 
| 0x54501154
 
| 0x54501154
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_IMFILLCTL
+
| [[#TSEC_FALCON_IMFILLCTL|TSEC_FALCON_IMFILLCTL]]
 
| 0x54501158
 
| 0x54501158
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_IMCTL_DEBUG
+
| [[#TSEC_FALCON_IMCTL_DEBUG|TSEC_FALCON_IMCTL_DEBUG]]
 
| 0x5450115C
 
| 0x5450115C
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_CMEMBASE
+
| [[#TSEC_FALCON_CMEMBASE|TSEC_FALCON_CMEMBASE]]
 
| 0x54501160
 
| 0x54501160
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_DMEMAPERT
+
| [[#TSEC_FALCON_DMEMAPERT|TSEC_FALCON_DMEMAPERT]]
 
| 0x54501164
 
| 0x54501164
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_EXTERRADDR
+
| [[#TSEC_FALCON_EXTERRADDR|TSEC_FALCON_EXTERRADDR]]
 
| 0x54501168
 
| 0x54501168
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_EXTERRSTAT
+
| [[#TSEC_FALCON_EXTERRSTAT|TSEC_FALCON_EXTERRSTAT]]
 
| 0x5450116C
 
| 0x5450116C
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_CG1_SLCG
+
| [[#TSEC_FALCON_CG2|TSEC_FALCON_CG2]]
 
| 0x5450117C
 
| 0x5450117C
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_IMEMC|FALCON_IMEMC]]
+
| [[#TSEC_FALCON_IMEMC|TSEC_FALCON_IMEMC0]]
 
| 0x54501180
 
| 0x54501180
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_IMEMD|FALCON_IMEMD]]
+
| [[#TSEC_FALCON_IMEMD|TSEC_FALCON_IMEMD0]]
 
| 0x54501184
 
| 0x54501184
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_IMEMT|FALCON_IMEMT]]
+
| [[#TSEC_FALCON_IMEMT|TSEC_FALCON_IMEMT0]]
 
| 0x54501188
 
| 0x54501188
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_DMEMC0|FALCON_DMEMC0]]
+
| [[#TSEC_FALCON_IMEMC|TSEC_FALCON_IMEMC1]]
 +
| 0x54501190
 +
| 0x04
 +
|-
 +
| [[#TSEC_FALCON_IMEMD|TSEC_FALCON_IMEMD1]]
 +
| 0x54501194
 +
| 0x04
 +
|-
 +
| [[#TSEC_FALCON_IMEMT|TSEC_FALCON_IMEMT1]]
 +
| 0x54501198
 +
| 0x04
 +
|-
 +
| [[#TSEC_FALCON_IMEMC|TSEC_FALCON_IMEMC2]]
 +
| 0x545011A0
 +
| 0x04
 +
|-
 +
| [[#TSEC_FALCON_IMEMD|TSEC_FALCON_IMEMD2]]
 +
| 0x545011A4
 +
| 0x04
 +
|-
 +
| [[#TSEC_FALCON_IMEMT|TSEC_FALCON_IMEMT2]]
 +
| 0x545011A8
 +
| 0x04
 +
|-
 +
| [[#TSEC_FALCON_IMEMC|TSEC_FALCON_IMEMC3]]
 +
| 0x545011B0
 +
| 0x04
 +
|-
 +
| [[#TSEC_FALCON_IMEMD|TSEC_FALCON_IMEMD3]]
 +
| 0x545011B4
 +
| 0x04
 +
|-
 +
| [[#TSEC_FALCON_IMEMT|TSEC_FALCON_IMEMT3]]
 +
| 0x545011B8
 +
| 0x04
 +
|-
 +
| [[#TSEC_FALCON_DMEMC|TSEC_FALCON_DMEMC0]]
 
| 0x545011C0
 
| 0x545011C0
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_DMEMD0|FALCON_DMEMD0]]
+
| [[#TSEC_FALCON_DMEMD|TSEC_FALCON_DMEMD0]]
 
| 0x545011C4
 
| 0x545011C4
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_DMEMC1
+
| [[#TSEC_FALCON_DMEMC|TSEC_FALCON_DMEMC1]]
 
| 0x545011C8
 
| 0x545011C8
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_DMEMD1
+
| [[#TSEC_FALCON_DMEMD|TSEC_FALCON_DMEMD1]]
 
| 0x545011CC
 
| 0x545011CC
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_DMEMC2
+
| [[#TSEC_FALCON_DMEMC|TSEC_FALCON_DMEMC2]]
 
| 0x545011D0
 
| 0x545011D0
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_DMEMD2
+
| [[#TSEC_FALCON_DMEMD|TSEC_FALCON_DMEMD2]]
 
| 0x545011D4
 
| 0x545011D4
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_DMEMC3
+
| [[#TSEC_FALCON_DMEMC|TSEC_FALCON_DMEMC3]]
 
| 0x545011D8
 
| 0x545011D8
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_DMEMD3
+
| [[#TSEC_FALCON_DMEMD|TSEC_FALCON_DMEMD3]]
 
| 0x545011DC
 
| 0x545011DC
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_DMEMC4
+
| [[#TSEC_FALCON_DMEMC|TSEC_FALCON_DMEMC4]]
 
| 0x545011E0
 
| 0x545011E0
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_DMEMD4
+
| [[#TSEC_FALCON_DMEMD|TSEC_FALCON_DMEMD4]]
 
| 0x545011E4
 
| 0x545011E4
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_DMEMC5
+
| [[#TSEC_FALCON_DMEMC|TSEC_FALCON_DMEMC5]]
 
| 0x545011E8
 
| 0x545011E8
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_DMEMD5
+
| [[#TSEC_FALCON_DMEMD|TSEC_FALCON_DMEMD5]]
 
| 0x545011EC
 
| 0x545011EC
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_DMEMC6
+
| [[#TSEC_FALCON_DMEMC|TSEC_FALCON_DMEMC6]]
 
| 0x545011F0
 
| 0x545011F0
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_DMEMD6
+
| [[#TSEC_FALCON_DMEMD|TSEC_FALCON_DMEMD6]]
 
| 0x545011F4
 
| 0x545011F4
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_DMEMC7
+
| [[#TSEC_FALCON_DMEMC|TSEC_FALCON_DMEMC7]]
 
| 0x545011F8
 
| 0x545011F8
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_DMEMD7
+
| [[#TSEC_FALCON_DMEMD|TSEC_FALCON_DMEMD7]]
 
| 0x545011FC
 
| 0x545011FC
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_ICD_CMD|FALCON_ICD_CMD]]
+
| [[#TSEC_FALCON_ICD_CMD|TSEC_FALCON_ICD_CMD]]
 
| 0x54501200
 
| 0x54501200
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_ICD_ADDR|FALCON_ICD_ADDR]]
+
| [[#TSEC_FALCON_ICD_ADDR|TSEC_FALCON_ICD_ADDR]]
 
| 0x54501204
 
| 0x54501204
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_ICD_WDATA|FALCON_ICD_WDATA]]
+
| [[#TSEC_FALCON_ICD_WDATA|TSEC_FALCON_ICD_WDATA]]
 
| 0x54501208
 
| 0x54501208
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_ICD_RDATA|FALCON_ICD_RDATA]]
+
| [[#TSEC_FALCON_ICD_RDATA|TSEC_FALCON_ICD_RDATA]]
 
| 0x5450120C
 
| 0x5450120C
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_SCTL|FALCON_SCTL]]
+
| [[#TSEC_FALCON_SCTL|TSEC_FALCON_SCTL]]
 
| 0x54501240
 
| 0x54501240
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_SCTL_STAT|FALCON_SCTL_STAT]]
+
| [[#TSEC_FALCON_SSTAT|TSEC_FALCON_SSTAT]]
 
| 0x54501244
 
| 0x54501244
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_UNK_248
+
| TSEC_FALCON_UNK_250
| 0x54501248
 
| 0x04
 
|-
 
| FALCON_UNK_24C
 
| 0x5450124C
 
| 0x04
 
|-
 
| FALCON_UNK_250
 
 
| 0x54501250
 
| 0x54501250
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_UNK_260
+
| TSEC_FALCON_UNK_260
 
| 0x54501260
 
| 0x54501260
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_SPROT_IMEM|FALCON_SPROT_IMEM]]
+
| [[#TSEC_FALCON_SPROT_IMEM|TSEC_FALCON_SPROT_IMEM]]
 
| 0x54501280
 
| 0x54501280
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_SPROT_DMEM|FALCON_SPROT_DMEM]]
+
| [[#TSEC_FALCON_SPROT_DMEM|TSEC_FALCON_SPROT_DMEM]]
 
| 0x54501284
 
| 0x54501284
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_SPROT_CPUCTL|FALCON_SPROT_CPUCTL]]
+
| [[#TSEC_FALCON_SPROT_CPUCTL|TSEC_FALCON_SPROT_CPUCTL]]
 
| 0x54501288
 
| 0x54501288
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_SPROT_MISC|FALCON_SPROT_MISC]]
+
| [[#TSEC_FALCON_SPROT_MISC|TSEC_FALCON_SPROT_MISC]]
 
| 0x5450128C
 
| 0x5450128C
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_SPROT_IRQ|FALCON_SPROT_IRQ]]
+
| [[#TSEC_FALCON_SPROT_IRQ|TSEC_FALCON_SPROT_IRQ]]
 
| 0x54501290
 
| 0x54501290
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_SPROT_MTHD|FALCON_SPROT_MTHD]]
+
| [[#TSEC_FALCON_SPROT_MTHD|TSEC_FALCON_SPROT_MTHD]]
 
| 0x54501294
 
| 0x54501294
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_SPROT_SCTL|FALCON_SPROT_SCTL]]
+
| [[#TSEC_FALCON_SPROT_SCTL|TSEC_FALCON_SPROT_SCTL]]
 
| 0x54501298
 
| 0x54501298
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#FALCON_SPROT_WDTMR|FALCON_SPROT_WDTMR]]
+
| [[#TSEC_FALCON_SPROT_WDTMR|TSEC_FALCON_SPROT_WDTMR]]
 
| 0x5450129C
 
| 0x5450129C
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_UNK_2C0
+
| [[#TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW|TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW]]
 
| 0x545012C0
 
| 0x545012C0
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_UNK_2C4
+
| [[#TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH|TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH]]
 
| 0x545012C4
 
| 0x545012C4
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_UNK_2C8
+
| [[#TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW|TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW]]
 
| 0x545012C8
 
| 0x545012C8
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_UNK_2CC
+
| [[#TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH|TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH]]
 
| 0x545012CC
 
| 0x545012CC
 
| 0x04
 
| 0x04
 
|-
 
|-
| FALCON_UNK_2E0
+
| [[#TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW|TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW]]
 +
| 0x545012D0
 +
| 0x04
 +
|-
 +
| [[#TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH|TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH]]
 +
| 0x545012D4
 +
| 0x04
 +
|-
 +
| [[#TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW|TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW]]
 +
| 0x545012D8
 +
| 0x04
 +
|-
 +
| [[#TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH|TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH]]
 +
| 0x545012DC
 +
| 0x04
 +
|-
 +
| [[#TSEC_FALCON_DMAINFO_CTL|TSEC_FALCON_DMAINFO_CTL]]
 
| 0x545012E0
 
| 0x545012E0
 
| 0x04
 
| 0x04
Line 571: Line 643:
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_SCP_UNK_10
+
| [[#TSEC_SCP_CFG|TSEC_SCP_CFG]]
 
| 0x54501410
 
| 0x54501410
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_SCP_UNK_14
+
| [[#TSEC_SCP_CTL_SCP|TSEC_SCP_CTL_SCP]]
 
| 0x54501414
 
| 0x54501414
 
| 0x04
 
| 0x04
Line 583: Line 655:
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_SCP_UNK_1C
+
| [[#TSEC_SCP_CTL_DBG|TSEC_SCP_CTL_DBG]]
 
| 0x5450141C
 
| 0x5450141C
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_SCP_SEQ_CTL|TSEC_SCP_SEQ_CTL]]
+
| [[#TSEC_SCP_DBG0|TSEC_SCP_DBG0]]
 
| 0x54501420
 
| 0x54501420
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_SCP_SEQ_VAL|TSEC_SCP_SEQ_VAL]]
+
| [[#TSEC_SCP_DBG1|TSEC_SCP_DBG1]]
 
| 0x54501424
 
| 0x54501424
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_SCP_SEQ_STAT|TSEC_SCP_SEQ_STAT]]
+
| [[#TSEC_SCP_DBG2|TSEC_SCP_DBG2]]
 
| 0x54501428
 
| 0x54501428
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_SCP_INSN_STAT|TSEC_SCP_INSN_STAT]]
+
| [[#TSEC_SCP_CMD|TSEC_SCP_CMD]]
 
| 0x54501430
 
| 0x54501430
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_SCP_UNK_50
+
| [[#TSEC_SCP_STAT0|TSEC_SCP_STAT0]]
 
| 0x54501450
 
| 0x54501450
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_SCP_AUTH_STAT|TSEC_SCP_AUTH_STAT]]
+
| [[#TSEC_SCP_STAT1|TSEC_SCP_STAT1]]
 
| 0x54501454
 
| 0x54501454
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_SCP_AES_STAT|TSEC_SCP_AES_STAT]]
+
| [[#TSEC_SCP_STAT2|TSEC_SCP_STAT2]]
 
| 0x54501458
 
| 0x54501458
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_SCP_UNK_70
+
| [[#TSEC_SCP_RNG_STAT0|TSEC_SCP_RNG_STAT0]]
 
| 0x54501470
 
| 0x54501470
 +
| 0x04
 +
|-
 +
| [[#TSEC_SCP_RNG_STAT1|TSEC_SCP_RNG_STAT1]]
 +
| 0x54501474
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 631: Line 707:
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_SCP_UNK_94
+
| [[#TSEC_SCP_SEC_ERR|TSEC_SCP_SEC_ERR]]
 
| 0x54501494
 
| 0x54501494
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_SCP_INSN_ERR|TSEC_SCP_INSN_ERR]]
+
| [[#TSEC_SCP_CMD_ERR|TSEC_SCP_CMD_ERR]]
 
| 0x54501498
 
| 0x54501498
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TRNG_CLK_LIMIT_LOW
+
| [[#TSEC_SCP_RND_CTL0|TSEC_SCP_RND_CTL0]]
 
| 0x54501500
 
| 0x54501500
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TRNG_CLK_LIMIT_HIGH
+
| [[#TSEC_SCP_RND_CTL1|TSEC_SCP_RND_CTL1]]
 
| 0x54501504
 
| 0x54501504
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TRNG_UNK_08
+
| TSEC_SCP_RND_CTL2
 
| 0x54501508
 
| 0x54501508
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TRNG_TEST_CTL
+
| TSEC_SCP_RND_CTL3
 
| 0x5450150C
 
| 0x5450150C
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TRNG_TEST_CFG0
+
| TSEC_SCP_RND_CTL4
 
| 0x54501510
 
| 0x54501510
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TRNG_TEST_SEED0
+
| TSEC_SCP_RND_CTL5
 
| 0x54501514
 
| 0x54501514
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TRNG_TEST_CFG1
+
| TSEC_SCP_RND_CTL6
 
| 0x54501518
 
| 0x54501518
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TRNG_TEST_SEED1
+
| TSEC_SCP_RND_CTL7
 
| 0x5450151C
 
| 0x5450151C
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TRNG_UNK_20
+
| TSEC_SCP_RND_CTL8
 
| 0x54501520
 
| 0x54501520
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TRNG_UNK_24
+
| TSEC_SCP_RND_CTL9
 
| 0x54501524
 
| 0x54501524
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TRNG_UNK_28
+
| TSEC_SCP_RND_CTL10
 
| 0x54501528
 
| 0x54501528
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TRNG_CTL
+
| TSEC_SCP_RND_CTL11
 
| 0x5450152C
 
| 0x5450152C
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TFBIF_CTL
+
| [[#TSEC_TFBIF_CTL|TSEC_TFBIF_CTL]]
 
| 0x54501600
 
| 0x54501600
 
| 0x04
 
| 0x04
Line 695: Line 771:
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TFBIF_THROTTLE
+
| [[#TSEC_TFBIF_THROTTLE|TSEC_TFBIF_THROTTLE]]
 
| 0x54501608
 
| 0x54501608
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TFBIF_UNK_0C
+
| [[#TSEC_TFBIF_DBG_STAT0|TSEC_TFBIF_DBG_STAT0]]
 
| 0x5450160C
 
| 0x5450160C
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TFBIF_DEBUG_STAT
+
| [[#TSEC_TFBIF_DBG_STAT1|TSEC_TFBIF_DBG_STAT1]]
 +
| 0x54501610
 +
| 0x04
 +
|-
 +
| [[#TSEC_TFBIF_DBG_RDCOUNT_LO|TSEC_TFBIF_DBG_RDCOUNT_LO]]
 +
| 0x54501614
 +
| 0x04
 +
|-
 +
| [[#TSEC_TFBIF_DBG_RDCOUNT_HI|TSEC_TFBIF_DBG_RDCOUNT_HI]]
 +
| 0x54501618
 +
| 0x04
 +
|-
 +
| [[#TSEC_TFBIF_DBG_WRCOUNT_LO|TSEC_TFBIF_DBG_WRCOUNT_LO]]
 +
| 0x5450161C
 +
| 0x04
 +
|-
 +
| [[#TSEC_TFBIF_DBG_WRCOUNT_HI|TSEC_TFBIF_DBG_WRCOUNT_HI]]
 +
| 0x54501620
 +
| 0x04
 +
|-
 +
| [[#TSEC_TFBIF_DBG_R32COUNT|TSEC_TFBIF_DBG_R32COUNT]]
 +
| 0x54501624
 +
| 0x04
 +
|-
 +
| [[#TSEC_TFBIF_DBG_R64COUNT|TSEC_TFBIF_DBG_R64COUNT]]
 +
| 0x54501628
 +
| 0x04
 +
|-
 +
| [[#TSEC_TFBIF_DBG_R128COUNT|TSEC_TFBIF_DBG_R128COUNT]]
 +
| 0x5450162C
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_UNK_30
 
| 0x54501630
 
| 0x54501630
 
| 0x04
 
| 0x04
Line 711: Line 819:
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_TFBIF_MMU_PROT|TSEC_TFBIF_MMU_PROT]]
+
| [[#TSEC_TFBIF_WRR_RDP|TSEC_TFBIF_WRR_RDP]]
 +
| 0x54501638
 +
| 0x04
 +
|-
 +
| [[#TSEC_TFBIF_SPROT_EMEM|TSEC_TFBIF_SPROT_EMEM]]
 
| 0x54501640
 
| 0x54501640
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_TFBIF_MMU_PHYS_SEC|TSEC_TFBIF_MMU_PHYS_SEC]]
+
| [[#TSEC_TFBIF_TRANSCFG|TSEC_TFBIF_TRANSCFG]]
 
| 0x54501644
 
| 0x54501644
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_TFBIF_MMU_TRANSCFG|TSEC_TFBIF_MMU_TRANSCFG]]
+
| [[#TSEC_TFBIF_REGIONCFG|TSEC_TFBIF_REGIONCFG]]
 
| 0x54501648
 
| 0x54501648
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_TFBIF_ACTMON_MAMASK|TSEC_TFBIF_ACTMON_MAMASK]]
+
| [[#TSEC_TFBIF_ACTMON_ACTIVE_MASK|TSEC_TFBIF_ACTMON_ACTIVE_MASK]]
 
| 0x5450164C
 
| 0x5450164C
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_TFBIF_ACTMON_BORPS|TSEC_TFBIF_ACTMON_BORPS]]
+
| [[#TSEC_TFBIF_ACTMON_ACTIVE_BORPS|TSEC_TFBIF_ACTMON_ACTIVE_BORPS]]
 
| 0x54501650
 
| 0x54501650
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_TFBIF_ACTMON_CTL|TSEC_TFBIF_ACTMON_CTL]]
+
| [[#TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT|TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT]]
 
| 0x54501654
 
| 0x54501654
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_CG|TSEC_CG]]
+
| [[#TSEC_TFBIF_ACTMON_MCB_MASK|TSEC_TFBIF_ACTMON_MCB_MASK]]
| 0x545016D0
+
| 0x54501660
 
| 0x04
 
| 0x04
 
|-
 
|-
| [[#TSEC_BAR0_CTL|TSEC_BAR0_CTL]]
+
| [[#TSEC_TFBIF_ACTMON_MCB_BORPS|TSEC_TFBIF_ACTMON_MCB_BORPS]]
| 0x54501700
+
| 0x54501664
 +
| 0x04
 +
|-
 +
| [[#TSEC_TFBIF_ACTMON_MCB_WEIGHT|TSEC_TFBIF_ACTMON_MCB_WEIGHT]]
 +
| 0x54501668
 +
| 0x04
 +
|-
 +
| [[#TSEC_TFBIF_THI_TRANSPROP|TSEC_TFBIF_THI_TRANSPROP]]
 +
| 0x54501670
 +
| 0x04
 +
|-
 +
| [[#TSEC_CG|TSEC_CG]]
 +
| 0x545016D0
 +
| 0x04
 +
|-
 +
| [[#TSEC_BAR0_CTL|TSEC_BAR0_CTL]]
 +
| 0x54501700
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 755: Line 883:
 
| 0x04
 
| 0x04
 
|-
 
|-
| TSEC_TEGRA_FALCON_IP_VER
+
| TSEC_TEGRA_UNK_00
 
| 0x54501800
 
| 0x54501800
 
| 0x04
 
| 0x04
Line 816: Line 944:
 
|}
 
|}
  
=== TSEC_THI_METHOD0 ===
+
=== TSEC_THI_INCR_SYNCPT ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
ID
+
Bits
Method
+
Description
 
|-
 
|-
| 0x200
+
| 0-9
| SET_APPLICATION_ID
+
| TSEC_THI_INCR_SYNCPT_INDX
 
|-
 
|-
| 0x300
+
| 10-17
| EXECUTE
+
| TSEC_THI_INCR_SYNCPT_COND
 +
|}
 +
 
 +
=== TSEC_THI_INCR_SYNCPT_CTRL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x500
+
| 0
| HDCP_INIT
+
| TSEC_THI_INCR_SYNCPT_CTRL_SOFT_RESET
 
|-
 
|-
| 0x504
+
| 8
| HDCP_CREATE_SESSION
+
| TSEC_THI_INCR_SYNCPT_CTRL_NO_STALL
 
|-
 
|-
| 0x508
+
| 16
| HDCP_VERIFY_CERT_RX
+
| TSEC_THI_INCR_SYNCPT_CTRL_SOFT_RESET_0
 
|-
 
|-
| 0x50C
+
| 17
| HDCP_GENERATE_EKM
+
| TSEC_THI_INCR_SYNCPT_CTRL_NO_STALL_0
 
|-
 
|-
| 0x510
+
| 18
| HDCP_REVOCATION_CHECK
+
| TSEC_THI_INCR_SYNCPT_CTRL_SOFT_RESET_1
 
|-
 
|-
| 0x514
+
| 19
| HDCP_VERIFY_HPRIME
+
| TSEC_THI_INCR_SYNCPT_CTRL_NO_STALL_1
 
|-
 
|-
| 0x518
+
| 20
| HDCP_ENCRYPT_PAIRING_INFO
+
| TSEC_THI_INCR_SYNCPT_CTRL_SOFT_RESET_2
 
|-
 
|-
| 0x51C
+
| 21
| HDCP_DECRYPT_PAIRING_INFO
+
| TSEC_THI_INCR_SYNCPT_CTRL_NO_STALL_2
 
|-
 
|-
| 0x520
+
| 22
| HDCP_UPDATE_SESSION
+
| TSEC_THI_INCR_SYNCPT_CTRL_SOFT_RESET_3
 
|-
 
|-
| 0x524
+
| 23
| HDCP_GENERATE_LC_INIT
+
| TSEC_THI_INCR_SYNCPT_CTRL_NO_STALL_3
 
|-
 
|-
| 0x528
+
| 24
| HDCP_VERIFY_LPRIME
+
| TSEC_THI_INCR_SYNCPT_CTRL_SOFT_RESET_4
 
|-
 
|-
| 0x52C
+
| 25
| HDCP_GENERATE_SKE_INIT
+
| TSEC_THI_INCR_SYNCPT_CTRL_NO_STALL_4
 +
|}
 +
 
 +
=== TSEC_THI_INCR_SYNCPT_ERR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x530
+
| 0
| HDCP_VERIFY_VPRIME
+
| TSEC_THI_INCR_SYNCPT_ERR_COND_STS_IMM
 
|-
 
|-
| 0x534
+
| 1
| HDCP_ENCRYPTION_RUN_CTRL
+
| TSEC_THI_INCR_SYNCPT_ERR_COND_STS_OPDONE
 
|-
 
|-
| 0x538
+
| 2
| HDCP_SESSION_CTRL
+
| TSEC_THI_INCR_SYNCPT_ERR_COND_STS_RD_DONE
 
|-
 
|-
| 0x53C
+
| 3
| HDCP_COMPUTE_SPRIME
+
| TSEC_THI_INCR_SYNCPT_ERR_COND_STS_REG_WR_SAFE
 
|-
 
|-
| 0x540
+
| 4
| HDCP_GET_CERT_RX
+
| TSEC_THI_INCR_SYNCPT_ERR_COND_STS_ENGINE_IDLE
 +
|}
 +
 
 +
=== TSEC_THI_CTXSW_INCR_SYNCPT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x544
+
| 0-9
| HDCP_EXCHANGE_INFO
+
| TSEC_THI_CTXSW_INCR_SYNCPT_INDX
 +
|}
 +
 
 +
=== TSEC_THI_CTXSW ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x548
+
| 0-9
| HDCP_DECRYPT_KM
+
| TSEC_THI_CTXSW_CURR_CLASS
 
|-
 
|-
| 0x54C
+
| 10
| HDCP_GET_HPRIME
+
| TSEC_THI_CTXSW_AUTO_ACK
 
|-
 
|-
| 0x550
+
| 11-20
| HDCP_GENERATE_EKH_KM
+
| TSEC_THI_CTXSW_CURR_CHANNEL
 +
|}
 +
 
 +
=== TSEC_THI_CTXSW_NEXT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x554
+
| 0-9
| HDCP_VERIFY_RTT_CHALLENGE
+
| TSEC_THI_CTXSW_NEXT_NEXT_CLASS
 
|-
 
|-
| 0x558
+
| 10-19
| HDCP_GET_LPRIME
+
| TSEC_THI_CTXSW_NEXT_NEXT_CHANNEL
 +
|}
 +
 
 +
=== TSEC_THI_CONT_SYNCPT_EOF ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x55C
+
| 0-9
| HDCP_DECRYPT_KS
+
| TSEC_THI_CONT_SYNCPT_EOF_INDEX
 
|-
 
|-
| 0x560
+
| 10
| HDCP_DECRYPT
+
| TSEC_THI_CONT_SYNCPT_EOF_COND
 +
|}
 +
 
 +
=== TSEC_THI_CONT_SYNCPT_L1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x564
+
| 0-9
| HDCP_GET_RRX
+
| TSEC_THI_CONT_SYNCPT_L1_INDEX
 
|-
 
|-
| 0x568
+
| 10
| HDCP_DECRYPT_REENCRYPT
+
| TSEC_THI_CONT_SYNCPT_L1_COND
 +
|}
 +
 
 +
=== TSEC_THI_STREAMID0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x56C
+
| 0-6
|  
+
| TSEC_THI_STREAMID0_ID
 +
|}
 +
 
 +
=== TSEC_THI_STREAMID1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x570
+
| 0-6
|  
+
| TSEC_THI_STREAMID1_ID
 +
|}
 +
 
 +
=== TSEC_THI_THI_SEC ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x574
+
| 0
|  
+
| TSEC_THI_THI_SEC_TZ_LOCK
 +
|-
 +
| 4
 +
| TSEC_THI_THI_SEC_TZ_AUTH
 
|-
 
|-
| 0x578
+
| 8
|  
+
| TSEC_THI_THI_SEC_CH_LOCK
 +
|}
 +
 
 +
=== TSEC_THI_METHOD0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 0x57C
+
| 0-11
|  
+
| TSEC_THI_METHOD0_OFFSET
 +
|}
 +
 
 +
Used to encode and send a method's ID over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
 +
 
 +
The following methods are available:
 +
{| class="wikitable" border="1"
 +
!  ID
 +
!  Method
 
|-
 
|-
| 0x700
+
| 0x100
| HDCP_VALIDATE_SRM
+
| NOP
 
|-
 
|-
| 0x704
+
| 0x140
| HDCP_VALIDATE_STREAM
+
| PM_TRIGGER
 
|-
 
|-
| 0x708
+
| 0x200
| HDCP_TEST_SECURE_STATUS
+
| SET_APPLICATION_ID
 
|-
 
|-
| 0x70C
+
| 0x204
| HDCP_SET_DCP_KPUB
+
| SET_WATCHDOG_TIMER
 
|-
 
|-
| 0x710
+
| 0x240
| HDCP_SET_RX_KPUB
+
| SEMAPHORE_A
 
|-
 
|-
| 0x714
+
| 0x244
| HDCP_SET_CERT_RX
+
| SEMAPHORE_B
 
|-
 
|-
| 0x718
+
| 0x248
| HDCP_SET_SCRATCH_BUFFER
+
| SEMAPHORE_C
 
|-
 
|-
| 0x71C
+
| 0x24C
| HDCP_SET_SRM
+
|  
 
|-
 
|-
| 0x720
+
| 0x250
| HDCP_SET_RECEIVER_ID_LIST
+
|  
 
|-
 
|-
| 0x724
+
| 0x300
| HDCP_SET_SPRIME
+
| EXECUTE
 
|-
 
|-
| 0x728
+
| 0x304
| HDCP_SET_ENC_INPUT_BUFFER
+
| SEMAPHORE_D
 
|-
 
|-
| 0x72C
+
| 0x500
| HDCP_SET_ENC_OUTPUT_BUFFER
+
| HDCP_INIT
 
|-
 
|-
| 0x730
+
| 0x504
| HDCP_GET_RTT_CHALLENGE
+
| HDCP_CREATE_SESSION
 
|-
 
|-
| 0x734
+
| 0x508
| HDCP_STREAM_MANAGE
+
| HDCP_VERIFY_CERT_RX
 
|-
 
|-
| 0x738
+
| 0x50C
| HDCP_READ_CAPS
+
| HDCP_GENERATE_EKM
 
|-
 
|-
| 0x73C
+
| 0x510
| HDCP_ENCRYPT
+
| HDCP_REVOCATION_CHECK
 
|-
 
|-
| 0x740
+
| 0x514
| [6.0.0+] HDCP_GET_CURRENT_NONCE
+
| HDCP_VERIFY_HPRIME
|}
 
 
 
Used to encode and send a method's ID over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
 
 
 
=== TSEC_THI_METHOD1 ===
 
Used to encode and send a method's data over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
 
 
 
=== TSEC_THI_INT_STATUS ===
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Description
 
 
|-
 
|-
| 0
+
| 0x518
| TSEC_THI_INT_STATUS_FALCON_INT
+
| HDCP_ENCRYPT_PAIRING_INFO
|}
 
 
 
=== TSEC_THI_INT_MASK ===
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Description
 
 
|-
 
|-
| 0
+
| 0x51C
| TSEC_THI_INT_MASK_FALCON_INT
+
| HDCP_DECRYPT_PAIRING_INFO
|}
 
 
 
=== FALCON_IRQSSET ===
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Description
 
 
|-
 
|-
| 0
+
| 0x520
| FALCON_IRQSSET_GPTMR
+
| HDCP_UPDATE_SESSION
 
|-
 
|-
| 1
+
| 0x524
| FALCON_IRQSSET_WDTMR
+
| HDCP_GENERATE_LC_INIT
 
|-
 
|-
| 2
+
| 0x528
| FALCON_IRQSSET_MTHD
+
| HDCP_VERIFY_LPRIME
 
|-
 
|-
| 3
+
| 0x52C
| FALCON_IRQSSET_CTXSW
+
| HDCP_GENERATE_SKE_INIT
 
|-
 
|-
| 4
+
| 0x530
| FALCON_IRQSSET_HALT
+
| HDCP_VERIFY_VPRIME
 
|-
 
|-
| 5
+
| 0x534
| FALCON_IRQSSET_EXTERR
+
| HDCP_ENCRYPTION_RUN_CTRL
 
|-
 
|-
| 6
+
| 0x538
| FALCON_IRQSSET_SWGEN0
+
| HDCP_SESSION_CTRL
 
|-
 
|-
| 7
+
| 0x53C
| FALCON_IRQSSET_SWGEN1
+
| HDCP_COMPUTE_SPRIME
 
|-
 
|-
| 8-15
+
| 0x540
| FALCON_IRQSSET_EXT
+
| HDCP_GET_CERT_RX
|}
 
 
 
Used for setting Falcon's IRQs.
 
 
 
=== FALCON_IRQSCLR ===
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Description
 
 
|-
 
|-
| 0
+
| 0x544
| FALCON_IRQSCLR_GPTMR
+
| HDCP_EXCHANGE_INFO
 
|-
 
|-
| 1
+
| 0x548
| FALCON_IRQSCLR_WDTMR
+
| HDCP_DECRYPT_KM
 
|-
 
|-
| 2
+
| 0x54C
| FALCON_IRQSCLR_MTHD
+
| HDCP_GET_HPRIME
 
|-
 
|-
| 3
+
| 0x550
| FALCON_IRQSCLR_CTXSW
+
| HDCP_GENERATE_EKH_KM
 
|-
 
|-
| 4
+
| 0x554
| FALCON_IRQSCLR_HALT
+
| HDCP_VERIFY_RTT_CHALLENGE
 
|-
 
|-
| 5
+
| 0x558
| FALCON_IRQSCLR_EXTERR
+
| HDCP_GET_LPRIME
 
|-
 
|-
| 6
+
| 0x55C
| FALCON_IRQSCLR_SWGEN0
+
| HDCP_DECRYPT_KS
 
|-
 
|-
| 7
+
| 0x560
| FALCON_IRQSCLR_SWGEN1
+
| HDCP_DECRYPT
 
|-
 
|-
| 8-15
+
| 0x564
| FALCON_IRQSCLR_EXT
+
| HDCP_GET_RRX
|}
 
 
 
Used for clearing Falcon's IRQs.
 
 
 
=== FALCON_IRQSTAT ===
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Description
 
 
|-
 
|-
| 0
+
| 0x568
| FALCON_IRQSTAT_GPTMR
+
| HDCP_DECRYPT_REENCRYPT
 
|-
 
|-
| 1
+
| 0x56C
| FALCON_IRQSTAT_WDTMR
+
|  
 
|-
 
|-
| 2
+
| 0x570
| FALCON_IRQSTAT_MTHD
+
|  
 
|-
 
|-
| 3
+
| 0x574
| FALCON_IRQSTAT_CTXSW
+
| HDCP_DECRYPT_STORED_KM
 
|-
 
|-
| 4
+
| 0x578
| FALCON_IRQSTAT_HALT
+
| HDCP_GET_CURRENT_RESOLUTION
 
|-
 
|-
| 5
+
| 0x57C
| FALCON_IRQSTAT_EXTERR
+
| HDCP_GET_CURRENT_VERSION
 
|-
 
|-
| 6
+
| 0x700
| FALCON_IRQSTAT_SWGEN0
+
| HDCP_VALIDATE_SRM
 
|-
 
|-
| 7
+
| 0x704
| FALCON_IRQSTAT_SWGEN1
+
| HDCP_VALIDATE_STREAM
 
|-
 
|-
| 8-15
+
| 0x708
| FALCON_IRQSTAT_EXT
+
| HDCP_TEST_SECURE_STATUS
|}
 
 
 
Used for getting the status of Falcon's IRQs.
 
 
 
=== FALCON_IRQMODE ===
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Description
 
 
|-
 
|-
| 0
+
| 0x70C
| FALCON_IRQMODE_LVL_GPTMR
+
| HDCP_SET_DCP_KPUB
 
|-
 
|-
| 1
+
| 0x710
| FALCON_IRQMODE_LVL_WDTMR
+
| HDCP_SET_RX_KPUB
 
|-
 
|-
| 2
+
| 0x714
| FALCON_IRQMODE_LVL_MTHD
+
| HDCP_SET_CERT_RX
 
|-
 
|-
| 3
+
| 0x718
| FALCON_IRQMODE_LVL_CTXSW
+
| HDCP_SET_SCRATCH_BUFFER
 
|-
 
|-
| 4
+
| 0x71C
| FALCON_IRQMODE_LVL_HALT
+
| HDCP_SET_SRM
 
|-
 
|-
| 5
+
| 0x720
| FALCON_IRQMODE_LVL_EXTERR
+
| HDCP_SET_RECEIVER_ID_LIST
 
|-
 
|-
| 6
+
| 0x724
| FALCON_IRQMODE_LVL_SWGEN0
+
| HDCP_SET_SPRIME
 +
|-
 +
| 0x728
 +
| HDCP_SET_ENC_INPUT_BUFFER
 +
|-
 +
| 0x72C
 +
| HDCP_SET_ENC_OUTPUT_BUFFER
 +
|-
 +
| 0x730
 +
| HDCP_GET_RTT_CHALLENGE
 +
|-
 +
| 0x734
 +
| HDCP_STREAM_MANAGE
 +
|-
 +
| 0x738
 +
| HDCP_READ_CAPS
 +
|-
 +
| 0x73C
 +
| HDCP_ENCRYPT
 +
|-
 +
| 0x740
 +
| [6.0.0+] HDCP_GET_CURRENT_NONCE
 
|-
 
|-
| 7
+
| 0x1114
| FALCON_IRQMODE_LVL_SWGEN1
+
| PM_TRIGGER_END
 +
|}
 +
 
 +
=== TSEC_THI_METHOD1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 8-15
+
| 0-31
| FALCON_IRQMODE_LVL_EXT
+
| TSEC_THI_METHOD1_DATA
 
|}
 
|}
  
Used for changing the mode Falcon's IRQs. A value of 1 means level triggered while a value of 0 means edge triggered.
+
Used to encode and send a method's data over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
  
=== FALCON_IRQMSET ===
+
=== TSEC_THI_CONTEXT_SWITCH ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-27
| FALCON_IRQMSET_GPTMR
+
| TSEC_THI_CONTEXT_SWITCH_PTR
 
|-
 
|-
| 1
+
| 30-31
| FALCON_IRQMSET_WDTMR
+
| TSEC_THI_CONTEXT_SWITCH_TARGET
 +
|}
 +
 
 +
=== TSEC_THI_INT_STATUS ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 2
+
| 0
| FALCON_IRQMSET_MTHD
+
| TSEC_THI_INT_STATUS_FALCON_INT
 +
|}
 +
 
 +
=== TSEC_THI_INT_MASK ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_THI_INT_MASK_FALCON_INT
 +
|}
 +
 
 +
=== TSEC_THI_CONFIG0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 3
+
| 0
| FALCON_IRQMSET_CTXSW
+
| TSEC_THI_CONFIG0_RETURN_SYNCPT_ON_ERR
 
|-
 
|-
 
| 4
 
| 4
| FALCON_IRQMSET_HALT
+
| TSEC_THI_CONFIG0_IDLE_SYNCPT_INC_ENG
|-
 
| 5
 
| FALCON_IRQMSET_EXTERR
 
|-
 
| 6
 
| FALCON_IRQMSET_SWGEN0
 
|-
 
| 7
 
| FALCON_IRQMSET_SWGEN1
 
|-
 
| 8-15
 
| FALCON_IRQMSET_EXT
 
 
|}
 
|}
  
Used for setting the mask for Falcon's IRQs.
+
=== TSEC_THI_DBG_MISC ===
 
 
=== FALCON_IRQMCLR ===
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,179: Line 1,371:
 
|-
 
|-
 
| 0
 
| 0
| FALCON_IRQMCLR_GPTMR
+
| TSEC_THI_DBG_MISC_CLIENT_IDLE_STATUS
 
|-
 
|-
 
| 1
 
| 1
| FALCON_IRQMCLR_WDTMR
+
| TSEC_THI_DBG_MISC_THI_IDLE_STATUS
 
|-
 
|-
 
| 2
 
| 2
| FALCON_IRQMCLR_MTHD
+
| TSEC_THI_DBG_MISC_THI_SYNCPT_PENDING_STATUS
 
|-
 
|-
 
| 3
 
| 3
| FALCON_IRQMCLR_CTXSW
+
| TSEC_THI_DBG_MISC_THI_IDLE_EN
|-
+
|}
| 4
+
 
| FALCON_IRQMCLR_HALT
+
=== TSEC_THI_SLCG_OVERRIDE_HIGH_A ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 5
+
| 0-7
| FALCON_IRQMCLR_EXTERR
+
| TSEC_THI_SLCG_OVERRIDE_HIGH_A_REG
 +
|}
 +
 
 +
=== TSEC_THI_SLCG_OVERRIDE_LOW_A ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 6
+
| 0-31
| FALCON_IRQMCLR_SWGEN0
+
| TSEC_THI_SLCG_OVERRIDE_LOW_A_REG
|-
+
|}
| 7
+
 
| FALCON_IRQMCLR_SWGEN1
+
=== TSEC_THI_CLK_OVERRIDE ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 8-15
+
| 0-31
| FALCON_IRQMCLR_EXT
+
| TSEC_THI_CLK_OVERRIDE_CYA
 
|}
 
|}
  
Used for clearing the mask for Falcon's IRQs.
+
=== TSEC_FALCON_IRQSSET ===
 
 
=== FALCON_IRQMASK ===
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,214: Line 1,416:
 
|-
 
|-
 
| 0
 
| 0
| FALCON_IRQMASK_GPTMR
+
| TSEC_FALCON_IRQSSET_GPTMR
 
|-
 
|-
 
| 1
 
| 1
| FALCON_IRQMASK_WDTMR
+
| TSEC_FALCON_IRQSSET_WDTMR
 
|-
 
|-
 
| 2
 
| 2
| FALCON_IRQMASK_MTHD
+
| TSEC_FALCON_IRQSSET_MTHD
 
|-
 
|-
 
| 3
 
| 3
| FALCON_IRQMASK_CTXSW
+
| TSEC_FALCON_IRQSSET_CTXSW
 
|-
 
|-
 
| 4
 
| 4
| FALCON_IRQMASK_HALT
+
| TSEC_FALCON_IRQSSET_HALT
 
|-
 
|-
 
| 5
 
| 5
| FALCON_IRQMASK_EXTERR
+
| TSEC_FALCON_IRQSSET_EXTERR
 
|-
 
|-
 
| 6
 
| 6
| FALCON_IRQMASK_SWGEN0
+
| TSEC_FALCON_IRQSSET_SWGEN0
 
|-
 
|-
 
| 7
 
| 7
| FALCON_IRQMASK_SWGEN1
+
| TSEC_FALCON_IRQSSET_SWGEN1
 
|-
 
|-
 
| 8-15
 
| 8-15
| FALCON_IRQMASK_EXT
+
| TSEC_FALCON_IRQSSET_EXT
 +
|-
 +
| 16
 +
| TSEC_FALCON_IRQSSET_DMA
 
|}
 
|}
  
Used for getting the value of the mask for Falcon's IRQs.
+
Used for setting Falcon's IRQs.
  
=== FALCON_IRQDEST ===
+
=== TSEC_FALCON_IRQSCLR ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,249: Line 1,454:
 
|-
 
|-
 
| 0
 
| 0
| FALCON_IRQDEST_HOST_GPTMR
+
| TSEC_FALCON_IRQSCLR_GPTMR
 
|-
 
|-
 
| 1
 
| 1
| FALCON_IRQDEST_HOST_WDTMR
+
| TSEC_FALCON_IRQSCLR_WDTMR
 
|-
 
|-
 
| 2
 
| 2
| FALCON_IRQDEST_HOST_MTHD
+
| TSEC_FALCON_IRQSCLR_MTHD
 
|-
 
|-
 
| 3
 
| 3
| FALCON_IRQDEST_HOST_CTXSW
+
| TSEC_FALCON_IRQSCLR_CTXSW
 
|-
 
|-
 
| 4
 
| 4
| FALCON_IRQDEST_HOST_HALT
+
| TSEC_FALCON_IRQSCLR_HALT
 
|-
 
|-
 
| 5
 
| 5
| FALCON_IRQDEST_HOST_EXTERR
+
| TSEC_FALCON_IRQSCLR_EXTERR
 
|-
 
|-
 
| 6
 
| 6
| FALCON_IRQDEST_HOST_SWGEN0
+
| TSEC_FALCON_IRQSCLR_SWGEN0
 
|-
 
|-
 
| 7
 
| 7
| FALCON_IRQDEST_HOST_SWGEN1
+
| TSEC_FALCON_IRQSCLR_SWGEN1
 
|-
 
|-
 
| 8-15
 
| 8-15
| FALCON_IRQDEST_HOST_EXT
+
| TSEC_FALCON_IRQSCLR_EXT
 
|-
 
|-
 
| 16
 
| 16
| FALCON_IRQDEST_TARGET_GPTMR
+
| TSEC_FALCON_IRQSCLR_DMA
 +
|}
 +
 
 +
Used for clearing Falcon's IRQs.
 +
 
 +
=== TSEC_FALCON_IRQSTAT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 17
+
| 0
| FALCON_IRQDEST_TARGET_WDTMR
+
| TSEC_FALCON_IRQSTAT_GPTMR
 
|-
 
|-
| 18
+
| 1
| FALCON_IRQDEST_TARGET_MTHD
+
| TSEC_FALCON_IRQSTAT_WDTMR
 
|-
 
|-
| 19
+
| 2
| FALCON_IRQDEST_TARGET_CTXSW
+
| TSEC_FALCON_IRQSTAT_MTHD
 +
|-
 +
| 3
 +
| TSEC_FALCON_IRQSTAT_CTXSW
 +
|-
 +
| 4
 +
| TSEC_FALCON_IRQSTAT_HALT
 
|-
 
|-
| 20
+
| 5
| FALCON_IRQDEST_TARGET_HALT
+
| TSEC_FALCON_IRQSTAT_EXTERR
 
|-
 
|-
| 21
+
| 6
| FALCON_IRQDEST_TARGET_EXTERR
+
| TSEC_FALCON_IRQSTAT_SWGEN0
 
|-
 
|-
| 22
+
| 7
| FALCON_IRQDEST_TARGET_SWGEN0
+
| TSEC_FALCON_IRQSTAT_SWGEN1
 
|-
 
|-
| 23
+
| 8-15
| FALCON_IRQDEST_TARGET_SWGEN1
+
| TSEC_FALCON_IRQSTAT_EXT
 
|-
 
|-
| 24-31
+
| 16
| FALCON_IRQDEST_TARGET_EXT
+
| TSEC_FALCON_IRQSTAT_DMA
 
|}
 
|}
  
Used for routing Falcon's IRQs.
+
Used for getting the status of Falcon's IRQs.
  
=== FALCON_MAILBOX0 ===
+
=== TSEC_FALCON_IRQMODE ===
Scratch register for reading/writing data to Falcon.
 
 
 
=== FALCON_MAILBOX1 ===
 
Scratch register for reading/writing data to Falcon.
 
 
 
=== FALCON_ITFEN ===
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,317: Line 1,530:
 
|-
 
|-
 
| 0
 
| 0
| FALCON_ITFEN_CTXEN
+
| TSEC_FALCON_IRQMODE_LVL_GPTMR
 
|-
 
|-
 
| 1
 
| 1
| FALCON_ITFEN_MTHDEN
+
| TSEC_FALCON_IRQMODE_LVL_WDTMR
|}
+
|-
 
+
| 2
Used for enabling/disabling Falcon interfaces.
+
| TSEC_FALCON_IRQMODE_LVL_MTHD
 
 
=== FALCON_IDLESTATE ===
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Description
 
 
|-
 
|-
| 0
+
| 3
| FALCON_IDLESTATE_FALCON_BUSY
+
| TSEC_FALCON_IRQMODE_LVL_CTXSW
 
|-
 
|-
| 1-15
+
| 4
| FALCON_IDLESTATE_EXT_BUSY
+
| TSEC_FALCON_IRQMODE_LVL_HALT
|}
+
|-
 
+
| 5
Used for detecting if Falcon is busy or not.
+
| TSEC_FALCON_IRQMODE_LVL_EXTERR
 
 
=== FALCON_DEBUG1 ===
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Description
 
 
|-
 
|-
| 0-15
+
| 6
| FALCON_DEBUG1_MTHD_DRAIN_TIME
+
| TSEC_FALCON_IRQMODE_LVL_SWGEN0
 
|-
 
|-
| 16
+
| 7
| FALCON_DEBUG1_CTXSW_MODE
+
| TSEC_FALCON_IRQMODE_LVL_SWGEN1
|}
 
 
 
=== FALCON_DEBUGINFO ===
 
Used for UCODE self revocation. This register takes the base address of the GSC carveout shifted right by 8.
 
 
 
[6.0.0+] [[NV_services|nvservices]] sets this to 0x8005FF00 >> 8 (physical DRAM address inside the GPU UCODE carveout) before starting the nvhost_tsec firmware.
 
 
 
=== FALCON_EXCI ===
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Description
 
 
|-
 
|-
| 0-19
+
| 8-15
| PC that originated the exception
+
| TSEC_FALCON_IRQMODE_LVL_EXT
 
|-
 
|-
| 20-23
+
| 16
| Exception type
+
| TSEC_FALCON_IRQMODE_LVL_DMA
0x00: Trap 0
 
0x01: Trap 1
 
0x02: Trap 2
 
0x03: Trap 3
 
0x08: Invalid opcode
 
0x09: Authentication entry
 
0x0A: Page fault (no hit)
 
0x0B: Page fault (multi hit)
 
0x0F: Breakpoint
 
 
|}
 
|}
  
Contains information about raised exceptions.
+
Used for changing the mode Falcon's IRQs. A value of 1 means level triggered while a value of 0 means edge triggered.
  
=== FALCON_CPUCTL ===
+
=== TSEC_FALCON_IRQMSET ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,385: Line 1,568:
 
|-
 
|-
 
| 0
 
| 0
| FALCON_CPUCTL_IINVAL
+
| TSEC_FALCON_IRQMSET_GPTMR
 
|-
 
|-
 
| 1
 
| 1
| FALCON_CPUCTL_STARTCPU
+
| TSEC_FALCON_IRQMSET_WDTMR
 
|-
 
|-
 
| 2
 
| 2
| FALCON_CPUCTL_SRESET
+
| TSEC_FALCON_IRQMSET_MTHD
 
|-
 
|-
 
| 3
 
| 3
| FALCON_CPUCTL_HRESET
+
| TSEC_FALCON_IRQMSET_CTXSW
 
|-
 
|-
 
| 4
 
| 4
| FALCON_CPUCTL_HALTED
+
| TSEC_FALCON_IRQMSET_HALT
 
|-
 
|-
 
| 5
 
| 5
| FALCON_CPUCTL_STOPPED
+
| TSEC_FALCON_IRQMSET_EXTERR
 
|-
 
|-
 
| 6
 
| 6
| FALCON_CPUCTL_CPUCTL_ALIAS_EN
+
| TSEC_FALCON_IRQMSET_SWGEN0
 +
|-
 +
| 7
 +
| TSEC_FALCON_IRQMSET_SWGEN1
 +
|-
 +
| 8-15
 +
| TSEC_FALCON_IRQMSET_EXT
 +
|-
 +
| 16
 +
| TSEC_FALCON_IRQMSET_DMA
 
|}
 
|}
  
Used for signaling the Falcon CPU.
+
Used for setting the mask for Falcon's IRQs.
 
 
=== FALCON_BOOTVEC ===
 
Takes the Falcon's boot vector address.
 
  
=== FALCON_HWCFG ===
+
=== TSEC_FALCON_IRQMCLR ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-8
+
| 0
| FALCON_HWCFG_IMEM_SIZE
+
| TSEC_FALCON_IRQMCLR_GPTMR
 +
|-
 +
| 1
 +
| TSEC_FALCON_IRQMCLR_WDTMR
 
|-
 
|-
| 9-17
+
| 2
| FALCON_HWCFG_DMEM_SIZE
+
| TSEC_FALCON_IRQMCLR_MTHD
 
|-
 
|-
| 18-26
+
| 3
| FALCON_HWCFG_METHODFIFO_DEPTH
+
| TSEC_FALCON_IRQMCLR_CTXSW
 
|-
 
|-
| 27-31
+
| 4
| FALCON_HWCFG_DMAQUEUE_DEPTH
+
| TSEC_FALCON_IRQMCLR_HALT
|}
 
 
 
=== FALCON_DMACTL ===
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Description
 
 
|-
 
|-
| 0
+
| 5
| FALCON_DMACTL_REQUIRE_CTX
+
| TSEC_FALCON_IRQMCLR_EXTERR
 
|-
 
|-
| 1
+
| 6
| FALCON_DMACTL_DMEM_SCRUBBING
+
| TSEC_FALCON_IRQMCLR_SWGEN0
 
|-
 
|-
| 2
+
| 7
| FALCON_DMACTL_IMEM_SCRUBBING
+
| TSEC_FALCON_IRQMCLR_SWGEN1
 
|-
 
|-
| 3-6
+
| 8-15
| FALCON_DMACTL_DMAQ_NUM
+
| TSEC_FALCON_IRQMCLR_EXT
 
|-
 
|-
| 7
+
| 16
| FALCON_DMACTL_SECURE_STAT
+
| TSEC_FALCON_IRQMCLR_DMA
 
|}
 
|}
  
Used for configuring the Falcon's DMA engine.
+
Used for clearing the mask for Falcon's IRQs.
 
 
=== FALCON_DMATRFBASE ===
 
Base address of the external memory buffer, shifted right by 8.
 
 
 
The current transfer address is calculated by adding [[#FALCON_DMATRFFBOFFS|FALCON_DMATRFFBOFFS]] to the base.
 
  
=== FALCON_DMATRFMOFFS ===
+
=== TSEC_FALCON_IRQMASK ===
For transfers to DMEM: the destination address.
 
For transfers to IMEM: the destination virtual IMEM page.
 
 
 
=== FALCON_DMATRFCMD ===
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,467: Line 1,644:
 
|-
 
|-
 
| 0
 
| 0
| FALCON_DMATRFCMD_FULL
+
| TSEC_FALCON_IRQMASK_GPTMR
 
|-
 
|-
 
| 1
 
| 1
| FALCON_DMATRFCMD_IDLE
+
| TSEC_FALCON_IRQMASK_WDTMR
 
|-
 
|-
| 2-3
+
| 2
| FALCON_DMATRFCMD_SEC
+
| TSEC_FALCON_IRQMASK_MTHD
 +
|-
 +
| 3
 +
| TSEC_FALCON_IRQMASK_CTXSW
 
|-
 
|-
 
| 4
 
| 4
| FALCON_DMATRFCMD_IMEM
+
| TSEC_FALCON_IRQMASK_HALT
 
|-
 
|-
 
| 5
 
| 5
| FALCON_DMATRFCMD_WRITE
+
| TSEC_FALCON_IRQMASK_EXTERR
 
|-
 
|-
| 8-10
+
| 6
| FALCON_DMATRFCMD_SIZE
+
| TSEC_FALCON_IRQMASK_SWGEN0
 +
|-
 +
| 7
 +
| TSEC_FALCON_IRQMASK_SWGEN1
 +
|-
 +
| 8-15
 +
| TSEC_FALCON_IRQMASK_EXT
 
|-
 
|-
| 12-14
+
| 16
| FALCON_DMATRFCMD_CTXDMA
+
| TSEC_FALCON_IRQMASK_DMA
 
|}
 
|}
  
Used for configuring DMA transfers.
+
Used for getting the value of the mask for Falcon's IRQs.
  
=== FALCON_DMATRFFBOFFS ===
+
=== TSEC_FALCON_IRQDEST ===
For transfers to IMEM: the destination physical IMEM page.
 
 
 
=== FALCON_DMAPOLL_FB ===
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,499: Line 1,682:
 
|-
 
|-
 
| 0
 
| 0
| FALCON_DMAPOLL_FB_FENCE_ACTIVE
+
| TSEC_FALCON_IRQDEST_HOST_GPTMR
 
|-
 
|-
 
| 1
 
| 1
| FALCON_DMAPOLL_FB_DMA_ACTIVE
+
| TSEC_FALCON_IRQDEST_HOST_WDTMR
 +
|-
 +
| 2
 +
| TSEC_FALCON_IRQDEST_HOST_MTHD
 +
|-
 +
| 3
 +
| TSEC_FALCON_IRQDEST_HOST_CTXSW
 
|-
 
|-
 
| 4
 
| 4
| FALCON_DMAPOLL_FB_CFG_R_FENCE
+
| TSEC_FALCON_IRQDEST_HOST_HALT
 
|-
 
|-
 
| 5
 
| 5
| FALCON_DMAPOLL_FB_CFG_W_FENCE
+
| TSEC_FALCON_IRQDEST_HOST_EXTERR
 
|-
 
|-
| 16-23
+
| 6
| FALCON_DMAPOLL_FB_WCOUNT
+
| TSEC_FALCON_IRQDEST_HOST_SWGEN0
 
|-
 
|-
| 24-31
+
| 7
| FALCON_DMAPOLL_FB_RCOUNT
+
| TSEC_FALCON_IRQDEST_HOST_SWGEN1
|}
 
 
 
Contains the status of a DMA transfer between the Falcon and external memory.
 
 
 
=== FALCON_DMAPOLL_CP ===
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Description
 
 
|-
 
|-
| 0
+
| 8-15
| FALCON_DMAPOLL_CP_FENCE_ACTIVE
+
| TSEC_FALCON_IRQDEST_HOST_EXT
 
|-
 
|-
| 1
+
| 16
| FALCON_DMAPOLL_CP_DMA_ACTIVE
+
| TSEC_FALCON_IRQDEST_TARGET_GPTMR
 
|-
 
|-
| 4
+
| 17
| FALCON_DMAPOLL_CP_CFG_R_FENCE
+
| TSEC_FALCON_IRQDEST_TARGET_WDTMR
 
|-
 
|-
| 5
+
| 18
| FALCON_DMAPOLL_CP_CFG_W_FENCE
+
| TSEC_FALCON_IRQDEST_TARGET_MTHD
 
|-
 
|-
| 16-23
+
| 19
| FALCON_DMAPOLL_CP_WCOUNT
+
| TSEC_FALCON_IRQDEST_TARGET_CTXSW
 +
|-
 +
| 20
 +
| TSEC_FALCON_IRQDEST_TARGET_HALT
 +
|-
 +
| 21
 +
| TSEC_FALCON_IRQDEST_TARGET_EXTERR
 +
|-
 +
| 22
 +
| TSEC_FALCON_IRQDEST_TARGET_SWGEN0
 +
|-
 +
| 23
 +
| TSEC_FALCON_IRQDEST_TARGET_SWGEN1
 
|-
 
|-
 
| 24-31
 
| 24-31
| FALCON_DMAPOLL_CP_RCOUNT
+
| TSEC_FALCON_IRQDEST_TARGET_EXT
 
|}
 
|}
  
Contains the status of a DMA transfer between the Falcon and the SCP.
+
Used for routing Falcon's IRQs.
  
=== FALCON_HWCFG1 ===
+
=== TSEC_FALCON_GPTMRINT ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-31
| FALCON_HWCFG1_CORE_REV
+
| TSEC_FALCON_GPTMRINT_VAL
|-
 
| 4-5
 
| FALCON_HWCFG1_SECURITY_MODEL
 
|-
 
| 6-7
 
| FALCON_HWCFG1_CORE_REV_SUBVERSION
 
|-
 
| 8-11
 
| FALCON_HWCFG1_IMEM_PORTS
 
|-
 
| 12-15
 
| FALCON_HWCFG1_DMEM_PORTS
 
|-
 
| 16-20
 
| FALCON_HWCFG1_TAG_WIDTH
 
|-
 
| 27
 
| FALCON_HWCFG1_DBG_PRIV_BUS
 
|-
 
| 28
 
| FALCON_HWCFG1_CSB_SIZE_16M
 
|-
 
| 29
 
| FALCON_HWCFG1_PRIV_DIRECT
 
|-
 
| 30
 
| FALCON_HWCFG1_DMEM_APERTURES
 
|-
 
| 31
 
| FALCON_HWCFG1_IMEM_AUTOFILL
 
 
|}
 
|}
  
=== FALCON_IMCTL ===
+
=== TSEC_FALCON_GPTMRVAL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-23
+
| 0-31
| Address
+
| TSEC_FALCON_GPTMRVAL_VAL
|-
 
| 24-26
 
| Command
 
0x00: NOP
 
0x01: IMINV (ITLB)
 
0x02: IMBLK (PTLB)
 
0x03: IMTAG (VTLB)
 
 
|}
 
|}
  
Controls the Falcon TLB.
+
=== TSEC_FALCON_GPTMRCTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_FALCON_GPTMRCTL_GPTMREN
 +
|}
  
=== FALCON_IMSTAT ===
+
=== TSEC_FALCON_PTIMER0 ===
Returns the result of the last command from [[#FALCON_IMCTL|FALCON_IMCTL]].
 
 
 
=== FALCON_TRACEIDX ===
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-7
+
| 0-31
| Index of where to start tracing from
+
| TSEC_FALCON_PTIMER0_VAL
|-
 
| 16-23
 
| Maximum valid index
 
|-
 
| 24-31
 
| Number of trace reads remaining
 
 
|}
 
|}
  
Controls the index for tracing with [[#FALCON_TRACEPC|FALCON_TRACEPC]].
+
=== TSEC_FALCON_PTIMER1 ===
 
 
=== FALCON_TRACEPC ===
 
Returns the PC of the last call or branch executed.
 
 
 
=== FALCON_IMEMC ===
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 2-7
+
| 0-31
| Offset in IMEM block to read/write
+
| TSEC_FALCON_PTIMER1_VAL
|-
 
| 8-15
 
| IMEM block to read/write
 
|-
 
| 24
 
| Write auto-increment
 
|-
 
| 25
 
| Read auto-increment
 
|-
 
| 28
 
| Mark uploaded code as secret
 
|-
 
| 29
 
| Secret code upload lockdown status (read-only)
 
|-
 
| 30
 
| Secret code upload failure status (read-only)
 
|-
 
| 31
 
| Secret code upload reset scrubber status (read-only)
 
 
|}
 
|}
  
Used for configuring access to Falcon's IMEM.
+
=== TSEC_FALCON_WDTMRVAL ===
 
 
=== FALCON_IMEMD ===
 
Returns or takes the value for an IMEM read/write operation.
 
 
 
=== FALCON_IMEMT ===
 
Returns or takes the virtual page index for an IMEM read/write operation.
 
 
 
=== FALCON_DMEMC0 ===
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 2-7
+
| 0-31
| Offset in DMEM block to read/write
+
| TSEC_FALCON_WDTMRVAL_VAL
 +
|}
 +
 
 +
=== TSEC_FALCON_WDTMRCTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 8-15
+
| 0
| DMEM block to read/write
+
| TSEC_FALCON_WDTMRCTL_WDTMREN
 +
|}
 +
 
 +
=== TSEC_FALCON_IRQDEST2 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 24
+
| 0
| Write auto-increment
+
| TSEC_FALCON_IRQDEST2_HOST_DMA
 
|-
 
|-
| 25
+
| 16
| Read auto-increment
+
| TSEC_FALCON_IRQDEST2_TARGET_DMA
 
|}
 
|}
  
Used for configuring access to Falcon's DMEM.
+
Used for routing Falcon's IRQs.
 +
 
 +
=== TSEC_FALCON_MAILBOX0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_FALCON_MAILBOX0_DATA
 +
|}
  
=== FALCON_DMEMD0 ===
+
Scratch register for reading/writing data to Falcon.
Returns or takes the value for a DMEM read/write operation.
 
  
=== FALCON_ICD_CMD ===
+
=== TSEC_FALCON_MAILBOX1 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-31
| FALCON_ICD_CMD_OPC
+
| TSEC_FALCON_MAILBOX1_DATA
  0x00: STOP
+
|}
  0x01: RUN (run from PC)
+
 
0x02: JRUN (run from address)
+
Scratch register for reading/writing data to Falcon.
0x03: RUNB (run from PC)
+
 
0x04: JRUNB (run from address)
+
=== TSEC_FALCON_ITFEN ===
0x05: STEP (step from PC)
+
{| class="wikitable" border="1"
0x06: JSTEP (step from address)
+
! Bits
0x07: EMASK (set exception mask)
+
! Description
0x08: RREG (read register)
+
|-
0x09: WREG (write register)
+
| 0
0x0A: RDM (read data memory)
+
| TSEC_FALCON_ITFEN_CTXEN
0x0B: WDM (write data memory)
+
|-
0x0C: RCM (read code memory)
+
| 1
0x0D: WCM (write code memory)
+
| TSEC_FALCON_ITFEN_MTHDEN
  0x0E: RSTAT (read status)
+
|}
  0x0F: SBU
+
 
 +
Used for enabling/disabling Falcon interfaces.
 +
 
 +
=== TSEC_FALCON_IDLESTATE ===
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 
|-
 
|-
| 6-7
+
| 0
| FALCON_ICD_CMD_SZ
+
| TSEC_FALCON_IDLESTATE_FALCON_BUSY
0x00: B (byte
 
0x01: HW (half word)
 
0x02: W (word)
 
 
|-
 
|-
| 8-12
+
| 1-15
| FALCON_ICD_CMD_IDX
+
| TSEC_FALCON_IDLESTATE_EXT_BUSY
0x00: REG0 | RSTAT0 | WB0
+
|}
0x01: REG1 | RSTAT1 | WB1
+
 
0x02: REG2 | RSTAT2 | WB2
+
Used for detecting if Falcon is busy or not.
0x03: REG3 | RSTAT3 | WB3
+
 
0x04: REG4 | RSTAT4
+
=== TSEC_FALCON_CURCTX ===
0x05: REG5 | RSTAT5
+
{| class="wikitable" border="1"
0x06: REG6
+
! Bits
0x07: REG7
+
! Description
0x08: REG8
 
0x09: REG9
 
0x0A: REG10
 
0x0B: REG11
 
0x0C: REG12
 
0x0D: REG13
 
0x0E: REG14
 
0x0F: REG15
 
0x10: IV0
 
0x11: IV1
 
0x12: UNDEFINED
 
0x13: EV
 
0x14: SP
 
0x15: PC
 
0x16: IMB
 
0x17: DMB
 
0x18: CSW
 
0x19: CCR
 
0x1A: SEC
 
  0x1B: CTX
 
  0x1C: EXCI
 
 
|-
 
|-
| 14
+
| 0-27
| FALCON_ICD_CMD_ERROR
+
| TSEC_FALCON_CURCTX_CTXPTR
 
|-
 
|-
| 15
+
| 28-29
| FALCON_ICD_CMD_RDVLD
+
| TSEC_FALCON_CURCTX_CTXTGT
 
|-
 
|-
| 16-31
+
| 30
| FALCON_ICD_CMD_PARM
+
| TSEC_FALCON_CURCTX_CTXVLD
0x0001: EMASK_TRAP0
+
|}
0x0002: EMASK_TRAP1
+
 
0x0004: EMASK_TRAP2
+
=== TSEC_FALCON_NXTCTX ===
0x0008: EMASK_TRAP3
+
{| class="wikitable" border="1"
  0x0010: EMASK_EXC_UNIMP
+
! Bits
  0x0020: EMASK_EXC_IMISS
+
! Description
0x0040: EMASK_EXC_IMHIT
+
|-
0x0080: EMASK_EXC_IBREAK
+
| 0-27
0x0100: EMASK_IV0
+
| TSEC_FALCON_NXTCTX_CTXPTR
0x0200: EMASK_IV1
+
|-
0x0400: EMASK_IV2
+
| 28-29
0x0800: EMASK_EXT0
+
| TSEC_FALCON_NXTCTX_CTXTGT
0x1000: EMASK_EXT1
+
|-
0x2000: EMASK_EXT2
+
| 30
0x4000: EMASK_EXT3
+
| TSEC_FALCON_NXTCTX_CTXVLD
0x8000: EMASK_EXT4
 
 
|}
 
|}
  
Used for sending commands to the Falcon's in-chip debugger.
+
=== TSEC_FALCON_CTXACK ===
 
 
=== FALCON_ICD_ADDR ===
 
Takes the target address for the Falcon's in-chip debugger.
 
 
 
=== FALCON_ICD_WDATA ===
 
Takes the data for writing using the Falcon's in-chip debugger.
 
 
 
=== FALCON_ICD_RDATA ===
 
Returns the data read using the Falcon's in-chip debugger.
 
 
 
When reading from an internal status register (STAT), the following applies:
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,791: Line 1,901:
 
|-
 
|-
 
| 0
 
| 0
| RSTAT0_MEM_STALL
+
| TSEC_FALCON_CTXACK_SAVE_ACK
 
|-
 
|-
 
| 1
 
| 1
| RSTAT0_DMA_STALL
+
| TSEC_FALCON_CTXACK_REST_ACK
 +
|}
 +
 
 +
=== TSEC_FALCON_FHSTATE ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 2
+
| 0
| RSTAT0_FENCE_STALL
+
| TSEC_FALCON_FHSTATE_FALCON_HALTED
 
|-
 
|-
| 3
+
| 1-15
| RSTAT0_DIV_STALL
+
| TSEC_FALCON_FHSTATE_EXT_HALTED
 
|-
 
|-
| 4
+
| 16
| RSTAT0_DMA_STALL_DMAQ
+
| TSEC_FALCON_FHSTATE_ENGINE_FAULTED
 
|-
 
|-
| 5
+
| 17
| RSTAT0_DMA_STALL_DMWAITING
+
| TSEC_FALCON_FHSTATE_STALL_REQ
 +
|}
 +
 
 +
=== TSEC_FALCON_PRIVSTATE ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 6
+
| 0
| RSTAT0_DMA_STALL_IMWAITING
+
| TSEC_FALCON_PRIVSTATE_PRIV
 +
|}
 +
 
 +
=== TSEC_FALCON_MTHDDATA ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 7
+
| 0-31
| RSTAT0_ANY_STALL
+
| TSEC_FALCON_MTHDDATA_DATA
 +
|}
 +
 
 +
=== TSEC_FALCON_MTHDID ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 8
+
| 0-11
| RSTAT0_SBFULL_STALL
+
| TSEC_FALCON_MTHDID_ID
 
|-
 
|-
| 9
+
| 12-14
| RSTAT0_SBHIT_STALL
+
| TSEC_FALCON_MTHDID_SUBCH
 
|-
 
|-
| 10
+
| 15
| RSTAT0_FLOW_STALL
+
| TSEC_FALCON_MTHDID_PRIV
 
|-
 
|-
| 11
+
| 16
| RSTAT0_SP_STALL
+
| TSEC_FALCON_MTHDID_WPEND
 +
|}
 +
 
 +
=== TSEC_FALCON_MTHDWDAT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 12
+
| 0-31
| RSTAT0_BL_STALL
+
| TSEC_FALCON_MTHDWDAT_DATA
 +
|}
 +
 
 +
=== TSEC_FALCON_MTHDCOUNT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 13
+
| 0-15
| RSTAT0_IPND_STALL
+
| TSEC_FALCON_MTHDCOUNT_COUNT
 +
|}
 +
 
 +
=== TSEC_FALCON_MTHDPOP ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 14
+
| 0
| RSTAT0_LDSTQ_STALL
+
| TSEC_FALCON_MTHDPOP_POP
 +
|}
 +
 
 +
=== TSEC_FALCON_MTHDRAMSZ ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 16
+
| 0-15
| RSTAT0_NOINSTR_STALL
+
| TSEC_FALCON_MTHDRAMSZ_RAMSZ
|-
+
|}
| 20
+
 
| RSTAT0_HALTSTOP_FLUSH
+
=== TSEC_FALCON_SFTRESET ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 21
+
| 0
| RSTAT0_AFILL_FLUSH
+
| TSEC_FALCON_SFTRESET_EXT
 +
|}
 +
 
 +
=== TSEC_FALCON_OS ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 22
+
| 0-31
| RSTAT0_EXC_FLUSH
+
| TSEC_FALCON_OS_VERSION
|-
+
|}
| 23-25
+
 
| RSTAT0_IRQ_FLUSH
+
=== TSEC_FALCON_RM ===
|-
+
{| class="wikitable" border="1"
| 28
+
!  Bits
| RSTAT0_VALIDRD
+
!  Description
|-
 
| 29
 
| RSTAT0_WAITING
 
 
|-
 
|-
| 30
+
| 0-31
| RSTAT0_HALTED
+
| TSEC_FALCON_RM_CONFIG
|-
 
| 31
 
| RSTAT0_MTHD_FULL
 
 
|}
 
|}
 +
 +
=== TSEC_FALCON_SOFT_PM ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-5
| RSTAT1_WB_ALLOC
+
| TSEC_FALCON_SOFT_PM_PROBE
 
|-
 
|-
| 4-7
+
| 16
| RSTAT1_WB_VALID
+
| TSEC_FALCON_SOFT_PM_TRIGGER_END
 
|-
 
|-
| 8-9
+
| 17
| RSTAT1_WB0_SZ
+
| TSEC_FALCON_SOFT_PM_TRIGGER_START
 +
|}
 +
 
 +
=== TSEC_FALCON_SOFT_MODE ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 10-11
+
| 0-5
| RSTAT1_WB1_SZ
+
| TSEC_FALCON_SOFT_MODE_PROBE
|-
 
| 12-13
 
| RSTAT1_WB2_SZ
 
|-
 
| 14-15
 
| RSTAT1_WB3_SZ
 
|-
 
| 16-19
 
| RSTAT1_WB0_IDX
 
|-
 
| 20-23
 
| RSTAT1_WB1_IDX
 
|-
 
| 24-27
 
| RSTAT1_WB2_IDX
 
|-
 
| 28-31
 
| RSTAT1_WB3_IDX
 
 
|}
 
|}
 +
 +
=== TSEC_FALCON_DEBUG1 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-15
| RSTAT2_DMAQ_NUM
+
| TSEC_FALCON_DEBUG1_MTHD_DRAIN_TIME
 +
|-
 +
| 16
 +
| TSEC_FALCON_DEBUG1_CTXSW_MODE
 
|-
 
|-
| 4
+
| 17
| RSTAT2_DMA_ENABLE
+
| TSEC_FALCON_DEBUG1_TRACE_FORMAT
 +
|}
 +
 
 +
=== TSEC_FALCON_DEBUGINFO ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 5-7
+
| 0-31
| RSTAT2_LDSTQ_NUM
+
| TSEC_FALCON_DEBUGINFO_DATA
 +
|}
 +
 
 +
Used for UCODE self revocation. This register takes the base address of the GSC carveout shifted right by 8.
 +
 
 +
[6.0.0+] [[NV_services|nvservices]] sets this to 0x8005FF00 >> 8 (physical DRAM address inside the GPU UCODE carveout) before starting the nvhost_tsec firmware.
 +
 
 +
=== TSEC_FALCON_IBRKPT1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 16-19
+
| 0-23
| RSTAT2_EM_BUSY
+
| TSEC_FALCON_IBRKPT1_PC
 
|-
 
|-
| 20-23
+
| 29
| RSTAT2_EM_ACKED
+
| TSEC_FALCON_IBRKPT1_SUPPRESS
 
|-
 
|-
| 24-27
+
| 30
| RSTAT2_EM_ISWR
+
| TSEC_FALCON_IBRKPT1_SKIP
 
|-
 
|-
| 28-31
+
| 31
| RSTAT2_EM_DVLD
+
| TSEC_FALCON_IBRKPT1_EN
 
|}
 
|}
 +
 +
=== TSEC_FALCON_IBRKPT2 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-23
| RSTAT3_MTHD_IDLE
+
| TSEC_FALCON_IBRKPT2_PC
 +
|-
 +
| 29
 +
| TSEC_FALCON_IBRKPT2_SUPPRESS
 +
|-
 +
| 30
 +
| TSEC_FALCON_IBRKPT2_SKIP
 +
|-
 +
| 31
 +
| TSEC_FALCON_IBRKPT2_EN
 +
|}
 +
 
 +
=== TSEC_FALCON_CGCTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_FALCON_CGCTL_CG_OVERRIDE
 +
|}
 +
 
 +
=== TSEC_FALCON_ENGCTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_FALCON_ENGCTL_INV_CONTEXT
 
|-
 
|-
 
| 1
 
| 1
| RSTAT3_CTXSW_IDLE
+
| TSEC_FALCON_ENGCTL_SET_STALLREQ
 
|-
 
|-
 
| 2
 
| 2
| RSTAT3_DMA_IDLE
+
| TSEC_FALCON_ENGCTL_CLR_STALLREQ
 
|-
 
|-
 
| 3
 
| 3
| RSTAT3_SCP_IDLE
+
| TSEC_FALCON_ENGCTL_SWITCH_CONTEXT
 
|-
 
|-
| 4
+
| 8
| RSTAT3_LDST_IDLE
+
| TSEC_FALCON_ENGCTL_STALLREQ
 
|-
 
|-
| 5
+
| 9
| RSTAT3_SBWB_EMPTY
+
| TSEC_FALCON_ENGCTL_STALLACK
 +
|}
 +
 
 +
=== TSEC_FALCON_PMM ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 6-8
+
| 0-4
| RSTAT3_CSWIE
+
| TSEC_FALCON_PMM_FALCON_STALL_SEL
 +
0x00: ANY
 +
0x01: CODE
 +
0x02: DMAQ
 +
0x03: DMFENCE
 +
0x04: DMWAIT
 +
0x05: IMWAIT
 +
0x06: IPND
 +
0x07: LDSTQ
 +
0x08: SB
 +
0x09: ANY_SC
 +
0x0A: CODE_SC
 +
0x0B: DMAQ_SC
 +
0x0C: DMFENCE_SC
 +
0x0D: DMWAIT_SC
 +
0x0E: IMWAIT_SC
 +
0x0F: IPND_SC
 +
0x10: LDSTQ_SC
 +
0x11: SB_SC
 
|-
 
|-
| 10
+
| 5-7
| RSTAT3_CSWE
+
| TSEC_FALCON_PMM_FALCON_IDLE_SEL
 +
0x00: WAITING
 +
0x01: ENG_IDLE
 +
0x02: MTHD_FULL
 +
0x03: WAITING_SC
 +
0x04: ENG_IDLE_SC
 +
0x05: MTHD_FULL_SC
 
|-
 
|-
| 12-14
+
| 8-11
| RSTAT3_CTXSW_STATE
+
| TSEC_FALCON_PMM_FALCON_SOFTPM0_SEL
  0x00: IDLE
+
  0x00: 0
  0x01: SM_CHECK
+
  0x01: 1
  0x02: SM_SAVE
+
  0x02: 2
  0x03: SM_SAVE_WAIT
+
  0x03: 3
  0x04: SM_BLK_BIND
+
  0x04: 4
  0x05: SM_RESET
+
  0x05: 5
  0x06: SM_RESETWAIT
+
  0x06: 0_SC
  0x07: SM_ACK
+
  0x07: 1_SC
 +
0x08: 2_SC
 +
0x09: 3_SC
 +
0x0A: 4_SC
 +
0x0B: 5_SC
 
|-
 
|-
| 15
+
| 12-15
| RSTAT3_CTXSW_PEND
+
| TSEC_FALCON_PMM_FALCON_SOFTPM1_SEL
 +
0x00: 0
 
|-
 
|-
| 17
+
| 17-19
| RSTAT3_DMA_FBREQ_IDLE
+
| TSEC_FALCON_PMM_TFBIF_DSTAT_SEL
 +
0x00: 1KTRANSFER
 +
0x01: RREQ
 +
0x02: WREQ
 +
0x03: TWREQ
 +
0x04: 1KTRANSFER_SC
 +
0x05: RREQ_SC
 +
0x06: WREQ_SC
 +
0x07: TWREQ_SC
 
|-
 
|-
| 18
+
| 20-23
| RSTAT3_DMA_ACKQ_EMPTY
+
| TSEC_FALCON_PMM_TFBIF_STALL0_SEL
 +
0x00: RDATQ_FULL
 +
0x01: RACKQ_FULL
 +
0x02: WREQQ_FULL
 +
0x03: WDATQ_FULL
 +
0x04: WACKQ_FULL
 +
0x05: MREQQ_FULL
 +
0x06: RREQ_PEND
 +
0x07: WREQ_PEND
 +
0x08: RDATQ_FULL_SC
 +
0x09: RACKQ_FULL_SC
 +
0x0A: WREQQ_FULL_SC
 +
0x0B: WDATQ_FULL_SC
 +
0x0C: WACKQ_FULL_SC
 +
0x0D: MREQQ_FULL_SC
 +
0x0E: RREQ_PEND_SC
 +
0x0F: WREQ_PEND_SC
 
|-
 
|-
| 19
+
| 24-27
| RSTAT3_DMA_RDQ_EMPTY
+
| TSEC_FALCON_PMM_TFBIF_STALL1_SEL
 +
0x00: RDATQ_FULL
 
|-
 
|-
| 20
+
| 28-31
| RSTAT3_DMA_WR_BUSY
+
| TSEC_FALCON_PMM_TFBIF_STALL2_SEL
 +
0x00: RDATQ_FULL
 +
|}
 +
 
 +
=== TSEC_FALCON_ADDR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 21
+
| 0-5
| RSTAT3_DMA_RD_BUSY
+
| TSEC_FALCON_ADDR_LSB
 
|-
 
|-
| 22
+
| 6-11
| RSTAT3_LDST_XT_BUSY
+
| TSEC_FALCON_ADDR_MSB
 +
|}
 +
 
 +
=== TSEC_FALCON_IBRKPT3 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-23
 +
| TSEC_FALCON_IBRKPT3_PC
 +
|-
 +
| 29
 +
| TSEC_FALCON_IBRKPT3_SUPPRESS
 
|-
 
|-
| 23
+
| 30
| RSTAT3_LDST_XT_BLOCK
+
| TSEC_FALCON_IBRKPT3_SKIP
 
|-
 
|-
| 24
+
| 31
| RSTAT3_ENG_IDLE
+
| TSEC_FALCON_IBRKPT3_EN
 
|}
 
|}
 +
 +
=== TSEC_FALCON_IBRKPT4 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-1
+
| 0-23
| RSTAT4_ICD_STATE
+
| TSEC_FALCON_IBRKPT4_PC
0x00: NORMAL
 
0x01: WAIT_ISSUE_CLEAR
 
0x02: WAIT_EXLDQ_CLEAR
 
0x03: FULL_DBG_MODE
 
 
|-
 
|-
| 2-3
+
| 29
| RSTAT4_ICD_MODE
+
| TSEC_FALCON_IBRKPT4_SUPPRESS
0x00: SUPPRESSICD
 
0x01: ENTERICD_IBRK
 
0x02: ENTERICD_STEP
 
 
|-
 
|-
| 16
+
| 30
| RSTAT4_ICD_EMASK_TRAP0
+
| TSEC_FALCON_IBRKPT4_SKIP
 
|-
 
|-
| 17
+
| 31
| RSTAT4_ICD_EMASK_TRAP1
+
| TSEC_FALCON_IBRKPT4_EN
 +
|}
 +
 
 +
=== TSEC_FALCON_IBRKPT5 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 18
+
| 0-23
| RSTAT4_ICD_EMASK_TRAP2
+
| TSEC_FALCON_IBRKPT5_PC
 
|-
 
|-
| 19
+
| 29
| RSTAT4_ICD_EMASK_TRAP3
+
| TSEC_FALCON_IBRKPT5_SUPPRESS
 
|-
 
|-
| 20
+
| 30
| RSTAT4_ICD_EMASK_EXC_UNIMP
+
| TSEC_FALCON_IBRKPT5_SKIP
 
|-
 
|-
| 21
+
| 31
| RSTAT4_ICD_EMASK_EXC_IMISS
+
| TSEC_FALCON_IBRKPT5_EN
 +
|}
 +
 
 +
=== TSEC_FALCON_EXCI ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 22
+
| 0-19
| RSTAT4_ICD_EMASK_EXC_IMHIT
+
| TSEC_FALCON_EXCI_EXPC
 
|-
 
|-
| 23
+
| 20-23
| RSTAT4_ICD_EMASK_EXC_IBREAK
+
| TSEC_FALCON_EXCI_EXCAUSE
 +
0x00: TRAP0
 +
0x01: TRAP1
 +
0x02: TRAP2
 +
0x03: TRAP3
 +
0x08: ILL_INS (invalid opcode)
 +
0x09: INV_INS (authentication entry)
 +
0x0A: MISS_INS (page miss)
 +
0x0B: DHIT_INS (page multiple hit)
 +
0x0F: BRKPT_INS (breakpoint hit)
 +
|}
 +
 
 +
Contains information about raised exceptions.
 +
 
 +
=== TSEC_FALCON_SVEC_SPR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 24
+
| 18
| RSTAT4_ICD_EMASK_IV0
+
| TSEC_FALCON_SVEC_SPR_SIGPASS
 +
|}
 +
 
 +
=== TSEC_FALCON_RSTAT0 ===
 +
Mirror of the [[#TSEC_FALCON_ICD_RDATA|ICD status register 0]].
 +
 
 +
=== TSEC_FALCON_RSTAT3 ===
 +
Mirror of the [[#TSEC_FALCON_ICD_RDATA|ICD status register 3]].
 +
 
 +
=== TSEC_FALCON_CPUCTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 25
+
| 0
| RSTAT4_ICD_EMASK_IV1
+
| TSEC_FALCON_CPUCTL_IINVAL
 
|-
 
|-
| 26
+
| 1
| RSTAT4_ICD_EMASK_IV2
+
| TSEC_FALCON_CPUCTL_STARTCPU
 
|-
 
|-
| 27
+
| 2
| RSTAT4_ICD_EMASK_EXT0
+
| TSEC_FALCON_CPUCTL_SRESET
 
|-
 
|-
| 28
+
| 3
| RSTAT4_ICD_EMASK_EXT1
+
| TSEC_FALCON_CPUCTL_HRESET
 
|-
 
|-
| 29
+
| 4
| RSTAT4_ICD_EMASK_EXT2
+
| TSEC_FALCON_CPUCTL_HALTED
 
|-
 
|-
| 30
+
| 5
| RSTAT4_ICD_EMASK_EXT3
+
| TSEC_FALCON_CPUCTL_STOPPED
 
|-
 
|-
| 31
+
| 6
| RSTAT4_ICD_EMASK_EXT4
+
| TSEC_FALCON_CPUCTL_ALIAS_EN
 
|}
 
|}
 +
 +
Used for signaling the Falcon CPU.
 +
 +
=== TSEC_FALCON_BOOTVEC ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-7
+
| 0-31
| RSTAT5_LRU_STATE
+
| TSEC_FALCON_BOOTVEC_VEC
 
|}
 
|}
  
=== FALCON_SCTL ===
+
Takes the Falcon's boot vector address.
 +
 
 +
=== TSEC_FALCON_HWCFG ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-1
+
| 0-8
| FALCON_SCTL_SEC_MODE
+
| TSEC_FALCON_HWCFG_IMEM_SIZE
0: Non-secure
 
1: Light Secure
 
2: Heavy Secure
 
 
|-
 
|-
| 4-5
+
| 9-17
| FALCON_SCTL_OLD_SEC_MODE
+
| TSEC_FALCON_HWCFG_DMEM_SIZE
0: Non-secure
 
1: Light Secure
 
2: Heavy Secure
 
 
|-
 
|-
| 12-13
+
| 18-26
| Unknown
+
| TSEC_FALCON_HWCFG_METHODFIFO_DEPTH
 
|-
 
|-
| 14
+
| 27-31
| Initialize the transition to LS mode
+
| TSEC_FALCON_HWCFG_DMAQUEUE_DEPTH
 
|}
 
|}
  
=== FALCON_SCTL_STAT ===
+
=== TSEC_FALCON_DMACTL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 31
+
| 0
| Set on memory protection violation
+
| TSEC_FALCON_DMACTL_REQUIRE_CTX
|}
+
|-
 
+
| 1
=== FALCON_SPROT_IMEM ===
+
| TSEC_FALCON_DMACTL_DMEM_SCRUBBING
{| class="wikitable" border="1"
+
|-
!  Bits
+
| 2
!  Description
+
| TSEC_FALCON_DMACTL_IMEM_SCRUBBING
 
|-
 
|-
| 0-3
+
| 3-6
| Read access level
+
| TSEC_FALCON_DMACTL_DMAQ_NUM
 
|-
 
|-
| 4-7
+
| 7
| Write access level
+
| TSEC_FALCON_DMACTL_SECURE_STAT
 
|}
 
|}
  
Controls accesses to Falcon IMEM.
+
Used for configuring the Falcon's DMA engine.
  
=== FALCON_SPROT_DMEM ===
+
=== TSEC_FALCON_DMATRFBASE ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-31
| Read access level
+
| TSEC_FALCON_DMATRFBASE_BASE
|-
 
| 4-7
 
| Write access level
 
 
|}
 
|}
  
Controls accesses to Falcon DMEM.
+
Base address of the external memory buffer, shifted right by 8.
 +
 
 +
The current transfer address is calculated by adding [[#TSEC_FALCON_DMATRFFBOFFS|TSEC_FALCON_DMATRFFBOFFS]] to the base.
  
=== FALCON_SPROT_CPUCTL ===
+
=== TSEC_FALCON_DMATRFMOFFS ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-15
| Read access level
+
| TSEC_FALCON_DMATRFMOFFS_OFFS
|-
 
| 4-7
 
| Write access level
 
 
|}
 
|}
  
Controls accesses to the [[#FALCON_CPUCTL|FALCON_CPUCTL]] register.
+
For transfers to DMEM: the destination address.
 +
For transfers to IMEM: the destination virtual IMEM page.
  
=== FALCON_SPROT_MISC ===
+
=== TSEC_FALCON_DMATRFCMD ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0
| Read access level
+
| TSEC_FALCON_DMATRFCMD_FULL
 +
|-
 +
| 1
 +
| TSEC_FALCON_DMATRFCMD_IDLE
 +
|-
 +
| 2-3
 +
| TSEC_FALCON_DMATRFCMD_SEC
 +
|-
 +
| 4
 +
| TSEC_FALCON_DMATRFCMD_IMEM
 +
|-
 +
| 5
 +
| TSEC_FALCON_DMATRFCMD_WRITE
 +
|-
 +
| 8-10
 +
| TSEC_FALCON_DMATRFCMD_SIZE
 
|-
 
|-
| 4-7
+
| 12-14
| Write access level
+
| TSEC_FALCON_DMATRFCMD_CTXDMA
 
|}
 
|}
  
Controls accesses to the following registers:
+
Used for configuring DMA transfers.
* FALCON_PRIVSTATE
 
* FALCON_SFTRESET
 
* FALCON_ADDR
 
* [[#FALCON_DMACTL|FALCON_DMACTL]]
 
* [[#FALCON_IMCTL|FALCON_IMCTL]]
 
* [[#FALCON_IMSTAT|FALCON_IMSTAT]]
 
* FALCON_UNK_250
 
* FALCON_UNK_2E0
 
  
=== FALCON_SPROT_IRQ ===
+
=== TSEC_FALCON_DMATRFFBOFFS ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-31
| Read access level
+
| TSEC_FALCON_DMATRFFBOFFS_OFFS
|-
 
| 4-7
 
| Write access level
 
 
|}
 
|}
  
Controls accesses to the following registers:
+
For transfers to IMEM: the destination physical IMEM page.
* [[#FALCON_IRQMODE|FALCON_IRQMODE]]
 
* [[#FALCON_IRQMSET|FALCON_IRQMSET]]
 
* [[#FALCON_IRQMCLR|FALCON_IRQMCLR]]
 
* [[#FALCON_IRQDEST|FALCON_IRQDEST]]
 
* FALCON_GPTMRINT
 
* FALCON_GPTMRVAL
 
* FALCON_GPTMRCTL
 
* FALCON_UNK_3C
 
* FALCON_UNK_E0
 
  
=== FALCON_SPROT_MTHD ===
+
=== TSEC_FALCON_DMAPOLL_FB ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0
| Read access level
+
| TSEC_FALCON_DMAPOLL_FB_FENCE_ACTIVE
 
|-
 
|-
| 4-7
+
| 1
| Write access level
+
| TSEC_FALCON_DMAPOLL_FB_DMA_ACTIVE
 +
|-
 +
| 4
 +
| TSEC_FALCON_DMAPOLL_FB_CFG_R_FENCE
 +
|-
 +
| 5
 +
| TSEC_FALCON_DMAPOLL_FB_CFG_W_FENCE
 +
|-
 +
| 16-23
 +
| TSEC_FALCON_DMAPOLL_FB_WCOUNT
 +
|-
 +
| 24-31
 +
| TSEC_FALCON_DMAPOLL_FB_RCOUNT
 
|}
 
|}
  
Controls accesses to the following registers:
+
Contains the status of a DMA transfer between the Falcon and external memory.
* [[#FALCON_ITFEN|FALCON_ITFEN]]
 
* FALCON_CURCTX
 
* FALCON_NXTCTX
 
* FALCON_CTXACK
 
* FALCON_MTHDDATA
 
* FALCON_MTHDID
 
* FALCON_MTHDWDAT
 
* FALCON_MTHDCOUNT
 
* FALCON_MTHDPOP
 
* FALCON_MTHDRAMSZ
 
* [[#FALCON_DEBUG1|FALCON_DEBUG1]]
 
  
=== FALCON_SPROT_SCTL ===
+
=== TSEC_FALCON_DMAPOLL_CP ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0
| Read access level
+
| TSEC_FALCON_DMAPOLL_CP_FENCE_ACTIVE
 +
|-
 +
| 1
 +
| TSEC_FALCON_DMAPOLL_CP_DMA_ACTIVE
 +
|-
 +
| 4
 +
| TSEC_FALCON_DMAPOLL_CP_CFG_R_FENCE
 +
|-
 +
| 5
 +
| TSEC_FALCON_DMAPOLL_CP_CFG_W_FENCE
 +
|-
 +
| 16-23
 +
| TSEC_FALCON_DMAPOLL_CP_WCOUNT
 
|-
 
|-
| 4-7
+
| 24-31
| Write access level
+
| TSEC_FALCON_DMAPOLL_CP_RCOUNT
 
|}
 
|}
  
Controls accesses to the [[#FALCON_SCTL|FALCON_SCTL]] register.
+
Contains the status of a DMA transfer between the Falcon and the SCP.
  
=== FALCON_SPROT_WDTMR ===
+
=== TSEC_FALCON_HWCFG1 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 2,225: Line 2,546:
 
|-
 
|-
 
| 0-3
 
| 0-3
| Read access level
+
| TSEC_FALCON_HWCFG1_CORE_REV
 +
|-
 +
| 4-5
 +
| TSEC_FALCON_HWCFG1_SECURITY_MODEL
 +
|-
 +
| 6-7
 +
| TSEC_FALCON_HWCFG1_CORE_REV_SUBVERSION
 
|-
 
|-
| 4-7
+
| 8-11
| Write access level
+
| TSEC_FALCON_HWCFG1_IMEM_PORTS
|}
+
|-
 
+
| 12-15
Controls accesses to the following registers:
+
| TSEC_FALCON_HWCFG1_DMEM_PORTS
* FALCON_WDTMRVAL
+
|-
* FALCON_WDTMRCTL
+
| 16-20
 +
| TSEC_FALCON_HWCFG1_TAG_WIDTH
 +
|-
 +
| 27
 +
| TSEC_FALCON_HWCFG1_DBG_PRIV_BUS
 +
|-
 +
| 28
 +
| TSEC_FALCON_HWCFG1_CSB_SIZE_16M
 +
|-
 +
| 29
 +
| TSEC_FALCON_HWCFG1_PRIV_DIRECT
 +
|-
 +
| 30
 +
| TSEC_FALCON_HWCFG1_DMEM_APERTURES
 +
|-
 +
| 31
 +
| TSEC_FALCON_HWCFG1_IMEM_AUTOFILL
 +
|}
  
=== TSEC_SCP_CTL0 ===
+
=== TSEC_FALCON_CPUCTL_ALIAS ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 20
+
| 1
| Enable TSEC_SCP_INSN_STAT register
+
| TSEC_FALCON_CPUCTL_ALIAS_STARTCPU
 
|}
 
|}
  
=== TSEC_SCP_CTL1 ===
+
=== TSEC_FALCON_STACKCFG ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 11
+
| 0-15
| Enable TRNG testing mode
+
| TSEC_FALCON_STACKCFG_BOTTOM
 
|-
 
|-
| 12
+
| 31
| Enable the TRNG
+
| TSEC_FALCON_STACKCFG_SPEXC
 
|}
 
|}
  
=== TSEC_SCP_CTL_STAT ===
+
=== TSEC_FALCON_IMCTL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 20
+
| 0-23
| TSEC_SCP_CTL_STAT_DEBUG_MODE
+
| TSEC_FALCON_IMCTL_ADDR_BLK
 +
|-
 +
| 24-26
 +
| TSEC_FALCON_IMCTL_CMD
 +
0x00: NOP
 +
0x01: IMINV (ITLB)
 +
0x02: IMBLK (PTLB)
 +
0x03: IMTAG (VTLB)
 +
0x04: IMTAG_SETVLD
 
|}
 
|}
  
=== TSEC_SCP_CTL_LOCK ===
+
Controls the Falcon TLB.
 +
 
 +
=== TSEC_FALCON_IMSTAT ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-31
| Disable reads for the SCP and TRNG register blocks
+
| TSEC_FALCON_IMSTAT_VAL
 +
|}
 +
 
 +
Returns the result of the last command from [[#TSEC_FALCON_IMCTL|TSEC_FALCON_IMCTL]].
 +
 
 +
=== TSEC_FALCON_TRACEIDX ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 1
+
| 0-7
| Disable reads for the TFBIF register block
+
| TSEC_FALCON_TRACEIDX_IDX
 
|-
 
|-
| 2
+
| 16-23
| Disable reads for the DMA register block
+
| TSEC_FALCON_TRACEIDX_MAXIDX
 
|-
 
|-
| 3
+
| 24-31
| Disable reads for the TEGRA register block
+
| TSEC_FALCON_TRACEIDX_CNT
|-
 
| 4
 
| Disable writes for the SCP and TRNG register blocks
 
|-
 
| 5
 
| Disable writes for the TFBIF register block
 
|-
 
| 6
 
| Disable writes for the DMA register block
 
|-
 
| 7
 
| Disable writes for the TEGRA register block
 
 
|}
 
|}
  
Locks accesses to sub-engines and can only be cleared in Heavy Secure mode.
+
Controls the index for tracing with [[#TSEC_FALCON_TRACEPC|TSEC_FALCON_TRACEPC]].
  
=== TSEC_SCP_CTL_PKEY ===
+
=== TSEC_FALCON_TRACEPC ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-23
| TSEC_SCP_CTL_PKEY_REQUEST_RELOAD
+
| TSEC_FALCON_TRACEPC_PC
|-
 
| 1
 
| TSEC_SCP_CTL_PKEY_LOADED
 
 
|}
 
|}
  
=== TSEC_SCP_SEQ_CTL ===
+
Returns the PC of the last call or branch executed.
 +
 
 +
=== TSEC_FALCON_IMFILLRNG0 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-15
| Sequence's instruction index
+
| TSEC_FALCON_IMFILLRNG0_TAG_LO
 
|-
 
|-
| 4-7
+
| 16-31
| Target and control flags
+
| TSEC_FALCON_IMFILLRNG0_TAG_HI
|-
 
| 8-11
 
| Sequence's size
 
 
|}
 
|}
  
Controls the last crypto sequence (cs0 or cs1) created.
+
=== TSEC_FALCON_IMFILLRNG1 ===
 
 
=== TSEC_SCP_SEQ_VAL ===
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-15
| Sequence instruction's first operand
+
| TSEC_FALCON_IMFILLRNG1_TAG_LO
 
|-
 
|-
| 4-9
+
| 16-31
| Sequence instruction's second operand
+
| TSEC_FALCON_IMFILLRNG1_TAG_HI
 +
|}
 +
 
 +
=== TSEC_FALCON_IMFILLCTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 10-14
+
| 0-7
| Sequence instruction's opcode
+
| TSEC_FALCON_IMFILLCTL_NBLOCKS
 
|}
 
|}
  
Contains information on the last crypto sequence (cs0 or cs1) created.
+
=== TSEC_FALCON_IMCTL_DEBUG ===
 
 
=== TSEC_SCP_SEQ_STAT ===
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-23
| Set if crypto sequence recording (cs0begin/cs1begin) is active
+
| TSEC_FALCON_IMCTL_DEBUG_ADDR_BLK
 
|-
 
|-
| 4-7
+
| 24-26
| Number of instructions left for the crypto sequence
+
| TSEC_FALCON_IMCTL_DEBUG_CMD
 +
0x00: NOP
 +
0x02: IMBLK
 +
0x03: IMTAG
 +
|}
 +
 
 +
=== TSEC_FALCON_CMEMBASE ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 12-15
+
| 18-31
| Active crypto key register
+
| TSEC_FALCON_CMEMBASE_VAL
 
|}
 
|}
  
Contains information on the last crypto sequence (cs0 or cs1) executed.
+
=== TSEC_FALCON_DMEMAPERT ===
 
 
=== TSEC_SCP_INSN_STAT ===
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-7
| Destination register or immediate value
+
| TSEC_FALCON_DMEMAPERT_TIME_OUT
 +
|-
 +
| 8-11
 +
| TSEC_FALCON_DMEMAPERT_TIME_UNIT
 
|-
 
|-
| 8-13
+
| 16
| Source register or immediate value
+
| TSEC_FALCON_DMEMAPERT_ENABLE
 
|-
 
|-
| 20-24
+
| 17-19
| Operation
+
| TSEC_FALCON_DMEMAPERT_LDSTQ_NUM
0x0:  nop (fuc5 opcode 0x00)
+
|}
0x1:  cmov (fuc5 opcode 0x84)
+
 
0x2:  cxsin (fuc5 opcode 0x88) or xdst (with cxset)
+
=== TSEC_FALCON_EXTERRADDR ===
0x3:  cxsout (fuc5 opcode 0x8C) or xdld (with cxset)
+
{| class="wikitable" border="1"
0x4:  crnd (fuc5 opcode 0x90)
+
! Bits
0x5:  cs0begin (fuc5 opcode 0x94)
+
! Description
0x6:  cs0exec (fuc5 opcode 0x98)
 
  0x7:  cs1begin (fuc5 opcode 0x9C)
 
  0x8:  cs1exec (fuc5 opcode 0xA0)
 
0x9:  invalid (fuc5 opcode 0xA4)
 
0xA:  cchmod (fuc5 opcode 0xA8)
 
0xB:  cxor (fuc5 opcode 0xAC)
 
0xC:  cadd (fuc5 opcode 0xB0)
 
0xD:  cand (fuc5 opcode 0xB4)
 
0xE:  crev (fuc5 opcode 0xB8)
 
0xF:  cprecmac (fuc5 opcode 0xBC)
 
0x10: csecret (fuc5 opcode 0xC0)
 
0x11: ckeyreg (fuc5 opcode 0xC4)
 
0x12: ckexp (fuc5 opcode 0xC8)
 
0x13: ckrexp (fuc5 opcode 0xCC)
 
0x14: cenc (fuc5 opcode 0xD0)
 
0x15: cdec (fuc5 opcode 0xD4)
 
0x16: csigauth (fuc5 opcode 0xD8)
 
0x17: csigenc (fuc5 opcode 0xDC)
 
0x18: csigclr (fuc5 opcode 0xE0)
 
|-
 
| 28
 
| Set if the instruction is valid
 
 
|-
 
|-
| 31
+
| 0-31
| Set if running in HS mode
+
| TSEC_FALCON_EXTERRADDR_ADDR
 
|}
 
|}
  
Contains information on the last crypto instruction executed.
+
=== TSEC_FALCON_EXTERRSTAT ===
 
 
=== TSEC_SCP_AUTH_STAT ===
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-1
+
| 0-23
| Signature comparison result (3=succeeded, 2=failed)
+
| TSEC_FALCON_EXTERRSTAT_PC
 +
|-
 +
| 24-27
 +
| TSEC_FALCON_EXTERRSTAT_STAT
 +
|-
 +
| 31
 +
| TSEC_FALCON_EXTERRSTAT_VALID
 
|}
 
|}
  
Contains information on the last authentication attempt.
+
=== TSEC_FALCON_CG2 ===
 
 
=== TSEC_SCP_AES_STAT ===
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-4
+
| 1
| First opcode
+
| TSEC_FALCON_CG2_SLCG_FALCON_DMA
 +
|-
 +
| 2
 +
| TSEC_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM
 +
|-
 +
| 3
 +
| TSEC_FALCON_CG2_SLCG_FALCON_PIPE
 +
|-
 +
| 4
 +
| TSEC_FALCON_CG2_SLCG_FALCON_DIV
 
|-
 
|-
| 5-9
+
| 5
| Second opcode
+
| TSEC_FALCON_CG2_SLCG_FALCON_ICD
 
|-
 
|-
| 15-16
+
| 6
| AES operation
+
| TSEC_FALCON_CG2_SLCG_FALCON_CFG
0: Encryption
 
1: Decryption
 
2: Key expansion
 
3: Key reverse expansion
 
|}
 
 
 
Contains information on the last AES sequence executed.
 
 
 
=== TSEC_SCP_IRQSTAT ===
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Description
 
 
|-
 
|-
| 0
+
| 7
| TSEC_SCP_IRQSTAT_TRNG
+
| TSEC_FALCON_CG2_SLCG_FALCON_CTXSW
 
|-
 
|-
 
| 8
 
| 8
| TSEC_SCP_IRQSTAT_ACL_ERROR
+
| TSEC_FALCON_CG2_SLCG_FALCON_PMB
 +
|-
 +
| 9
 +
| TSEC_FALCON_CG2_SLCG_FALCON_RF
 +
|-
 +
| 10
 +
| TSEC_FALCON_CG2_SLCG_FALCON_MUL
 +
|-
 +
| 11
 +
| TSEC_FALCON_CG2_SLCG_FALCON_LDST
 
|-
 
|-
 
| 12
 
| 12
| Unknown
+
| TSEC_FALCON_CG2_SLCG_FALCON_TSYNC
 
|-
 
|-
| 16
+
| 13
| TSEC_SCP_IRQSTAT_INSN_ERROR
+
| TSEC_FALCON_CG2_SLCG_FALCON_GPTMR
 
|-
 
|-
| 20
+
| 14
| TSEC_SCP_IRQSTAT_SINGLE_STEP
+
| TSEC_FALCON_CG2_SLCG_FALCON_WDTMR
 
|-
 
|-
| 24
+
| 15
| Unknown
+
| TSEC_FALCON_CG2_SLCG_FALCON_IRQSTAT
 
|-
 
|-
| 28
+
| 16
| Unknown
+
| TSEC_FALCON_CG2_SLCG_FALCON_TOP
 +
|-
 +
| 17
 +
| TSEC_FALCON_CG2_SLCG_FBIF
 
|}
 
|}
  
Used for getting the status of crypto IRQs.
+
=== TSEC_FALCON_IMEMC ===
 
 
=== TSEC_SCP_IRQMASK ===
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 2-7
| TSEC_SCP_IRQMASK_TRNG
+
| TSEC_FALCON_IMEMC_OFFS
 +
|-
 +
| 8-15
 +
| TSEC_FALCON_IMEMC_BLK
 
|-
 
|-
| 8
+
| 24
| TSEC_SCP_IRQMASK_ACL_ERROR
+
| TSEC_FALCON_IMEMC_AINCW
 
|-
 
|-
| 12
+
| 25
| Unknown
+
| TSEC_FALCON_IMEMC_AINCR
 
|-
 
|-
| 16
+
| 28
| TSEC_SCP_IRQMASK_INSN_ERROR
+
| TSEC_FALCON_IMEMC_SECURE
 
|-
 
|-
| 20
+
| 29
| TSEC_SCP_IRQMASK_SINGLE_STEP
+
| TSEC_FALCON_IMEMC_SEC_ATOMIC
 
|-
 
|-
| 24
+
| 30
| Unknown
+
| TSEC_FALCON_IMEMC_SEC_WR_VIO
 
|-
 
|-
| 28
+
| 31
| Unknown
+
| TSEC_FALCON_IMEMC_SEC_LOCK
 
|}
 
|}
  
Used for getting the value of the mask for crypto IRQs.
+
Used for configuring access to Falcon's IMEM.
  
=== TSEC_SCP_ACL_ERR ===
+
=== TSEC_FALCON_IMEMD ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-31
| Set when writing to a crypto register without the correct ACL
+
| TSEC_FALCON_IMEMD_DATA
|-
+
|}
| 4
+
 
| Set when reading from a crypto register without the correct ACL
+
Returns or takes the value for an IMEM read/write operation.
 +
 
 +
=== TSEC_FALCON_IMEMT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 8
+
| 0-15
| Set on an invalid ACL change (cchmod)
+
| TSEC_FALCON_IMEMT_TAG
|-
 
| 31
 
| An ACL error occurred
 
 
|}
 
|}
  
Contains information on the status generated by the [[#TSEC_SCP_IRQSTAT|TSEC_SCP_IRQSTAT_ACL_ERROR]] IRQ.
+
Returns or takes the virtual page index for an IMEM read/write operation.
  
=== TSEC_SCP_INSN_ERR ===
+
=== TSEC_FALCON_DMEMC ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 2-7
| Invalid instruction
+
| TSEC_FALCON_DMEMC_OFFS
 
|-
 
|-
| 4
+
| 8-15
| Empty crypto sequence
+
| TSEC_FALCON_DMEMC_BLK
 
|-
 
|-
| 8
+
| 24
| Crypto sequence is too long
+
| TSEC_FALCON_DMEMC_AINCW
 
|-
 
|-
| 12
+
| 25
| Crypto sequence was not finished
+
| TSEC_FALCON_DMEMC_AINCR
|-
+
|}
| 16
+
 
| Insecure signature (csigenc, csigclr or csigauth)
+
Used for configuring access to Falcon's DMEM.
|-
+
 
| 20
+
=== TSEC_FALCON_DMEMD ===
| Invalid signature (csigauth in HS mode)
+
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 24
+
| 0-31
| Forbidden ACL change (cchmod in NS mode)
+
| TSEC_FALCON_DMEMD_DATA
 
|}
 
|}
  
Contains information on crypto errors generated by the [[#TSEC_SCP_IRQSTAT|TSEC_SCP_IRQSTAT_INSN_ERROR]] IRQ.
+
Returns or takes the value for a DMEM read/write operation.
  
=== TSEC_TFBIF_MCCIF_FIFOCTRL ===
+
=== TSEC_FALCON_ICD_CMD ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0
+
| 0-3
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVERRIDE
+
| TSEC_FALCON_ICD_CMD_OPC
 +
0x00: STOP
 +
0x01: RUN (run from PC)
 +
0x02: JRUN (run from address)
 +
0x03: RUNB (run from PC)
 +
0x04: JRUNB (run from address)
 +
0x05: STEP (step from PC)
 +
0x06: JSTEP (step from address)
 +
0x07: EMASK (set exception mask)
 +
0x08: RREG (read register)
 +
0x09: WREG (write register)
 +
0x0A: RDM (read data memory)
 +
0x0B: WDM (write data memory)
 +
0x0C: RCM (read MMIO/configuration memory)
 +
0x0D: WCM (write MMIO/configuration memory)
 +
0x0E: RSTAT (read status)
 +
0x0F: SBU (store buffer update)
 
|-
 
|-
| 1
+
| 6-7
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVERRIDE
+
| TSEC_FALCON_ICD_CMD_SZ
 +
0x00: B (byte)
 +
0x01: HW (half word)
 +
0x02: W (word)
 
|-
 
|-
| 2
+
| 8-12
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRCL_MCLE2X
+
| TSEC_FALCON_ICD_CMD_IDX
|-
+
0x00: REG0 | RSTAT0 | WB0
| 3
+
0x01: REG1 | RSTAT1 | WB1
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDMC_RDFAST
+
0x02: REG2 | RSTAT2 | WB2
|-
+
0x03: REG3 | RSTAT3 | WB3
| 4
+
0x04: REG4 | RSTAT4
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRMC_CLLE2X
+
0x05: REG5 | RSTAT5
|-
+
0x06: REG6
| 5
+
0x07: REG7
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDCL_RDFAST
+
0x08: REG8
 +
0x09: REG9
 +
0x0A: REG10
 +
0x0B: REG11
 +
0x0C: REG12
 +
0x0D: REG13
 +
0x0E: REG14
 +
0x0F: REG15
 +
0x10: IV0
 +
0x11: IV1
 +
0x12: UNDEFINED
 +
0x13: EV
 +
0x14: SP
 +
0x15: PC
 +
0x16: IMB
 +
0x17: DMB
 +
0x18: CSW
 +
0x19: CCR
 +
0x1A: SEC
 +
0x1B: CTX
 +
0x1C: EXCI
 +
0x1D: SEC1
 +
0x1E: IMB1
 +
0x1F: DMB1
 
|-
 
|-
| 6
+
| 14
| TSEC_TFBIF_MCCIF_FIFOCTRL_CCLK_OVERRIDE
+
| TSEC_FALCON_ICD_CMD_ERROR
 
|-
 
|-
| 7
+
| 15
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVR_MODE
+
| TSEC_FALCON_ICD_CMD_RDVLD
 
|-
 
|-
| 8
+
| 16-31
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVR_MODE
+
| TSEC_FALCON_ICD_CMD_PARM
|}
+
0x0001: EMASK_TRAP0
 
+
0x0002: EMASK_TRAP1
=== TSEC_TFBIF_MCCIF_FIFOCTRL1 ===
+
0x0004: EMASK_TRAP2
 +
0x0008: EMASK_TRAP3
 +
0x0010: EMASK_EXC_UNIMP
 +
0x0020: EMASK_EXC_IMISS
 +
0x0040: EMASK_EXC_IMHIT
 +
0x0080: EMASK_EXC_IBREAK
 +
0x0100: EMASK_IV0
 +
0x0200: EMASK_IV1
 +
0x0400: EMASK_IV2
 +
0x0800: EMASK_EXT0
 +
0x1000: EMASK_EXT1
 +
0x2000: EMASK_EXT2
 +
0x4000: EMASK_EXT3
 +
0x8000: EMASK_EXT4
 +
|}
 +
 
 +
Used for sending commands to the Falcon's in-chip debugger.
 +
 
 +
=== TSEC_FALCON_ICD_ADDR ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-15
+
| 0-31
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SRD2MC_REORDER_DEPTH_LIMIT
+
| TSEC_FALCON_ICD_ADDR_ADDR
 +
|}
 +
 
 +
Takes the target address for the Falcon's in-chip debugger.
 +
 
 +
=== TSEC_FALCON_ICD_WDATA ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
| 16-31
+
| 0-31
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SWR2MC_REORDER_DEPTH_LIMIT
+
| TSEC_FALCON_ICD_WDATA_DATA
 
|}
 
|}
  
=== TSEC_TFBIF_MMU_PROT ===
+
Takes the data for writing using the Falcon's in-chip debugger.
 +
 
 +
=== TSEC_FALCON_ICD_RDATA ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-3
+
| 0-31
| Read access level
+
| TSEC_FALCON_ICD_RDATA_DATA
|-
 
| 4-7
 
| Write access level
 
 
|}
 
|}
  
Controls accesses to external memory at the MMU level. Accessible in HS mode only.
+
Returns the data read using the Falcon's in-chip debugger.
  
=== TSEC_TFBIF_MMU_PHYS_SEC ===
+
When reading from an internal status register (STAT), the following applies:
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 2,612: Line 3,031:
 
|-
 
|-
 
| 0
 
| 0
| Bypass MMU translation on CTXDMA port 0
+
| RSTAT0_MEM_STALL
 +
|-
 +
| 1
 +
| RSTAT0_DMA_STALL
 +
|-
 +
| 2
 +
| RSTAT0_FENCE_STALL
 +
|-
 +
| 3
 +
| RSTAT0_DIV_STALL
 
|-
 
|-
 
| 4
 
| 4
| Bypass MMU translation on CTXDMA port 1
+
| RSTAT0_DMA_STALL_DMAQ
 +
|-
 +
| 5
 +
| RSTAT0_DMA_STALL_DMWAITING
 +
|-
 +
| 6
 +
| RSTAT0_DMA_STALL_IMWAITING
 +
|-
 +
| 7
 +
| RSTAT0_ANY_STALL
 
|-
 
|-
 
| 8
 
| 8
| Bypass MMU translation on CTXDMA port 2
+
| RSTAT0_SBFULL_STALL
 +
|-
 +
| 9
 +
| RSTAT0_SBHIT_STALL
 +
|-
 +
| 10
 +
| RSTAT0_FLOW_STALL
 +
|-
 +
| 11
 +
| RSTAT0_SP_STALL
 
|-
 
|-
 
| 12
 
| 12
| Bypass MMU translation on CTXDMA port 3
+
| RSTAT0_BL_STALL
 +
|-
 +
| 13
 +
| RSTAT0_IPND_STALL
 +
|-
 +
| 14
 +
| RSTAT0_LDSTQ_STALL
 
|-
 
|-
 
| 16
 
| 16
| Bypass MMU translation on CTXDMA port 4
+
| RSTAT0_NOINSTR_STALL
 
|-
 
|-
 
| 20
 
| 20
| Bypass MMU translation on CTXDMA port 5
+
| RSTAT0_HALTSTOP_FLUSH
 
|-
 
|-
| 24
+
| 21
| Bypass MMU translation on CTXDMA port 6
+
| RSTAT0_AFILL_FLUSH
 +
|-
 +
| 22
 +
| RSTAT0_EXC_FLUSH
 +
|-
 +
| 23-25
 +
| RSTAT0_IRQ_FLUSH
 
|-
 
|-
 
| 28
 
| 28
| Bypass MMU translation on CTXDMA port 7
+
| RSTAT0_VALIDRD
 +
|-
 +
| 29
 +
| RSTAT0_WAITING
 +
|-
 +
| 30
 +
| RSTAT0_HALTED
 +
|-
 +
| 31
 +
| RSTAT0_MTHD_FULL
 
|}
 
|}
 
Controls MMU bypass mode. Accessible in HS mode only.
 
 
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
 
 
=== TSEC_TFBIF_MMU_TRANSCFG ===
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 2,646: Line 3,107:
 
|-
 
|-
 
| 0-3
 
| 0-3
| Transfer configuration for CTXDMA port 0
+
| RSTAT1_WB_ALLOC
 
|-
 
|-
 
| 4-7
 
| 4-7
| Transfer configuration for CTXDMA port 1
+
| RSTAT1_WB_VALID
 
|-
 
|-
| 8-11
+
| 8-9
| Transfer configuration for CTXDMA port 2
+
| RSTAT1_WB0_SZ
 
|-
 
|-
| 12-15
+
| 10-11
| Transfer configuration for CTXDMA port 3
+
| RSTAT1_WB1_SZ
 
|-
 
|-
| 16-19
+
| 12-13
| Transfer configuration for CTXDMA port 4
+
| RSTAT1_WB2_SZ
 
|-
 
|-
| 20-23
+
| 14-15
| Transfer configuration for CTXDMA port 5
+
| RSTAT1_WB3_SZ
 +
|-
 +
| 16-19
 +
| RSTAT1_WB0_IDX
 +
|-
 +
| 20-23
 +
| RSTAT1_WB1_IDX
 
|-
 
|-
 
| 24-27
 
| 24-27
| Transfer configuration for CTXDMA port 6
+
| RSTAT1_WB2_IDX
 
|-
 
|-
 
| 28-31
 
| 28-31
| Transfer configuration for CTXDMA port 7
+
| RSTAT1_WB3_IDX
 
|}
 
|}
 
Controls external memory transfers' configuration at the MMU level. Accessible in HS mode only.
 
 
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
 
 
=== TSEC_TFBIF_ACTMON_MAMASK ===
 
Takes the memory access mask for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
 
 
=== TSEC_TFBIF_ACTMON_BORPS ===
 
Takes the billions of records per second count for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
 
 
=== TSEC_TFBIF_ACTMON_CTL ===
 
Controls the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
 
 
=== TSEC_CG ===
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
| 0-5
+
| 0-3
| TSEC_CG_IDLE_CG_DLY_CNT
+
| RSTAT2_DMAQ_NUM
 +
|-
 +
| 4
 +
| RSTAT2_DMA_ENABLE
 
|-
 
|-
| 6
+
| 5-7
| TSEC_CG_IDLE_CG_EN
+
| RSTAT2_LDSTQ_NUM
 
|-
 
|-
| 16-18
+
| 16-19
| TSEC_CG_WAKEUP_DLY_CNT
+
| RSTAT2_EM_BUSY
 
|-
 
|-
| 19
+
| 20-23
| TSEC_CG_WAKEUP_DLY_EN
+
| RSTAT2_EM_ACKED
|}
+
|-
 
+
| 24-27
=== TSEC_BAR0_CTL ===
+
| RSTAT2_EM_ISWR
 +
|-
 +
| 28-31
 +
| RSTAT2_EM_DVLD
 +
|}
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 2,707: Line 3,166:
 
|-
 
|-
 
| 0
 
| 0
| TSEC_BAR0_CTL_READ
+
| RSTAT3_MTHD_IDLE
 
|-
 
|-
 
| 1
 
| 1
| TSEC_BAR0_CTL_WRITE
+
| RSTAT3_CTXSW_IDLE
 +
|-
 +
| 2
 +
| RSTAT3_DMA_IDLE
 +
|-
 +
| 3
 +
| RSTAT3_SCP_IDLE
 
|-
 
|-
| 4-7
+
| 4
| TSEC_BAR0_CTL_BYTE_MASK
+
| RSTAT3_LDST_IDLE
 
|-
 
|-
| 12-13
+
| 5
| TSEC_BAR0_CTL_STATUS
+
| RSTAT3_SBWB_EMPTY
0: Idle
 
1: Busy
 
2: Error
 
3: Disabled
 
 
|-
 
|-
| 31
+
| 6-8
| TSEC_BAR0_CTL_INIT
+
| RSTAT3_CSWIE
|}
+
|-
 
+
| 10
A BAR0 DMA read/write operation requires bits TSEC_BAR0_CTL_INIT and TSEC_BAR0_CTL_READ/TSEC_BAR0_CTL_WRITE to be set in TSEC_BAR0_CTL.
+
| RSTAT3_CSWE
 
+
|-
During the transfer, TSEC_BAR0_CTL_STATUS is set to "Busy".
+
| 12-14
 
+
| RSTAT3_CTXSW_STATE
Accessing an invalid address sets TSEC_BAR0_CTL_STATUS to "Error".
+
0x00: IDLE
 
+
0x01: SM_CHECK
=== TSEC_BAR0_ADDR ===
+
0x02: SM_SAVE
Takes the address for DMA transfers between TSEC and HOST1X (master and clients).
+
0x03: SM_SAVE_WAIT
 
+
0x04: SM_BLK_BIND
=== TSEC_BAR0_DATA ===
+
0x05: SM_RESET
Takes the data for DMA transfers between TSEC and HOST1X (master and clients).
+
  0x06: SM_RESETWAIT
 
+
  0x07: SM_ACK
=== TSEC_BAR0_TIMEOUT ===
 
Takes the timeout value for DMA transfers between TSEC and HOST1X (master and clients).
 
 
 
=== TSEC_TEGRA_CTL ===
 
{| class="wikitable" border="1"
 
! Bits
 
! Description
 
 
|-
 
|-
| 16
+
| 15
| TSEC_TEGRA_CTL_TKFI_KFUSE
+
| RSTAT3_CTXSW_PEND
 
|-
 
|-
 
| 17
 
| 17
| TSEC_TEGRA_CTL_TKFI_RESTART_FSM_KFUSE
+
| RSTAT3_DMA_FBREQ_IDLE
|-
+
|-
| 24
+
| 18
| TSEC_TEGRA_CTL_TMPI_FORCE_IDLE_INPUTS_I2C
+
| RSTAT3_DMA_ACKQ_EMPTY
|-
+
|-
| 25
+
| 19
| TSEC_TEGRA_CTL_TMPI_RESTART_FSM_HOST1X
+
| RSTAT3_DMA_RDQ_EMPTY
|-
+
|-
| 26
+
| 20
| TSEC_TEGRA_CTL_TMPI_RESTART_FSM_APB
+
| RSTAT3_DMA_WR_BUSY
|-
+
|-
| 27
+
| 21
| TSEC_TEGRA_CTL_TMPI_DISABLE_OUTPUT_I2C
+
| RSTAT3_DMA_RD_BUSY
|}
+
|-
 
+
| 22
== SCP ==
+
| RSTAT3_LDST_XT_BUSY
Part of the information here (which hasn't made it into envytools documentation yet) was shared by [https://wiki.0x04.net/wiki/Marcin_Ko%C5%9Bcielnicki mwk] from reverse engineering falcon processors over the years.
+
|-
 
+
| 23
=== Authenticated Mode ===
+
| RSTAT3_LDST_XT_BLOCK
==== Entry ====
+
|-
From non-secure mode, upon jumping to a page marked as secret, a secret fault occurs. This causes the CPU to verify the region specified in $cauth against the MAC loaded in $c6. If the comparison is successful, the valid bit (bit0) is set on all pages in the $cauth region, and $pc is set to the base of the $cauth region. If the comparsion fails, the CPU is halted.
+
| 24
 
+
| RSTAT3_ENG_IDLE
==== Exit ====
+
|}
The CPU automatically goes back to non-secure mode when returning back into non-secret pages. When this happens, the valid bit (bit0) in the TLB flags is cleared for all secret pages.
+
{| class="wikitable" border="1"
 
+
!  Bits
==== Implementation ====
+
!  Description
Under certain circumstances, it is possible to observe [[#csigauth|csigauth]] being briefly written to [[#TSEC_SCP_INSN_STAT|TSEC_SCP_INSN_STAT]] as "csigauth $c4 $c6" while the opcodes in [[#TSEC_SCP_AES_STAT|TSEC_SCP_AES_STAT]] are set to "cxsin" and "csigauth", respectively.
+
|-
 
+
| 0-1
Via [[#TSEC_SCP_SEQ_CTL|TSEC_SCP_SEQ_CTL]] it can be observed that a 3-sized macro sequence is loaded into cs0 during a secure mode transition.
+
| RSTAT4_ICD_STATE
 
+
0x00: NORMAL
=== Operations ===
+
0x01: WAIT_ISSUE_CLEAR
{| class="wikitable" border="1"
+
0x02: WAIT_EXLDQ_CLEAR
Opcode
+
0x03: FULL_DBG_MODE
Name
+
|-
!  Operand0
+
| 2-3
!  Operand1
+
| RSTAT4_ICD_MODE
!  Operation
+
0x00: SUPPRESSICD
!  Condition
+
0x01: ENTERICD_IBRK
|-
+
0x02: ENTERICD_STEP
| 0 || nop || N/A || N/A || ||
+
|-
|-
+
| 16
| 1 || mov || $cX || $cY || <code>$cX = $cY; ACL(X) = ACL(Y);</code> ||
+
| RSTAT4_ICD_EMASK_TRAP0
|-
+
|-
| 2 || sin || $cX || N/A || <code>$cX = read_stream(); ACL(X) = ???;</code> ||
+
| 17
|-
+
| RSTAT4_ICD_EMASK_TRAP1
| 3 || sout || $cX || N/A || <code>write_stream($cX);</code> || ?
+
|-
|-
+
| 18
| 4 || rnd || $cX || N/A || <code>$cX = read_trng(); ACL(X) = ???;</code> ||
+
| RSTAT4_ICD_EMASK_TRAP2
|-
+
|-
| 5 || s0begin || immX || N/A || <code>record_macro_for_N_instructions(0, immX);</code> ||
+
| 19
|-
+
| RSTAT4_ICD_EMASK_TRAP3
| 6 || s0exec || immX || N/A || <code>execute_macro_N_times(0, immX);</code> ||
+
|-
|-
+
| 20
| 7 || s1begin || immX || N/A || <code>record_macro_for_N_instructions(1, immX);</code> ||
+
| RSTAT4_ICD_EMASK_EXC_UNIMP
|-
+
|-
| 8 || s1exec || immX || N/A || <code>execute_macro_N_times(1, immX);</code> ||
+
| 21
 +
| RSTAT4_ICD_EMASK_EXC_IMISS
 +
|-
 +
| 22
 +
| RSTAT4_ICD_EMASK_EXC_IMHIT
 +
|-
 +
| 23
 +
| RSTAT4_ICD_EMASK_EXC_IBREAK
 +
|-
 +
| 24
 +
| RSTAT4_ICD_EMASK_IV0
 +
|-
 +
| 25
 +
| RSTAT4_ICD_EMASK_IV1
 +
|-
 +
| 26
 +
| RSTAT4_ICD_EMASK_IV2
 +
|-
 +
| 27
 +
| RSTAT4_ICD_EMASK_EXT0
 +
|-
 +
| 28
 +
| RSTAT4_ICD_EMASK_EXT1
 +
|-
 +
| 29
 +
| RSTAT4_ICD_EMASK_EXT2
 +
|-
 +
| 30
 +
| RSTAT4_ICD_EMASK_EXT3
 +
|-
 +
| 31
 +
| RSTAT4_ICD_EMASK_EXT4
 +
|}
 +
{| class="wikitable" border="1"
 +
Bits
 +
Description
 +
|-
 +
| 0-7
 +
| RSTAT5_LRU_STATE
 +
|}
 +
 
 +
=== TSEC_FALCON_SCTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_FALCON_SCTL_LSMODE
 +
|-
 +
| 1
 +
| TSEC_FALCON_SCTL_HSMODE
 +
|-
 +
| 4-5
 +
| Unknown
 +
|-
 +
| 12-13
 +
| Unknown
 +
|-
 +
| 14
 +
| Initialize the transition to LS mode
 +
|}
 +
 
 +
=== TSEC_FALCON_SSTAT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 30
 +
| Unknown
 +
|-
 +
| 31
 +
| Set on memory protection violation
 +
|}
 +
 
 +
=== TSEC_FALCON_SPROT_IMEM ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to Falcon IMEM.
 +
 
 +
=== TSEC_FALCON_SPROT_DMEM ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to Falcon DMEM.
 +
 
 +
=== TSEC_FALCON_SPROT_CPUCTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to the [[#TSEC_FALCON_CPUCTL|TSEC_FALCON_CPUCTL]] register.
 +
 
 +
=== TSEC_FALCON_SPROT_MISC ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to the following registers:
 +
* [[#TSEC_FALCON_PRIVSTATE|TSEC_FALCON_PRIVSTATE]]
 +
* [[#TSEC_FALCON_SFTRESET|TSEC_FALCON_SFTRESET]]
 +
* [[#TSEC_FALCON_ADDR|TSEC_FALCON_ADDR]]
 +
* [[#TSEC_FALCON_DMACTL|TSEC_FALCON_DMACTL]]
 +
* [[#TSEC_FALCON_IMCTL|TSEC_FALCON_IMCTL]]
 +
* [[#TSEC_FALCON_IMSTAT|TSEC_FALCON_IMSTAT]]
 +
* TSEC_FALCON_UNK_250
 +
* [[#TSEC_FALCON_DMAINFO_CTL|TSEC_FALCON_DMAINFO_CTL]]
 +
 
 +
=== TSEC_FALCON_SPROT_IRQ ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to the following registers:
 +
* [[#TSEC_FALCON_IRQMODE|TSEC_FALCON_IRQMODE]]
 +
* [[#TSEC_FALCON_IRQMSET|TSEC_FALCON_IRQMSET]]
 +
* [[#TSEC_FALCON_IRQMCLR|TSEC_FALCON_IRQMCLR]]
 +
* [[#TSEC_FALCON_IRQDEST|TSEC_FALCON_IRQDEST]]
 +
* [[#TSEC_FALCON_GPTMRINT|TSEC_FALCON_GPTMRINT]]
 +
* [[#TSEC_FALCON_GPTMRVAL|TSEC_FALCON_GPTMRVAL]]
 +
* [[#TSEC_FALCON_GPTMRCTL|TSEC_FALCON_GPTMRCTL]]
 +
* [[#TSEC_FALCON_IRQDEST2|TSEC_FALCON_IRQDEST2]]
 +
* TSEC_FALCON_UNK_E0
 +
 
 +
=== TSEC_FALCON_SPROT_MTHD ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to the following registers:
 +
* [[#TSEC_FALCON_ITFEN|TSEC_FALCON_ITFEN]]
 +
* [[#TSEC_FALCON_CURCTX|TSEC_FALCON_CURCTX]]
 +
* [[#TSEC_FALCON_NXTCTX|TSEC_FALCON_NXTCTX]]
 +
* [[#TSEC_FALCON_CTXACK|TSEC_FALCON_CTXACK]]
 +
* [[#TSEC_FALCON_MTHDDATA|TSEC_FALCON_MTHDDATA]]
 +
* [[#TSEC_FALCON_MTHDID|TSEC_FALCON_MTHDID]]
 +
* [[#TSEC_FALCON_MTHDWDAT|TSEC_FALCON_MTHDWDAT]]
 +
* [[#TSEC_FALCON_MTHDCOUNT|TSEC_FALCON_MTHDCOUNT]]
 +
* [[#TSEC_FALCON_MTHDPOP|TSEC_FALCON_MTHDPOP]]
 +
* [[#TSEC_FALCON_MTHDRAMSZ|TSEC_FALCON_MTHDRAMSZ]]
 +
* [[#TSEC_FALCON_DEBUG1|TSEC_FALCON_DEBUG1]]
 +
 
 +
=== TSEC_FALCON_SPROT_SCTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to the [[#TSEC_FALCON_SCTL|TSEC_FALCON_SCTL]] register.
 +
 
 +
=== TSEC_FALCON_SPROT_WDTMR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to the following registers:
 +
* [[#TSEC_FALCON_WDTMRVAL|TSEC_FALCON_WDTMRVAL]]
 +
* [[#TSEC_FALCON_WDTMRCTL|TSEC_FALCON_WDTMRCTL]]
 +
 
 +
=== TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL
 +
|}
 +
 
 +
=== TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-30
 +
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL
 +
|-
 +
| 31
 +
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT
 +
|}
 +
 
 +
=== TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL
 +
|}
 +
 
 +
=== TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-30
 +
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL
 +
|-
 +
| 31
 +
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT
 +
|}
 +
 
 +
=== TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL
 +
|}
 +
 
 +
=== TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-30
 +
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL
 +
|-
 +
| 31
 +
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT
 +
|}
 +
 
 +
=== TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL
 +
|}
 +
 
 +
=== TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-30
 +
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL
 +
|-
 +
| 31
 +
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT
 +
|}
 +
 
 +
=== TSEC_FALCON_DMAINFO_CTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_FALCON_DMAINFO_CTL_CLR_FBRD
 +
|-
 +
| 1
 +
| TSEC_FALCON_DMAINFO_CTL_CLR_FBWR
 +
|}
 +
 
 +
=== TSEC_SCP_CTL0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 10
 +
| Enable the [[#LOAD|LOAD]] block's interface
 +
|-
 +
| 12
 +
| Enable the [[#STORE|STORE]] block's interface
 +
|-
 +
| 14
 +
| Enable the [[#CMD|CMD]] block's interface
 +
|-
 +
| 16
 +
| Enable the [[#SEQ|SEQ]] block
 +
|-
 +
| 20
 +
| Enable the [[#CTL|CTL]] block
 +
|}
 +
 
 +
=== TSEC_SCP_CTL1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Clear [[#SEQ|SEQ]] block's pipeline
 +
|-
 +
| 8
 +
| Clear the main [[#SCP|SCP]] pipeline
 +
|-
 +
| 11
 +
| Enable [[#RNG|RNG]] block's test mode
 +
|-
 +
| 12
 +
| Enable the [[#RNG|RNG]] block
 +
|-
 +
| 16
 +
| Enable [[#LOAD|LOAD]] block's interface dummy mode (all reads return 0)
 +
|-
 +
| 20
 +
| Enable [[#LOAD|LOAD]] block's interface bypassing (all reads are dropped)
 +
|-
 +
| 24
 +
| Enable [[#STORE|STORE]] block's interface bypassing (all writes are dropped)
 +
|}
 +
 
 +
=== TSEC_SCP_CTL_STAT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 20
 +
| TSEC_SCP_CTL_STAT_DEBUG_MODE
 +
|}
 +
 
 +
=== TSEC_SCP_CTL_LOCK ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Enable lockdown mode (locks IMEM and DMEM)
 +
|-
 +
| 1
 +
| Unknown
 +
|-
 +
| 2
 +
| Unknown
 +
|-
 +
| 3
 +
| Unknown
 +
|-
 +
| 4
 +
| Lock the [[#SCP|SCP]]
 +
|-
 +
| 5
 +
| Unknown
 +
|-
 +
| 6
 +
| Unknown
 +
|-
 +
| 7
 +
| Unknown
 +
|}
 +
 
 +
Controls lockdown mode and can only be cleared in Heavy Secure mode.
 +
 
 +
=== TSEC_SCP_CFG ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Unknown
 +
|-
 +
| 1
 +
| Unknown
 +
|-
 +
| 2
 +
| Unknown
 +
|-
 +
| 3
 +
| Unknown
 +
|-
 +
| 4
 +
| [[#AES|AES]] block's endianness
 +
0: Little
 +
1: Big
 +
|-
 +
| 8
 +
| Flush [[#CMD|CMD]] block's pipeline
 +
|-
 +
| 12-13
 +
| Carry chain size
 +
0: 32 bits
 +
1: 64 bits
 +
2: 96 bits
 +
3: 128 bits
 +
|-
 +
| 16-31
 +
| Timeout value
 +
|}
 +
 
 +
=== TSEC_SCP_CTL_SCP ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Swap [[#SCP|SCP]] master
 +
|-
 +
| 1
 +
| Current [[#SCP|SCP]] master
 +
0: Falcon
 +
1: External
 +
|}
 +
 
 +
=== TSEC_SCP_CTL_PKEY ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_SCP_CTL_PKEY_REQUEST_RELOAD
 +
|-
 +
| 1
 +
| TSEC_SCP_CTL_PKEY_LOADED
 +
|}
 +
 
 +
=== TSEC_SCP_CTL_DBG ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Unknown
 +
|-
 +
| 4
 +
| Unknown
 +
|-
 +
| 8
 +
| Unknown
 +
|-
 +
| 12
 +
| Unknown
 +
|}
 +
 
 +
=== TSEC_SCP_DBG0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Index
 +
|-
 +
| 4
 +
| Auto-increment
 +
|-
 +
| 5-6
 +
| Target
 +
0: None
 +
1: STORE
 +
2: LOAD
 +
3: SEQ
 +
|-
 +
| 8-12
 +
| [[#SEQ|SEQ]] block's current sequence size
 +
|-
 +
| 13-16
 +
| [[#SEQ|SEQ]] block's current instruction address
 +
|-
 +
| 17
 +
| [[#SEQ|SEQ]] block's current instruction is valid
 +
|-
 +
| 18
 +
| [[#SEQ|SEQ]] block is running in HS mode
 +
|-
 +
| 19-22
 +
| [[#LOAD|LOAD]] block's pipeline size
 +
|-
 +
| 23
 +
| [[#LOAD|LOAD]] block's current operation is valid
 +
|-
 +
| 24
 +
| [[#LOAD|LOAD]] block is running in HS mode
 +
|-
 +
| 25-26
 +
| [[#STORE|STORE]] block's pipeline size
 +
|-
 +
| 30
 +
| [[#STORE|STORE]] block's current operation is valid
 +
|-
 +
| 31
 +
| [[#STORE|STORE]] block is running in HS mode
 +
|}
 +
 
 +
Used for debugging the [[#LOAD|LOAD]], [[#STORE|STORE]] and [[#SEQ|SEQ]] blocks.
 +
 
 +
=== TSEC_SCP_DBG1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| [[#SEQ|SEQ]] block's current instruction's first operand
 +
|-
 +
| 4-9
 +
| [[#SEQ|SEQ]] block's current instruction's second operand
 +
|-
 +
| 10-14
 +
| [[#SEQ|SEQ]] block's current instruction's opcode
 +
|}
 +
 
 +
Used for retrieving debug data. Contains information on the last crypto sequence created when debugging the SEQ controller.
 +
 
 +
=== TSEC_SCP_DBG2 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-1
 +
| [[#SEQ|SEQ]] block's state
 +
0: Idle
 +
1: Recording is active (cs0begin/cs1begin)
 +
|-
 +
| 4-7
 +
| Number of [[#SEQ|SEQ]] block's instructions left
 +
|-
 +
| 12-15
 +
| Active crypto key register
 +
|}
 +
 
 +
Used for retrieving additional debug data associated with the [[#SEQ|SEQ]] block.
 +
 
 +
=== TSEC_SCP_CMD ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Destination register
 +
|-
 +
| 8-13
 +
| Source register or immediate value
 +
|-
 +
| 20-24
 +
| Command opcode
 +
0x0:  nop (fuc5 opcode 0x00)
 +
0x1:  cmov (fuc5 opcode 0x84)
 +
0x2:  cxsin (fuc5 opcode 0x88) or xdst (with cxset)
 +
0x3:  cxsout (fuc5 opcode 0x8C) or xdld (with cxset)
 +
0x4:  crnd (fuc5 opcode 0x90)
 +
0x5:  cs0begin (fuc5 opcode 0x94)
 +
0x6:  cs0exec (fuc5 opcode 0x98)
 +
0x7:  cs1begin (fuc5 opcode 0x9C)
 +
0x8:  cs1exec (fuc5 opcode 0xA0)
 +
0x9:  invalid (fuc5 opcode 0xA4)
 +
0xA:  cchmod (fuc5 opcode 0xA8)
 +
0xB:  cxor (fuc5 opcode 0xAC)
 +
0xC:  cadd (fuc5 opcode 0xB0)
 +
0xD:  cand (fuc5 opcode 0xB4)
 +
0xE:  crev (fuc5 opcode 0xB8)
 +
0xF:  cprecmac (fuc5 opcode 0xBC)
 +
0x10: csecret (fuc5 opcode 0xC0)
 +
0x11: ckeyreg (fuc5 opcode 0xC4)
 +
0x12: ckexp (fuc5 opcode 0xC8)
 +
0x13: ckrexp (fuc5 opcode 0xCC)
 +
0x14: cenc (fuc5 opcode 0xD0)
 +
0x15: cdec (fuc5 opcode 0xD4)
 +
0x16: csigcmp (fuc5 opcode 0xD8)
 +
0x17: csigenc (fuc5 opcode 0xDC)
 +
0x18: csigclr (fuc5 opcode 0xE0)
 +
|-
 +
| 28
 +
| [[#CMD|CMD]] block's current instruction is valid
 +
|-
 +
| 31
 +
| [[#CMD|CMD]] block is running in HS mode
 +
|}
 +
 
 +
Contains information on the last crypto command executed.
 +
 
 +
=== TSEC_SCP_STAT0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| [[#SCP|SCP]] is active
 +
|-
 +
| 2
 +
| [[#CMD|CMD]] block's interface is active
 +
|-
 +
| 4
 +
| [[#STORE|STORE]] block's interface is active
 +
|-
 +
| 6
 +
| [[#SEQ|SEQ]] block is active
 +
|-
 +
| 8
 +
| [[#CTL|CTL]] block is active
 +
|-
 +
| 10
 +
| [[#LOAD|LOAD]] block's interface is active
 +
|-
 +
| 14
 +
| [[#AES|AES]] block is active
 +
|-
 +
| 16
 +
| [[#RNG|RNG]] block is active
 +
|}
 +
 
 +
Contains the status of the hardware blocks and interfaces.
 +
 
 +
=== TSEC_SCP_STAT1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-1
 +
| Signature comparison result
 +
0: None
 +
1: Running
 +
2: Failed
 +
3: Succeeded
 +
|-
 +
| 4
 +
| [[#LOAD|LOAD]] block's interface is running in HS mode
 +
|-
 +
| 6
 +
| [[#LOAD|LOAD]] block's interface is ready
 +
|-
 +
| 8
 +
| [[#STORE|STORE]] block's interface is running in HS mode
 +
|-
 +
| 10
 +
| [[#STORE|STORE]] block's interface received a valid operation
 +
|-
 +
| 12
 +
| [[#CMD|CMD]] block's interface is running in HS mode
 +
|-
 +
| 14
 +
| [[#CMD|CMD]] block's interface received a valid instruction
 +
|}
 +
 
 +
Contains the status of the last authentication attempt and other miscellaneous statuses.
 +
 
 +
=== TSEC_SCP_STAT2 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-4
 +
| Current [[#SEQ|SEQ]] block opcode
 +
|-
 +
| 5-9
 +
| Current [[#CMD|CMD]] block's interface opcode
 +
|-
 +
| 10-14
 +
| Pending [[#CMD|CMD]] block opcode
 +
|-
 +
| 15-16
 +
| Current [[#AES|AES]] block operation
 +
0: Encryption
 +
1: Decryption
 +
2: Key expansion
 +
3: Key reverse expansion
 +
|-
 +
| 24
 +
| Unknown
 +
|-
 +
| 25
 +
| [[#STORE|STORE]] block is stalled
 +
|-
 +
| 26
 +
| [[#LOAD|LOAD]] block is stalled
 +
|-
 +
| 27
 +
| [[#RNG|RNG]] block is stalled
 +
|-
 +
| 28
 +
| Unknown
 +
|-
 +
| 29
 +
| [[#AES|AES]] block is stalled
 +
|}
 +
 
 +
Contains the status of crypto operations.
 +
 
 +
=== TSEC_SCP_RNG_STAT0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| [[#RND|RND]] block is ready
 +
|-
 +
| 4-7
 +
| Unknown
 +
|-
 +
| 8-11
 +
| Unknown
 +
|-
 +
| 16
 +
| Unknown
 +
|-
 +
| 20
 +
| Unknown
 +
|}
 +
 
 +
=== TSEC_SCP_RNG_STAT1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-15
 +
| Unknown
 +
|-
 +
| 16-31
 +
| Unknown
 +
|}
 +
 
 +
=== TSEC_SCP_IRQSTAT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| [[#RND|RND]] ready
 +
|-
 +
| 8
 +
| ACL error
 +
|-
 +
| 12
 +
| SEC error
 +
|-
 +
| 16
 +
| [[#CMD|CMD]] error
 +
|-
 +
| 20
 +
| Single step
 +
|-
 +
| 24
 +
| [[#RND|RND]] operation
 +
|-
 +
| 28
 +
| Timeout
 +
|}
 +
 
 +
Used for getting the status of crypto IRQs.
 +
 
 +
=== TSEC_SCP_IRQMASK ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| [[#RND|RND]] ready
 +
|-
 +
| 8
 +
| ACL error
 +
|-
 +
| 12
 +
| SEC error
 +
|-
 +
| 16
 +
| [[#CMD|CMD]] error
 +
|-
 +
| 20
 +
| Single step
 +
|-
 +
| 24
 +
| [[#RND|RND]] operation
 +
|-
 +
| 28
 +
| Timeout
 +
|}
 +
 
 +
Used for getting the value of the mask for crypto IRQs.
 +
 
 +
=== TSEC_SCP_ACL_ERR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Writing to a crypto register without the correct ACL
 +
|-
 +
| 4
 +
| Reading from a crypto register without the correct ACL
 +
|-
 +
| 8
 +
| Invalid ACL change (cchmod)
 +
|-
 +
| 31
 +
| ACL error occurred
 +
|}
 +
 
 +
Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|ACL error]] IRQ.
 +
 
 +
=== TSEC_SCP_SEC_ERR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Unknown
 +
|-
 +
| 1-2
 +
| Unknown
 +
|-
 +
| 4
 +
| Unknown
 +
|-
 +
| 5-6
 +
| Unknown
 +
|-
 +
| 16
 +
| Unknown
 +
|-
 +
| 17-18
 +
| Unknown
 +
|-
 +
| 20
 +
| Unknown
 +
|-
 +
| 21-22
 +
| Unknown
 +
|-
 +
| 24
 +
| Unknown
 +
|-
 +
| 25-26
 +
| Unknown
 +
|-
 +
| 31
 +
| SEC error occurred
 +
|}
 +
 
 +
=== TSEC_SCP_CMD_ERR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Invalid [[#CMD|CMD]] command
 +
|-
 +
| 4
 +
| Empty [[#SEQ|SEQ]] sequence
 +
|-
 +
| 8
 +
| [[#SEQ|SEQ]] sequence is too long
 +
|-
 +
| 12
 +
| [[#SEQ|SEQ]] sequence was not finished
 +
|-
 +
| 16
 +
| Forbidden signature operation (csigcmp, csigenc or csigclr in NS mode)
 +
|-
 +
| 20
 +
| Invalid signature operation (csigcmp in HS mode)
 +
|-
 +
| 24
 +
| Forbidden ACL change (cchmod in NS mode)
 +
|}
 +
 
 +
Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|CMD error]] IRQ.
 +
 
 +
=== TSEC_SCP_RND_CTL0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| [[#RND|RND]] clock trigger lower limit
 +
|}
 +
 
 +
=== TSEC_SCP_RND_CTL1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-15
 +
| [[#RND|RND]] clock trigger upper limit
 +
|-
 +
| 16-31
 +
| [[#RND|RND]] clock trigger mask
 +
|}
 +
 
 +
=== TSEC_TFBIF_CTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_CTL_CLR_BWCOUNT
 +
|-
 +
| 1
 +
| TSEC_TFBIF_CTL_ENABLE
 +
|-
 +
| 2
 +
| TSEC_TFBIF_CTL_CLR_IDLEWDERR
 +
|-
 +
| 3
 +
| TSEC_TFBIF_CTL_RESET
 +
|-
 +
| 4
 +
| TSEC_TFBIF_CTL_IDLE
 +
|-
 +
| 5
 +
| TSEC_TFBIF_CTL_IDLEWDERR
 +
|-
 +
| 6
 +
| TSEC_TFBIF_CTL_SRTOUT
 +
|-
 +
| 7
 +
| TSEC_TFBIF_CTL_CLR_SRTOUT
 +
|-
 +
| 8-11
 +
| TSEC_TFBIF_CTL_SRTOVAL
 +
|-
 +
| 12
 +
| TSEC_TFBIF_CTL_VPR
 +
|}
 +
 
 +
=== TSEC_TFBIF_MCCIF_FIFOCTRL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVERRIDE
 +
|-
 +
| 1
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVERRIDE
 +
|-
 +
| 2
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRCL_MCLE2X
 +
|-
 +
| 3
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDMC_RDFAST
 +
|-
 +
| 4
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRMC_CLLE2X
 +
|-
 +
| 5
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDCL_RDFAST
 +
|-
 +
| 6
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_CCLK_OVERRIDE
 +
|-
 +
| 7
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVR_MODE
 +
|-
 +
| 8
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVR_MODE
 +
|}
 +
 
 +
=== TSEC_TFBIF_THROTTLE ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-11
 +
| TSEC_TFBIF_THROTTLE_BUCKET_SIZE
 +
|-
 +
| 16-27
 +
| TSEC_TFBIF_THROTTLE_LEAK_COUNT
 +
|-
 +
| 30-31
 +
| TSEC_TFBIF_THROTTLE_LEAK_SIZE
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_STAT0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_DBG_STAT0_1K_TRANSFER
 +
|-
 +
| 1
 +
| TSEC_TFBIF_DBG_STAT0_RREQ_ISSUED
 +
|-
 +
| 2
 +
| TSEC_TFBIF_DBG_STAT0_WREQ_ISSUED
 +
|-
 +
| 3
 +
| TSEC_TFBIF_DBG_STAT0_TAGQ_ISSUED
 +
|-
 +
| 4
 +
| TSEC_TFBIF_DBG_STAT0_STALL_RDATQ
 +
|-
 +
| 5
 +
| TSEC_TFBIF_DBG_STAT0_STALL_RACKQ
 +
|-
 +
| 6
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WREQQ
 +
|-
 +
| 7
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WDATQ
 +
|-
 +
| 8
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WACKQ
 +
|-
 +
| 9
 +
| TSEC_TFBIF_DBG_STAT0_STALL_RREQ_PENDING
 +
|-
 +
| 10
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WREQ_PENDING
 +
|-
 +
| 11
 +
| TSEC_TFBIF_DBG_STAT0_STALL_MREQ
 +
|-
 +
| 12
 +
| TSEC_TFBIF_DBG_STAT0_ENGINE_IDLE
 +
|-
 +
| 13
 +
| TSEC_TFBIF_DBG_STAT0_RMCCIF_IDLE
 +
|-
 +
| 14
 +
| TSEC_TFBIF_DBG_STAT0_WMCCIF_IDLE
 +
|-
 +
| 15
 +
| TSEC_TFBIF_DBG_STAT0_CSB_IDLE
 +
|-
 +
| 16
 +
| TSEC_TFBIF_DBG_STAT0_RU_IDLE
 +
|-
 +
| 17
 +
| TSEC_TFBIF_DBG_STAT0_WU_IDLE
 +
|-
 +
| 19
 +
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_ACTIVE
 +
|-
 +
| 20
 +
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_MCB
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_STAT1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_DBG_STAT1_DATA
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_RDCOUNT_LO ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_DBG_RDCOUNT_LO_DATA
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_RDCOUNT_HI ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_DBG_RDCOUNT_HI_DATA
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_WRCOUNT_LO ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_DBG_WRCOUNT_LO_DATA
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_WRCOUNT_HI ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_DBG_WRCOUNT_HI_DATA
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_R32COUNT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_DBG_R32COUNT_DATA
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_R64COUNT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_DBG_R64COUNT_DATA
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_R128COUNT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_DBG_R128COUNT_DATA
 +
|}
 +
 
 +
=== TSEC_TFBIF_MCCIF_FIFOCTRL1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-15
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SRD2MC_REORDER_DEPTH_LIMIT
 +
|-
 +
| 16-31
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SWR2MC_REORDER_DEPTH_LIMIT
 +
|}
 +
 
 +
=== TSEC_TFBIF_WRR_RDP ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-15
 +
| TSEC_TFBIF_WRR_RDP_EXT_WEIGHT
 +
|-
 +
| 16-31
 +
| TSEC_TFBIF_WRR_RDP_INT_WEIGHT
 +
|}
 +
 
 +
=== TSEC_TFBIF_SPROT_EMEM ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to external memory regions. Accessible in HS mode only.
 +
 
 +
=== TSEC_TFBIF_TRANSCFG ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_TRANSCFG_ATT0_SWID
 +
|-
 +
| 4
 +
| TSEC_TFBIF_TRANSCFG_ATT1_SWID
 +
|-
 +
| 8
 +
| TSEC_TFBIF_TRANSCFG_ATT2_SWID
 +
|-
 +
| 12
 +
| TSEC_TFBIF_TRANSCFG_ATT3_SWID
 +
|-
 +
| 16
 +
| TSEC_TFBIF_TRANSCFG_ATT4_SWID
 +
|-
 +
| 20
 +
| TSEC_TFBIF_TRANSCFG_ATT5_SWID
 +
|-
 +
| 24
 +
| TSEC_TFBIF_TRANSCFG_ATT6_SWID
 +
|-
 +
| 28
 +
| TSEC_TFBIF_TRANSCFG_ATT7_SWID
 +
|}
 +
 
 +
Configures the software ID per CTXDMA port for memory transactions. Software ID 0 (HW_SWID) forces all transactions to go through the SMMU while software ID 1 (PHY_SWID) bypasses it. Accessible in HS mode only.
 +
 
 +
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
 +
 
 +
=== TSEC_TFBIF_REGIONCFG ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-2
 +
| TSEC_TFBIF_REGIONCFG_T0_APERT_ID
 +
|-
 +
| 3
 +
| TSEC_TFBIF_REGIONCFG_T0_VPR
 +
|-
 +
| 4-6
 +
| TSEC_TFBIF_REGIONCFG_T1_APERT_ID
 +
|-
 +
| 7
 +
| TSEC_TFBIF_REGIONCFG_T1_VPR
 +
|-
 +
| 8-10
 +
| TSEC_TFBIF_REGIONCFG_T2_APERT_ID
 +
|-
 +
| 11
 +
| TSEC_TFBIF_REGIONCFG_T2_VPR
 +
|-
 +
| 12-14
 +
| TSEC_TFBIF_REGIONCFG_T3_APERT_ID
 +
|-
 +
| 15
 +
| TSEC_TFBIF_REGIONCFG_T3_VPR
 +
|-
 +
| 16-18
 +
| TSEC_TFBIF_REGIONCFG_T4_APERT_ID
 +
|-
 +
| 19
 +
| TSEC_TFBIF_REGIONCFG_T4_VPR
 +
|-
 +
| 20-22
 +
| TSEC_TFBIF_REGIONCFG_T5_APERT_ID
 +
|-
 +
| 23
 +
| TSEC_TFBIF_REGIONCFG_T5_VPR
 +
|-
 +
| 24-26
 +
| TSEC_TFBIF_REGIONCFG_T6_APERT_ID
 +
|-
 +
| 27
 +
| TSEC_TFBIF_REGIONCFG_T6_VPR
 +
|-
 +
| 28-30
 +
| TSEC_TFBIF_REGIONCFG_T7_APERT_ID
 +
|-
 +
| 31
 +
| TSEC_TFBIF_REGIONCFG_T7_VPR
 +
|}
 +
 
 +
Configures the aperture ID and VPR mode per CTXDMA port for memory region accessing. Accessible in HS mode only.
 +
 
 +
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
 +
 
 +
=== TSEC_TFBIF_ACTMON_ACTIVE_MASK ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_STARVED_MC
 +
|-
 +
| 1
 +
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_STALLED_MC
 +
|-
 +
| 2
 +
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED_MC
 +
|-
 +
| 3
 +
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_ACTIVE
 +
|}
 +
 
 +
Takes the memory access mask for the Activity Monitor. Disconnected on the TSEC.
 +
 
 +
=== TSEC_TFBIF_ACTMON_ACTIVE_BORPS ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STARVED_MC_POLARITY
 +
|-
 +
| 1
 +
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STARVED_MC_OPERATION
 +
|-
 +
| 2
 +
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STALLED_MC_POLARITY
 +
|-
 +
| 3
 +
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STALLED_MC_OPERATION
 +
|-
 +
| 4
 +
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_DELAYED_MC_POLARITY
 +
|-
 +
| 5
 +
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_DELAYED_MC_OPERATION
 +
|-
 +
| 6
 +
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE_POLARITY
 +
|-
 +
| 7
 +
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE_OPERATION
 +
|}
 +
 
 +
Takes the billions of records per second count for the Activity Monitor. Disconnected on the TSEC.
 +
 
 +
=== TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT_VAL
 +
|}
 +
 
 +
Controls the Activity Monitor. Disconnected on the TSEC.
 +
 
 +
=== TSEC_TFBIF_ACTMON_MCB_MASK ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_ACTMON_MCB_MASK_STARVED_MC
 +
|-
 +
| 1
 +
| TSEC_TFBIF_ACTMON_MCB_MASK_STALLED_MC
 +
|-
 +
| 2
 +
| TSEC_TFBIF_ACTMON_MCB_MASK_DELAYED_MC
 +
|-
 +
| 3
 +
| TSEC_TFBIF_ACTMON_MCB_MASK_ACTIVE
 +
|}
 +
 
 +
Disconnected on the TSEC.
 +
 
 +
=== TSEC_TFBIF_ACTMON_MCB_BORPS ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_ACTMON_MCB_BORPS_STARVED_MC_POLARITY
 +
|-
 +
| 1
 +
| TSEC_TFBIF_ACTMON_MCB_BORPS_STARVED_MC_OPERATION
 +
|-
 +
| 2
 +
| TSEC_TFBIF_ACTMON_MCB_BORPS_STALLED_MC_POLARITY
 +
|-
 +
| 3
 +
| TSEC_TFBIF_ACTMON_MCB_BORPS_STALLED_MC_OPERATION
 +
|-
 +
| 4
 +
| TSEC_TFBIF_ACTMON_MCB_BORPS_DELAYED_MC_POLARITY
 +
|-
 +
| 5
 +
| TSEC_TFBIF_ACTMON_MCB_BORPS_DELAYED_MC_OPERATION
 +
|-
 +
| 6
 +
| TSEC_TFBIF_ACTMON_MCB_BORPS_ACTIVE_POLARITY
 +
|-
 +
| 7
 +
| TSEC_TFBIF_ACTMON_MCB_BORPS_ACTIVE_OPERATION
 +
|}
 +
 
 +
Disconnected on the TSEC.
 +
 
 +
=== TSEC_TFBIF_ACTMON_MCB_WEIGHT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_TFBIF_ACTMON_MCB_WEIGHT_VAL
 +
|}
 +
 
 +
Disconnected on the TSEC.
 +
 
 +
=== TSEC_TFBIF_THI_TRANSPROP ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-6
 +
| TSEC_TFBIF_THI_TRANSPROP_STREAMID0
 +
|-
 +
| 8-14
 +
| TSEC_TFBIF_THI_TRANSPROP_STREAMID1
 +
|-
 +
| 16
 +
| TSEC_TFBIF_THI_TRANSPROP_TZ_AUTH
 +
|}
 +
 
 +
=== TSEC_CG ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-5
 +
| TSEC_CG_IDLE_CG_DLY_CNT
 +
|-
 +
| 6
 +
| TSEC_CG_IDLE_CG_EN
 +
|-
 +
| 16-18
 +
| TSEC_CG_WAKEUP_DLY_CNT
 +
|-
 +
| 19
 +
| TSEC_CG_WAKEUP_DLY_EN
 +
|}
 +
 
 +
=== TSEC_BAR0_CTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_BAR0_CTL_READ
 +
|-
 +
| 1
 +
| TSEC_BAR0_CTL_WRITE
 +
|-
 +
| 4-7
 +
| TSEC_BAR0_CTL_BYTE_MASK
 +
|-
 +
| 12-13
 +
| TSEC_BAR0_CTL_STATUS
 +
0: Idle
 +
1: Busy
 +
2: Error
 +
3: Disabled
 +
|-
 +
| 16-17
 +
| TSEC_BAR0_CTL_SEC_MODE
 +
0: None
 +
1: Invalid
 +
2: Light Secure
 +
3: Heavy Secure
 +
|-
 +
| 31
 +
| TSEC_BAR0_CTL_INIT
 +
|}
 +
 
 +
Controls DMA transfers between TSEC and HOST1X (master and clients).
 +
 
 +
Starting a transfer over BAR0 automatically sets TSEC_BAR0_CTL_SEC_MODE to the current Falcon security mode. Once set, any attempts to start a transfer from a lower security level will fail.
 +
 
 +
=== TSEC_BAR0_ADDR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_BAR0_ADDR_VAL
 +
|}
 +
 
 +
Takes the address for DMA transfers between TSEC and HOST1X (master and clients).
 +
 
 +
=== TSEC_BAR0_DATA ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_BAR0_DATA_VAL
 +
|}
 +
 
 +
Takes the data for DMA transfers between TSEC and HOST1X (master and clients).
 +
 
 +
=== TSEC_BAR0_TIMEOUT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_BAR0_TIMEOUT_VAL
 +
|}
 +
 
 +
Takes the timeout value for DMA transfers between TSEC and HOST1X (master and clients).
 +
 
 +
=== TSEC_TEGRA_CTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 16
 +
| TSEC_TEGRA_CTL_TKFI_KFUSE
 +
|-
 +
| 17
 +
| TSEC_TEGRA_CTL_TKFI_RESTART_FSM_KFUSE
 +
|-
 +
| 24
 +
| TSEC_TEGRA_CTL_TMPI_FORCE_IDLE_INPUTS_I2C
 +
|-
 +
| 25
 +
| TSEC_TEGRA_CTL_TMPI_RESTART_FSM_HOST1X
 +
|-
 +
| 26
 +
| TSEC_TEGRA_CTL_TMPI_RESTART_FSM_APB
 +
|-
 +
| 27
 +
| TSEC_TEGRA_CTL_TMPI_DISABLE_OUTPUT_I2C
 +
|}
 +
 
 +
== Falcon ==
 +
"Falcon" (FAst Logic CONtroller) is a proprietary general purpose CPU which can be found inside various hardware blocks that require some sort of logic processing such as TSEC (TSECA and TSECB), NVDEC, NVENC, NVJPG, VIC, GPU PMU and XUSB.
 +
 
 +
=== Processor Registers ===
 +
A total of 32 processor registers are available in the Falcon CPU.
 +
 
 +
==== REG0-REG15 ====
 +
These are 16 32-bit GPRs (general purpose registers).
 +
 
 +
==== IV0 ====
 +
This is a SPR (special purpose register) that holds the address for interrupt vector 0. Only bits 0 to 15 are used.
 +
 
 +
==== IV1 ====
 +
This is a SPR (special purpose register) that holds the address for interrupt vector 1. Only bits 0 to 15 are used.
 +
 
 +
==== IV2 ====
 +
This is a SPR (special purpose register) that holds the address for interrupt vector 2. This register is considered "UNDEFINED" and appears to be unused.
 +
 
 +
==== EV ====
 +
This is a SPR (special purpose register) that holds the address for the exception vector. Only bits 0 to 15 are used.
 +
 
 +
Alternative name (envytools): "tv".
 +
 
 +
==== SP ====
 +
This is a SPR (special purpose register) that holds the current stack pointer. Only bits 0 to 15 are used.
 +
 
 +
==== PC ====
 +
This is a SPR (special purpose register) that holds the current program counter. Only bits 0 to 15 are used.
 +
 
 +
==== IMB ====
 +
This is a SPR (special purpose register) that holds the external base address for IMEM transfers.
 +
 
 +
Alternative name (envytools): "xcbase".
 +
 
 +
==== DMB ====
 +
This is a SPR (special purpose register) that holds the external base address for DMEM transfers.
 +
 
 +
Alternative name (envytools): "xdbase".
 +
 
 +
==== CSW ====
 +
This is a SPR (special purpose register) that holds various flag bits.
 +
 
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-7 || General purpose predicates
 +
|-
 +
| 8 || ALU carry flag
 +
|-
 +
| 9 || ALU signed overflow flag
 +
|-
 +
| 10 || ALU sign flag
 +
|-
 +
| 11 || ALU zero flag
 +
|-
 +
| 16 || Interrupt 0 enable
 +
|-
 +
| 17 || Interrupt 1 enable
 +
|-
 +
| 18 || Interrupt 2 enable (undefined)
 +
|-
 +
| 20 || Interrupt 0 saved enable
 +
|-
 +
| 21 || Interrupt 1 saved enable
 +
|-
 +
| 22 || Interrupt 2 saved enable (undefined)
 +
|-
 +
| 24 || Exception active
 +
|-
 +
| 26-31 || Unknown
 +
|}
 +
 
 +
Alternative name (envytools): "flags".
 +
 
 +
==== CCR ====
 +
This is a SPR (special purpose register) that holds configuration bits for the SCP DMA override functionality. The value of this register is set using the "cxset" instruction which provides a way to change the behavior of a variable amount of successively executed DMA-related instructions ("xdwait", "xdst" and "xdld").
 +
 
 +
{| class=wikitable
 +
! Bits || Description
 +
|-
 +
| 0-4 || Number of instructions the override is valid for (0x1F means infinite)
 +
|-
 +
| 5 || Crypto source/destination select
 +
0: Crypto register
 +
1: Crypto stream
 +
|-
 +
| 6 || Bypass mode
 +
0: Disabled
 +
1: Enabled
 +
|-
 +
| 7 || Internal memory select
 +
0: DMEM
 +
1: IMEM
 +
|}
 +
 
 +
Alternative name (envytools): "cx".
 +
 
 +
==== SEC ====
 +
This is a SPR (special purpose register) that holds configuration bits for the SCP authentication process.
 +
 
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-7 || Start of region to authenticate (in pages of 0x100 bytes)
 +
|-
 +
| 16 || Force secure DMA transfers
 +
|-
 +
| 17 || Decrypt region to authenticate
 +
|-
 +
| 18 || Signature check passed
 +
|-
 +
| 19 || Suppress interrupts and exceptions
 +
|-
 +
| 24-31 || Size of region to authenticate (in pages of 0x100 bytes)
 +
|}
 +
 
 +
Alternative name (envytools): "cauth".
 +
 
 +
==== CTX ====
 +
This is a SPR (special purpose register) that holds configuration bits for the CTXDMA ports.
 +
 
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-2 || CTXDMA port for code loads (xcld)
 +
|-
 +
| 4-6 || CTXDMA port for code stores (invalid)
 +
|-
 +
| 8-10 || CTXDMA port for data loads (xdld)
 +
|-
 +
| 12-14 || CTXDMA port for data stores (xdst)
 +
|}
 +
 
 +
Alternative name (envytools): "xtargets".
 +
 
 +
==== EXCI ====
 +
This is a SPR (special purpose register) that holds information on raised exceptions.
 +
 
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-19 || Exception PC
 +
|-
 +
| 20-23 || Exception cause
 +
|}
 +
 
 +
Alternative name (envytools): "tstatus".
 +
 
 +
==== SEC1 ====
 +
Unknown. Marked as "RESERVED".
 +
 
 +
==== IMB1 ====
 +
Unknown. Marked as "RESERVED".
 +
 
 +
==== DMB1 ====
 +
Unknown. Marked as "RESERVED".
 +
 
 +
=== Heavy Secure Mode ===
 +
==== Entry ====
 +
From non-secure mode, upon jumping to a page marked as secret, a secret fault occurs. This causes the CPU to verify the region specified in $cauth against the MAC loaded in $c6. If the comparison is successful, the valid bit (bit0) is set on all pages in the $cauth region, and $pc is set to the base of the $cauth region. If the comparsion fails, the CPU is halted.
 +
 
 +
==== Exit ====
 +
The CPU automatically goes back to non-secure mode when returning back into non-secret pages. When this happens, the valid bit (bit0) in the TLB flags is cleared for all secret pages.
 +
 
 +
==== Implementation ====
 +
Under certain circumstances, it is possible to observe [[#sigcmp|sigcmp]] being briefly written to [[#TSEC_SCP_CMD|TSEC_SCP_CMD]] as "csigcmp $c4 $c6" while the opcodes in [[#TSEC_SCP_STAT2|TSEC_SCP_STAT2]] are set to "cxsin" and "csigcmp", respectively.
 +
 
 +
Via [[#TSEC_SCP_DBG0|TSEC_SCP_DBG0]] it can be observed that a 3-sized macro sequence is loaded into cs0 during a secure mode transition.
 +
 
 +
== SCP ==
 +
"SCP" (Secure Co-Processor) is a proprietary coprocessor which can be found inside every [[#Falcon|Falcon]] that supports [[#Heavy_Secure_Mode|Heavy Secure Mode]]. On the Tegra X1 these are TSECA, TSECB, NVDEC and the GPU's PMU.
 +
 
 +
=== Hardware ===
 +
SCP is subdivided into several specialized hardware blocks and interfaces.
 +
 
 +
==== LOAD ====
 +
Block for handling memory reads from SCP to Falcon. It communicates with Falcon over a dedicated interface.
 +
 
 +
The interface can be enabled or disabled by register [[#TSEC_SCP_CTL0|TSEC_SCP_CTL0]].
 +
 
 +
==== STORE ====
 +
Block for handling memory writes from Falcon to SCP. It communicates with Falcon over a dedicated interface.
 +
 
 +
The interface can be enabled or disabled by register [[#TSEC_SCP_CTL0|TSEC_SCP_CTL0]].
 +
 
 +
==== CMD ====
 +
Block for translating Falcon crypto operands into SCP commands. It communicates with Falcon over a dedicated interface.
 +
 
 +
The interface can be enabled or disabled by register [[#TSEC_SCP_CTL0|TSEC_SCP_CTL0]]. The status of the current command is reported through register [[#TSEC_SCP_CMD|TSEC_SCP_CMD]].
 +
 
 +
==== SEQ ====
 +
Block for recording and executing sequences of crypto operations in the form of macros.
 +
 
 +
Can be enabled or disabled by register [[#TSEC_SCP_CTL0|TSEC_SCP_CTL0]].
 +
 
 +
==== CTL ====
 +
Overseer block for controlling certain SCP features.
 +
 
 +
Can be enabled or disabled by register [[#TSEC_SCP_CTL0|TSEC_SCP_CTL0]].
 +
 
 +
Registers [[#TSEC_SCP_CTL_STAT|TSEC_SCP_CTL_STAT]], [[#TSEC_SCP_CTL_LOCK|TSEC_SCP_CTL_LOCK]], [[#TSEC_SCP_CTL_SCP|TSEC_SCP_CTL_SCP]], [[#TSEC_SCP_CTL_PKEY|TSEC_SCP_CTL_PKEY]] and [[#TSEC_SCP_CTL_DBG|TSEC_SCP_CTL_DBG]] refer to this block.
 +
 
 +
==== AES ====
 +
Block for providing AES-128-ECB functionality.
 +
 
 +
==== RNG ====
 +
Block for encapsulating and controlling the internal random number generator.
 +
 
 +
Can be enabled or disabled by register [[#TSEC_SCP_CTL1|TSEC_SCP_CTL1]] and reports the status of the internal random number generator through registers [[#TSEC_SCP_RNG_STAT0|TSEC_SCP_RNG_STAT0]] and [[#TSEC_SCP_RNG_STAT1|TSEC_SCP_RNG_STAT1]].
 +