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TSEC (view source)

Revision as of 18:49, 23 August 2019

11,408 bytes added ,  18:49, 23 August 2019
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Line 8: Line 8:     
Registers from 0x54501000 to 0x54502000 are a MMIO window for communicating with the Falcon microprocessor. From this range, the subset of registers from 0x54501400 to 0x54501FE8 are specific to the TSEC and are subdivided into:
 
Registers from 0x54501000 to 0x54502000 are a MMIO window for communicating with the Falcon microprocessor. From this range, the subset of registers from 0x54501400 to 0x54501FE8 are specific to the TSEC and are subdivided into:
−
* 0x54501400 to 0x54501500: SCP (Secure Crypto Processor?).
+
* 0x54501400 to 0x54501500: SCP (Secure Co-Processor).
 
* 0x54501500 to 0x54501600: TRNG (True Random Number Generator).
 
* 0x54501500 to 0x54501600: TRNG (True Random Number Generator).
 
* 0x54501600 to 0x54501700: TFBIF (Tegra Framebuffer Interface) and CG (Clock Gate).
 
* 0x54501600 to 0x54501700: TFBIF (Tegra Framebuffer Interface) and CG (Clock Gate).
−
* 0x54501700 to 0x54501800: DMA.
+
* 0x54501700 to 0x54501800: BAR0.
 
* 0x54501800 to 0x54501900: TEGRA (miscellaneous interfaces).  
 
* 0x54501800 to 0x54501900: TEGRA (miscellaneous interfaces).  
   Line 21: Line 21:  
| TSEC_THI_INCR_SYNCPT
 
| TSEC_THI_INCR_SYNCPT
 
| 0x54500000
 
| 0x54500000
 +
| 0x04
 +
|-
 +
| TSEC_THI_INCR_SYNCPT_CTRL
 +
| 0x54500004
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 33: Line 37:  
| TSEC_THI_CTXSW
 
| TSEC_THI_CTXSW
 
| 0x54500020
 
| 0x54500020
 +
| 0x04
 +
|-
 +
| TSEC_THI_CTXSW_NEXT
 +
| 0x54500024
 
| 0x04
 
| 0x04
 
|-
 
|-
 
| TSEC_THI_CONT_SYNCPT_EOF
 
| TSEC_THI_CONT_SYNCPT_EOF
 
| 0x54500028
 
| 0x54500028
 +
| 0x04
 +
|-
 +
| TSEC_THI_CONT_SYNCPT_L1
 +
| 0x5450002C
 +
| 0x04
 +
|-
 +
| TSEC_THI_STREAMID0
 +
| 0x54500030
 +
| 0x04
 +
|-
 +
| TSEC_THI_STREAMID1
 +
| 0x54500034
 +
| 0x04
 +
|-
 +
| TSEC_THI_THI_SEC
 +
| 0x54500038
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 45: Line 69:  
| [[#TSEC_THI_METHOD1|TSEC_THI_METHOD1]]
 
| [[#TSEC_THI_METHOD1|TSEC_THI_METHOD1]]
 
| 0x54500044
 
| 0x54500044
 +
| 0x04
 +
|-
 +
| TSEC_THI_CONTEXT_SWITCH
 +
| 0x54500060
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 55: Line 83:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_THI_SLCG_STATUS
+
| TSEC_THI_CONFIG0
 +
| 0x54500080
 +
| 0x04
 +
|-
 +
| TSEC_THI_DBG_MISC
 
| 0x54500084
 
| 0x54500084
 
| 0x04
 
| 0x04
Line 103: Line 135:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_GPTMR_PERIOD
+
| FALCON_GPTMRINT
 
| 0x54501020
 
| 0x54501020
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_GPTMR_TIME
+
| FALCON_GPTMRVAL
 
| 0x54501024
 
| 0x54501024
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_GPTMR_ENABLE
+
| FALCON_GPTMRCTL
 
| 0x54501028
 
| 0x54501028
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_TIME_LOW
+
| FALCON_PTIMER0
 
| 0x5450102C
 
| 0x5450102C
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_TIME_HIGH
+
| FALCON_PTIMER1
 
| 0x54501030
 
| 0x54501030
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_WDTMR_TIME
+
| FALCON_WDTMRVAL
 
| 0x54501034
 
| 0x54501034
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_WDTMR_ENABLE
+
| FALCON_WDTMRCTL
 
| 0x54501038
 
| 0x54501038
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_3C
+
| [[#FALCON_IRQDEST2|FALCON_IRQDEST2]]
 
| 0x5450103C
 
| 0x5450103C
 
| 0x04
 
| 0x04
Line 159: Line 191:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_CMDCTX
+
| FALCON_CTXACK
 
| 0x54501058
 
| 0x54501058
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_STATUS_MASK
+
| FALCON_FHSTATE
 
| 0x5450105C
 
| 0x5450105C
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_VM_SUPERVISOR
+
| FALCON_PRIVSTATE
 
| 0x54501060
 
| 0x54501060
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_MTHD_DATA
+
| FALCON_MTHDDATA
 
| 0x54501064
 
| 0x54501064
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_MTHD_CMD
+
| FALCON_MTHDID
 
| 0x54501068
 
| 0x54501068
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_MTHD_DATA_WR
+
| FALCON_MTHDWDAT
 
| 0x5450106C
 
| 0x5450106C
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_MTHD_OCCUPIED
+
| FALCON_MTHDCOUNT
 
| 0x54501070
 
| 0x54501070
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_MTHD_ACK
+
| FALCON_MTHDPOP
 
| 0x54501074
 
| 0x54501074
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_MTHD_LIMIT
+
| FALCON_MTHDRAMSZ
 
| 0x54501078
 
| 0x54501078
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_SUBENGINE_RESET
+
| FALCON_SFTRESET
 
| 0x5450107C
 
| 0x5450107C
 
| 0x04
 
| 0x04
Line 207: Line 239:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_PM_SIGNAL
+
| FALCON_SOFT_PM
 
| 0x54501088
 
| 0x54501088
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_PM_MODE
+
| FALCON_SOFT_MODE
 
| 0x5450108C
 
| 0x5450108C
 
| 0x04
 
| 0x04
Line 223: Line 255:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_BREAKPOINT0
+
| FALCON_IBRKPT1
 
| 0x54501098
 
| 0x54501098
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_BREAKPOINT1
+
| FALCON_IBRKPT2
 
| 0x5450109C
 
| 0x5450109C
 
| 0x04
 
| 0x04
Line 239: Line 271:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_PM_SEL
+
| FALCON_PMM
 
| 0x545010A8
 
| 0x545010A8
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_HOST_IO_INDEX
+
| FALCON_ADDR
 
| 0x545010AC
 
| 0x545010AC
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_BREAKPOINT2
+
| FALCON_IBRKPT3
 
| 0x545010B0
 
| 0x545010B0
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_BREAKPOINT3
+
| FALCON_IBRKPT4
 
| 0x545010B4
 
| 0x545010B4
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_BREAKPOINT4
+
| FALCON_IBRKPT5
 
| 0x545010B8
 
| 0x545010B8
 
| 0x04
 
| 0x04
Line 263: Line 295:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_D4
+
| [[#FALCON_SVEC_SPR|FALCON_SVEC_SPR]]
 
| 0x545010D4
 
| 0x545010D4
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_D8
+
| [[#FALCON_RSTAT0|FALCON_RSTAT0]]
 
| 0x545010D8
 
| 0x545010D8
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_DC
+
| [[#FALCON_RSTAT3|FALCON_RSTAT3]]
 
| 0x545010DC
 
| 0x545010DC
 
| 0x04
 
| 0x04
Line 311: Line 343:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_DMATRFSTAT|FALCON_DMATRFSTAT]]
+
| [[#FALCON_DMAPOLL_FB|FALCON_DMAPOLL_FB]]
 
| 0x54501120
 
| 0x54501120
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_CRYPTTRFSTAT|FALCON_CRYPTTRFSTAT]]
+
| [[#FALCON_DMAPOLL_CP|FALCON_DMAPOLL_CP]]
 
| 0x54501124
 
| 0x54501124
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_CPUSTAT
+
| FALCON_DBG_STATE
 
| 0x54501128
 
| 0x54501128
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_HWCFG2|FALCON_HWCFG2]]
+
| [[#FALCON_HWCFG1|FALCON_HWCFG1]]
 
| 0x5450112C
 
| 0x5450112C
 
| 0x04
 
| 0x04
Line 329: Line 361:  
| FALCON_CPUCTL_ALIAS
 
| FALCON_CPUCTL_ALIAS
 
| 0x54501130
 
| 0x54501130
 +
| 0x04
 +
|-
 +
| FALCON_STACKCFG
 +
| 0x54501138
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 363: Line 399:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_EXTERRWIN
+
| FALCON_CMEMBASE
 
| 0x54501160
 
| 0x54501160
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_EXTERRCFG
+
| FALCON_DMEMAPERT
 
| 0x54501164
 
| 0x54501164
 
| 0x04
 
| 0x04
Line 383: Line 419:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_IMEMC|FALCON_IMEMC]]
+
| [[#FALCON_IMEMC0|FALCON_IMEMC0]]
 
| 0x54501180
 
| 0x54501180
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_IMEMD|FALCON_IMEMD]]
+
| [[#FALCON_IMEMD0|FALCON_IMEMD0]]
 
| 0x54501184
 
| 0x54501184
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_IMEMT|FALCON_IMEMT]]
+
| [[#FALCON_IMEMT0|FALCON_IMEMT0]]
 
| 0x54501188
 
| 0x54501188
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_DMEMC0|FALCON_DMEMC0]]
+
| FALCON_IMEMC1
−
| 0x545011C0
+
| 0x54501190
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_DMEMD0|FALCON_DMEMD0]]
+
| FALCON_IMEMD1
−
| 0x545011C4
+
| 0x54501194
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DMEMC1
+
| FALCON_IMEMT1
−
| 0x545011C8
+
| 0x54501198
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DMEMD1
+
| FALCON_IMEMC2
−
| 0x545011CC
+
| 0x545011A0
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DMEMC2
+
| FALCON_IMEMD2
−
| 0x545011D0
+
| 0x545011A4
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DMEMD2
+
| FALCON_IMEMT2
−
| 0x545011D4
+
| 0x545011A8
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DMEMC3
+
| FALCON_IMEMC3
−
| 0x545011D8
+
| 0x545011B0
 +
| 0x04
 +
|-
 +
| FALCON_IMEMD3
 +
| 0x545011B4
 +
| 0x04
 +
|-
 +
| FALCON_IMEMT3
 +
| 0x545011B8
 +
| 0x04
 +
|-
 +
| [[#FALCON_DMEMC0|FALCON_DMEMC0]]
 +
| 0x545011C0
 +
| 0x04
 +
|-
 +
| [[#FALCON_DMEMD0|FALCON_DMEMD0]]
 +
| 0x545011C4
 +
| 0x04
 +
|-
 +
| FALCON_DMEMC1
 +
| 0x545011C8
 +
| 0x04
 +
|-
 +
| FALCON_DMEMD1
 +
| 0x545011CC
 +
| 0x04
 +
|-
 +
| FALCON_DMEMC2
 +
| 0x545011D0
 +
| 0x04
 +
|-
 +
| FALCON_DMEMD2
 +
| 0x545011D4
 +
| 0x04
 +
|-
 +
| FALCON_DMEMC3
 +
| 0x545011D8
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 463: Line 535:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_ICD_ADDR
+
| [[#FALCON_ICD_ADDR|FALCON_ICD_ADDR]]
 
| 0x54501204
 
| 0x54501204
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_ICD_WDATA
+
| [[#FALCON_ICD_WDATA|FALCON_ICD_WDATA]]
 
| 0x54501208
 
| 0x54501208
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_ICD_RDATA
+
| [[#FALCON_ICD_RDATA|FALCON_ICD_RDATA]]
 
| 0x5450120C
 
| 0x5450120C
 
| 0x04
 
| 0x04
Line 479: Line 551:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_SCTL_STAT|FALCON_SCTL_STAT]]
+
| [[#FALCON_SSTAT|FALCON_SSTAT]]
 
| 0x54501244
 
| 0x54501244
 
| 0x04
 
| 0x04
Line 531: Line 603:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_2C0
+
| FALCON_DMAINFO_FINISHED_FBRD_LOW
 
| 0x545012C0
 
| 0x545012C0
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_2C4
+
| FALCON_DMAINFO_FINISHED_FBRD_HIGH
 
| 0x545012C4
 
| 0x545012C4
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_2C8
+
| FALCON_DMAINFO_FINISHED_FBWR_LOW
 
| 0x545012C8
 
| 0x545012C8
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_2CC
+
| FALCON_DMAINFO_FINISHED_FBWR_HIGH
 
| 0x545012CC
 
| 0x545012CC
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_2E0
+
| FALCON_DMAINFO_CURRENT_FBRD_LOW
−
| 0x545012E0
+
| 0x545012D0
 +
| 0x04
 +
|-
 +
| FALCON_DMAINFO_CURRENT_FBRD_HIGH
 +
| 0x545012D4
 +
| 0x04
 +
|-
 +
| FALCON_DMAINFO_CURRENT_FBWR_LOW
 +
| 0x545012D8
 +
| 0x04
 +
|-
 +
| FALCON_DMAINFO_CURRENT_FBWR_HIGH
 +
| 0x545012DC
 +
| 0x04
 +
|-
 +
| FALCON_DMAINFO_CTL
 +
| 0x545012E0
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 683: Line 771:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TFBIF_UNK_00
+
| [[#TSEC_TFBIF_CTL|TSEC_TFBIF_CTL]]
 
| 0x54501600
 
| 0x54501600
 
| 0x04
 
| 0x04
Line 691: Line 779:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TFBIF_THROTTLE
+
| [[#TSEC_TFBIF_THROTTLE|TSEC_TFBIF_THROTTLE]]
 
| 0x54501608
 
| 0x54501608
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TFBIF_UNK_0C
+
| [[#TSEC_TFBIF_DBG_STAT0|TSEC_TFBIF_DBG_STAT0]]
 
| 0x5450160C
 
| 0x5450160C
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_STAT1
 +
| 0x54501610
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_RDCOUNT_LO
 +
| 0x54501614
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_RDCOUNT_HI
 +
| 0x54501618
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_WRCOUNT_LO
 +
| 0x5450161C
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_WRCOUNT_HI
 +
| 0x54501620
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_R32COUNT
 +
| 0x54501624
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_R64COUNT
 +
| 0x54501628
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_R128COUNT
 +
| 0x5450162C
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 707: Line 827:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TFBIF_UNK_40
+
| TSEC_TFBIF_WRR_RDP
 +
| 0x54501638
 +
| 0x04
 +
|-
 +
| [[#TSEC_TFBIF_SPROT_EMEM|TSEC_TFBIF_SPROT_EMEM]]
 
| 0x54501640
 
| 0x54501640
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_TFBIF_UNK_44|TSEC_TFBIF_UNK_44]]
+
| [[#TSEC_TFBIF_TRANSCFG|TSEC_TFBIF_TRANSCFG]]
 
| 0x54501644
 
| 0x54501644
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_TFBIF_UNK_48|TSEC_TFBIF_UNK_48]]
+
| [[#TSEC_TFBIF_REGIONCFG|TSEC_TFBIF_REGIONCFG]]
 
| 0x54501648
 
| 0x54501648
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_CG|TSEC_CG]]
+
| [[#TSEC_TFBIF_ACTMON_ACTIVE_MASK|TSEC_TFBIF_ACTMON_ACTIVE_MASK]]
−
| 0x545016D0
+
| 0x5450164C
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_DMA_CMD|TSEC_DMA_CMD]]
+
| [[#TSEC_TFBIF_ACTMON_ACTIVE_BORPS|TSEC_TFBIF_ACTMON_ACTIVE_BORPS]]
−
| 0x54501700
+
| 0x54501650
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_DMA_ADDR|TSEC_DMA_ADDR]]
+
| [[#TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT|TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT]]
−
| 0x54501704
+
| 0x54501654
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_DMA_DATA|TSEC_DMA_DATA]]
+
| TSEC_TFBIF_ACTMON_MCB_MASK
−
| 0x54501708
+
| 0x54501660
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_DMA_TIMEOUT|TSEC_DMA_TIMEOUT]]
+
| TSEC_TFBIF_ACTMON_MCB_BORPS
−
| 0x5450170C
+
| 0x54501664
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_ACTMON_MCB_WEIGHT
 +
| 0x54501668
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_THI_TRANSPROP
 +
| 0x54501670
 +
| 0x04
 +
|-
 +
| [[#TSEC_CG|TSEC_CG]]
 +
| 0x545016D0
 +
| 0x04
 +
|-
 +
| [[#TSEC_BAR0_CTL|TSEC_BAR0_CTL]]
 +
| 0x54501700
 +
| 0x04
 +
|-
 +
| [[#TSEC_BAR0_ADDR|TSEC_BAR0_ADDR]]
 +
| 0x54501704
 +
| 0x04
 +
|-
 +
| [[#TSEC_BAR0_DATA|TSEC_BAR0_DATA]]
 +
| 0x54501708
 +
| 0x04
 +
|-
 +
| [[#TSEC_BAR0_TIMEOUT|TSEC_BAR0_TIMEOUT]]
 +
| 0x5450170C
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 804: Line 956:  
!  ID
 
!  ID
 
!  Method
 
!  Method
 +
|-
 +
| 0x100
 +
| NOP
 +
|-
 +
| 0x140
 +
| PM_TRIGGER
 
|-
 
|-
 
| 0x200
 
| 0x200
 
| SET_APPLICATION_ID
 
| SET_APPLICATION_ID
 +
|-
 +
| 0x204
 +
| SET_WATCHDOG_TIMER
 +
|-
 +
| 0x240
 +
| SEMAPHORE_A
 +
|-
 +
| 0x244
 +
| SEMAPHORE_B
 +
|-
 +
| 0x248
 +
| SEMAPHORE_C
 +
|-
 +
| 0x24C
 +
|
 +
|-
 +
| 0x250
 +
|
 
|-
 
|-
 
| 0x300
 
| 0x300
 
| EXECUTE
 
| EXECUTE
 +
|-
 +
| 0x304
 +
| SEMAPHORE_D
 
|-
 
|-
 
| 0x500
 
| 0x500
Line 957: Line 1,136:  
| 0x740
 
| 0x740
 
| [6.0.0+] HDCP_GET_CURRENT_NONCE
 
| [6.0.0+] HDCP_GET_CURRENT_NONCE
 +
|-
 +
| 0x1114
 +
| PM_TRIGGER_END
 
|}
 
|}
   Line 1,013: Line 1,195:  
| 8-15
 
| 8-15
 
| FALCON_IRQSSET_EXT
 
| FALCON_IRQSSET_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQSSET_DMA
 
|}
 
|}
   Line 1,048: Line 1,233:  
| 8-15
 
| 8-15
 
| FALCON_IRQSCLR_EXT
 
| FALCON_IRQSCLR_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQSCLR_DMA
 
|}
 
|}
   Line 1,083: Line 1,271:  
| 8-15
 
| 8-15
 
| FALCON_IRQSTAT_EXT
 
| FALCON_IRQSTAT_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQSTAT_DMA
 
|}
 
|}
   Line 1,093: Line 1,284:  
|-
 
|-
 
| 0
 
| 0
−
| FALCON_IRQMODE_GPTMR
+
| FALCON_IRQMODE_LVL_GPTMR
 
|-
 
|-
 
| 1
 
| 1
−
| FALCON_IRQMODE_WDTMR
+
| FALCON_IRQMODE_LVL_WDTMR
 
|-
 
|-
 
| 2
 
| 2
−
| FALCON_IRQMODE_MTHD
+
| FALCON_IRQMODE_LVL_MTHD
 
|-
 
|-
 
| 3
 
| 3
−
| FALCON_IRQMODE_CTXSW
+
| FALCON_IRQMODE_LVL_CTXSW
 
|-
 
|-
 
| 4
 
| 4
−
| FALCON_IRQMODE_HALT
+
| FALCON_IRQMODE_LVL_HALT
 
|-
 
|-
 
| 5
 
| 5
−
| FALCON_IRQMODE_EXTERR
+
| FALCON_IRQMODE_LVL_EXTERR
 
|-
 
|-
 
| 6
 
| 6
−
| FALCON_IRQMODE_SWGEN0
+
| FALCON_IRQMODE_LVL_SWGEN0
 
|-
 
|-
 
| 7
 
| 7
−
| FALCON_IRQMODE_SWGEN1
+
| FALCON_IRQMODE_LVL_SWGEN1
 
|-
 
|-
 
| 8-15
 
| 8-15
−
| FALCON_IRQMODE_EXT
+
| FALCON_IRQMODE_LVL_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQMODE_LVL_DMA
 
|}
 
|}
   Line 1,153: Line 1,347:  
| 8-15
 
| 8-15
 
| FALCON_IRQMSET_EXT
 
| FALCON_IRQMSET_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQMSET_DMA
 
|}
 
|}
   Line 1,188: Line 1,385:  
| 8-15
 
| 8-15
 
| FALCON_IRQMCLR_EXT
 
| FALCON_IRQMCLR_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQMCLR_DMA
 
|}
 
|}
   Line 1,223: Line 1,423:  
| 8-15
 
| 8-15
 
| FALCON_IRQMASK_EXT
 
| FALCON_IRQMASK_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQMASK_DMA
 
|}
 
|}
   Line 1,285: Line 1,488:  
| 24-31
 
| 24-31
 
| FALCON_IRQDEST_TARGET_EXT
 
| FALCON_IRQDEST_TARGET_EXT
 +
|}
 +
 +
Used for routing Falcon's IRQs.
 +
 +
=== FALCON_IRQDEST2 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| FALCON_IRQDEST2_HOST_DMA
 +
|-
 +
| 16
 +
| FALCON_IRQDEST2_TARGET_DMA
 
|}
 
|}
   Line 1,327: Line 1,544:  
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 +
|-
 +
| 0-15
 +
| FALCON_DEBUG1_MTHD_DRAIN_TIME
 
|-
 
|-
 
| 16
 
| 16
 
| FALCON_DEBUG1_CTXSW_MODE
 
| FALCON_DEBUG1_CTXSW_MODE
 +
|-
 +
| 17
 +
| FALCON_DEBUG1_TRACE_FORMAT
 
|}
 
|}
   Line 1,343: Line 1,566:  
|-
 
|-
 
| 0-19
 
| 0-19
−
| PC that originated the exception
+
| FALCON_EXCI_EXPC
 
|-
 
|-
 
| 20-23
 
| 20-23
−
| Exception type
+
| FALCON_EXCI_EXCAUSE
−
  0x00: Trap 0
+
  0x00: TRAP0
−
  0x01: Trap 1
+
  0x01: TRAP1
−
  0x02: Trap 2
+
  0x02: TRAP2
−
  0x03: Trap 3
+
  0x03: TRAP3
−
  0x08: Invalid opcode
+
  0x08: ILL_INS (invalid opcode)
−
  0x09: Authentication entry
+
  0x09: INV_INS (authentication entry)
−
  0x0A: Page fault (no hit)
+
  0x0A: MISS_INS (page miss)
−
  0x0B: Page fault (multi hit)
+
  0x0B: DHIT_INS (page multiple hit)
−
  0x0F: Breakpoint
+
  0x0F: BRKPT_INS (breakpoint hit)
 
|}
 
|}
    
Contains information about raised exceptions.
 
Contains information about raised exceptions.
   −
=== FALCON_CPUCTL ===
+
=== FALCON_SVEC_SPR ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 18
−
| FALCON_CPUCTL_IINVAL
+
| FALCON_SVEC_SPR_SIGPASS
 +
|}
 +
 
 +
=== FALCON_RSTAT0 ===
 +
Mirror of the ICD status register 0.
 +
 
 +
=== FALCON_RSTAT3 ===
 +
Mirror of the ICD status register 3.
 +
 
 +
=== FALCON_CPUCTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| FALCON_CPUCTL_IINVAL
 
|-
 
|-
 
| 1
 
| 1
Line 1,384: Line 1,622:  
|-
 
|-
 
| 6
 
| 6
−
| FALCON_CPUCTL_CPUCTL_ALIAS_EN
+
| FALCON_CPUCTL_ALIAS_EN
 
|}
 
|}
   Line 1,403: Line 1,641:  
| FALCON_HWCFG_DMEM_SIZE
 
| FALCON_HWCFG_DMEM_SIZE
 
|-
 
|-
−
| 18-25
+
| 18-26
−
| FALCON_HWCFG_MTHD_SIZE
+
| FALCON_HWCFG_METHODFIFO_DEPTH
 
|-
 
|-
−
| 26-31
+
| 27-31
−
| FALCON_HWCFG_DMATRF_SLOTS
+
| FALCON_HWCFG_DMAQUEUE_DEPTH
 
|}
 
|}
   Line 1,474: Line 1,712:  
For transfers to IMEM: the destination physical IMEM page.
 
For transfers to IMEM: the destination physical IMEM page.
   −
=== FALCON_DMATRFSTAT ===
+
=== FALCON_DMAPOLL_FB ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,480: Line 1,718:  
|-
 
|-
 
| 0
 
| 0
−
| FALCON_DMATRFSTAT_PENDING
+
| FALCON_DMAPOLL_FB_FENCE_ACTIVE
 
|-
 
|-
−
| 16-18
+
| 1
−
| FALCON_DMATRFSTAT_NUM_STORES_PENDING
+
| FALCON_DMAPOLL_FB_DMA_ACTIVE
 +
|-
 +
| 4
 +
| FALCON_DMAPOLL_FB_CFG_R_FENCE
 +
|-
 +
| 5
 +
| FALCON_DMAPOLL_FB_CFG_W_FENCE
 +
|-
 +
| 16-23
 +
| FALCON_DMAPOLL_FB_WCOUNT
 
|-
 
|-
−
| 24-26
+
| 24-31
−
| FALCON_DMATRFSTAT_NUM_LOADS_PENDING
+
| FALCON_DMAPOLL_FB_RCOUNT
 
|}
 
|}
   −
=== FALCON_CRYPTTRFSTAT ===
+
Contains the status of a DMA transfer between the Falcon and external memory.
 +
 
 +
=== FALCON_DMAPOLL_CP ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 +
|-
 +
| 0
 +
| FALCON_DMAPOLL_CP_FENCE_ACTIVE
 
|-
 
|-
 
| 1
 
| 1
−
| FALCON_CRYPTTRFSTAT_PENDING
+
| FALCON_DMAPOLL_CP_DMA_ACTIVE
 +
|-
 +
| 4
 +
| FALCON_DMAPOLL_CP_CFG_R_FENCE
 
|-
 
|-
 
| 5
 
| 5
−
| FALCON_CRYPTTRFSTAT_ENABLED
+
| FALCON_DMAPOLL_CP_CFG_W_FENCE
 
|-
 
|-
−
| 16-18
+
| 16-23
−
| FALCON_CRYPTTRFSTAT_NUM_STORES_PENDING
+
| FALCON_DMAPOLL_CP_WCOUNT
 
|-
 
|-
−
| 24-26
+
| 24-31
−
| FALCON_CRYPTTRFSTAT_NUM_LOADS_PENDING
+
| FALCON_DMAPOLL_CP_RCOUNT
 
|}
 
|}
   −
=== FALCON_HWCFG2 ===
+
Contains the status of a DMA transfer between the Falcon and the SCP.
 +
 
 +
=== FALCON_HWCFG1 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,513: Line 1,770:  
|-
 
|-
 
| 0-3
 
| 0-3
−
| FALCON_HWCFG2_VERSION
+
| FALCON_HWCFG1_CORE_REV
 
|-
 
|-
 
| 4-5
 
| 4-5
−
| FALCON_HWCFG2_SCP_MODE
+
| FALCON_HWCFG1_SECURITY_MODEL
 
|-
 
|-
 
| 6-7
 
| 6-7
−
| FALCON_HWCFG2_SUBVERSION
+
| FALCON_HWCFG1_CORE_REV_SUBVERSION
 
|-
 
|-
 
| 8-11
 
| 8-11
−
| FALCON_HWCFG2_IMEM_PORTS
+
| FALCON_HWCFG1_IMEM_PORTS
 
|-
 
|-
 
| 12-15
 
| 12-15
−
| FALCON_HWCFG2_DMEM_PORTS
+
| FALCON_HWCFG1_DMEM_PORTS
 
|-
 
|-
−
| 16-19
+
| 16-20
−
| FALCON_HWCFG2_VM_PAGES_LOG2
+
| FALCON_HWCFG1_TAG_WIDTH
 
|-
 
|-
 
| 27
 
| 27
−
| FALCON_HWCFG2_HAS_IMCTL_DEBUG
+
| FALCON_HWCFG1_DBG_PRIV_BUS
 +
|-
 +
| 28
 +
| FALCON_HWCFG1_CSB_SIZE_16M
 
|-
 
|-
−
| 28-29
+
| 29
−
| FALCON_HWCFG2_IO_ADDR_TYPE
+
| FALCON_HWCFG1_PRIV_DIRECT
 
|-
 
|-
 
| 30
 
| 30
−
| FALCON_HWCFG2_HAS_EXTERR
+
| FALCON_HWCFG1_DMEM_APERTURES
 
|-
 
|-
 
| 31
 
| 31
−
| FALCON_HWCFG2_HAS_IMFILL
+
| FALCON_HWCFG1_IMEM_AUTOFILL
 
|}
 
|}
   Line 1,549: Line 1,809:  
|-
 
|-
 
| 0-23
 
| 0-23
−
| Address
+
| FALCON_IMCTL_ADDR_BLK
 
|-
 
|-
 
| 24-26
 
| 24-26
−
| Command
+
| FALCON_IMCTL_CMD
−
  1: ITLB
+
  0x00: NOP
−
  2: PTLB
+
0x01: IMINV (ITLB)
−
  3: VTLB
+
  0x02: IMBLK (PTLB)
 +
  0x03: IMTAG (VTLB)
 +
0x04: IMTAG_SETVLD
 
|}
 
|}
   Line 1,569: Line 1,831:  
|-
 
|-
 
| 0-7
 
| 0-7
−
| Index of where to start tracing from
+
| FALCON_TRACEIDX_IDX
 
|-
 
|-
 
| 16-23
 
| 16-23
−
| Maximum valid index
+
| FALCON_TRACEIDX_MAXIDX
 
|-
 
|-
 
| 24-31
 
| 24-31
−
| Number of trace reads remaining
+
| FALCON_TRACEIDX_CNT
 
|}
 
|}
   Line 1,583: Line 1,845:  
Returns the PC of the last call or branch executed.
 
Returns the PC of the last call or branch executed.
   −
=== FALCON_IMEMC ===
+
=== FALCON_IMEMC0 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,589: Line 1,851:  
|-
 
|-
 
| 2-7
 
| 2-7
−
| Offset in IMEM block to read/write
+
| FALCON_IMEMC_OFFS
 
|-
 
|-
 
| 8-15
 
| 8-15
−
| IMEM block to read/write
+
| FALCON_IMEMC_BLK
 
|-
 
|-
 
| 24
 
| 24
−
| Write auto-increment
+
| FALCON_IMEMC_AINCW
 
|-
 
|-
 
| 25
 
| 25
−
| Read auto-increment
+
| FALCON_IMEMC_AINCR
 
|-
 
|-
 
| 28
 
| 28
−
| Mark uploaded code as secret
+
| FALCON_IMEMC_SECURE
 
|-
 
|-
 
| 29
 
| 29
−
| Secret code upload lockdown status (read-only)
+
| FALCON_IMEMC_SEC_ATOMIC
 
|-
 
|-
 
| 30
 
| 30
−
| Secret code upload failure status (read-only)
+
| FALCON_IMEMC_SEC_WR_VIO
 
|-
 
|-
 
| 31
 
| 31
−
| Secret code upload reset scrubber status (read-only)
+
| FALCON_IMEMC_SEC_LOCK
 
|}
 
|}
    
Used for configuring access to Falcon's IMEM.
 
Used for configuring access to Falcon's IMEM.
   −
=== FALCON_IMEMD ===
+
=== FALCON_IMEMD0 ===
 
Returns or takes the value for an IMEM read/write operation.
 
Returns or takes the value for an IMEM read/write operation.
   −
=== FALCON_IMEMT ===
+
=== FALCON_IMEMT0 ===
 
Returns or takes the virtual page index for an IMEM read/write operation.
 
Returns or takes the virtual page index for an IMEM read/write operation.
   Line 1,627: Line 1,889:  
|-
 
|-
 
| 2-7
 
| 2-7
−
| Offset in DMEM block to read/write
+
| FALCON_DMEMC_OFFS
 
|-
 
|-
 
| 8-15
 
| 8-15
−
| DMEM block to read/write
+
| FALCON_DMEMC_BLK
 
|-
 
|-
 
| 24
 
| 24
−
| Write auto-increment
+
| FALCON_DMEMC_AINCW
 
|-
 
|-
 
| 25
 
| 25
−
| Read auto-increment
+
| FALCON_DMEMC_AINCR
 
|}
 
|}
   Line 1,651: Line 1,913:  
| 0-3
 
| 0-3
 
| FALCON_ICD_CMD_OPC
 
| FALCON_ICD_CMD_OPC
−
  0x0: BREAK
+
  0x00: STOP
−
  0x1: CONTINUE_FROM_PC
+
  0x01: RUN (run from PC)
−
  0x2: CONTINUE_FROM_ADDR
+
  0x02: JRUN (run from address)
−
  0x3: CONTINUE_UNK1_FROM_PC
+
  0x03: RUNB (run from PC)
−
  0x4: CONTINUE_UNK1_FROM_ADDR
+
  0x04: JRUNB (run from address)
−
  0x5: SINGLE_STEP_FROM_PC
+
  0x05: STEP (step from PC)
−
  0x6: SINGLE_STEP_FROM_ADDR
+
  0x06: JSTEP (step from address)
−
  0x7: SET_BREAK_MASK
+
  0x07: EMASK (set exception mask)
−
  0x8: REG_READ
+
  0x08: RREG (read register)
−
  0x9: REG_WRITE
+
  0x09: WREG (write register)
−
  0xA: DATA_READ
+
  0x0A: RDM (read data memory)
−
  0xB: DATA_WRITE
+
  0x0B: WDM (write data memory)
−
  0xC: IO_READ
+
  0x0C: RCM (read MMIO/configuration memory)
−
  0xD: IO_WRITE
+
  0x0D: WCM (write MMIO/configuration memory)
−
  0xE: STATUS_READ
+
  0x0E: RSTAT (read status)
 +
0x0F: SBU
 
|-
 
|-
 
| 6-7
 
| 6-7
−
| FALCON_ICD_CMD_DATA_SIZE
+
| FALCON_ICD_CMD_SZ
 +
0x00: B (byte
 +
0x01: HW (half word)
 +
0x02: W (word)
 
|-
 
|-
 
| 8-12
 
| 8-12
 
| FALCON_ICD_CMD_IDX
 
| FALCON_ICD_CMD_IDX
 +
0x00: REG0 | RSTAT0 | WB0
 +
0x01: REG1 | RSTAT1 | WB1
 +
0x02: REG2 | RSTAT2 | WB2
 +
0x03: REG3 | RSTAT3 | WB3
 +
0x04: REG4 | RSTAT4
 +
0x05: REG5 | RSTAT5
 +
0x06: REG6
 +
0x07: REG7
 +
0x08: REG8
 +
0x09: REG9
 +
0x0A: REG10
 +
0x0B: REG11
 +
0x0C: REG12
 +
0x0D: REG13
 +
0x0E: REG14
 +
0x0F: REG15
 +
0x10: IV0
 +
0x11: IV1
 +
0x12: UNDEFINED
 +
0x13: EV
 +
0x14: SP
 +
0x15: PC
 +
0x16: IMB
 +
0x17: DMB
 +
0x18: CSW
 +
0x19: CCR
 +
0x1A: SEC
 +
0x1B: CTX
 +
0x1C: EXCI
 +
0x1D: SEC1
 +
0x1E: IMB1
 +
0x1F: DMB1
 
|-
 
|-
 
| 14
 
| 14
Line 1,677: Line 1,975:  
|-
 
|-
 
| 15
 
| 15
−
| FALCON_ICD_CMD_DONE
+
| FALCON_ICD_CMD_RDVLD
 
|-
 
|-
 
| 16-31
 
| 16-31
−
| FALCON_ICD_CMD_BREAK_MASK
+
| FALCON_ICD_CMD_PARM
 +
0x0001: EMASK_TRAP0
 +
0x0002: EMASK_TRAP1
 +
0x0004: EMASK_TRAP2
 +
0x0008: EMASK_TRAP3
 +
0x0010: EMASK_EXC_UNIMP
 +
0x0020: EMASK_EXC_IMISS
 +
0x0040: EMASK_EXC_IMHIT
 +
0x0080: EMASK_EXC_IBREAK
 +
0x0100: EMASK_IV0
 +
0x0200: EMASK_IV1
 +
0x0400: EMASK_IV2
 +
0x0800: EMASK_EXT0
 +
0x1000: EMASK_EXT1
 +
0x2000: EMASK_EXT2
 +
0x4000: EMASK_EXT3
 +
0x8000: EMASK_EXT4
 
|}
 
|}
   −
=== FALCON_SCTL ===
+
Used for sending commands to the Falcon's in-chip debugger.
 +
 
 +
=== FALCON_ICD_ADDR ===
 +
Takes the target address for the Falcon's in-chip debugger.
 +
 
 +
=== FALCON_ICD_WDATA ===
 +
Takes the data for writing using the Falcon's in-chip debugger.
 +
 
 +
=== FALCON_ICD_RDATA ===
 +
Returns the data read using the Falcon's in-chip debugger.
 +
 
 +
When reading from an internal status register (STAT), the following applies:
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-1
+
| 0
−
| FALCON_SCTL_SEC_MODE
+
| RSTAT0_MEM_STALL
−
0: Non-secure
+
|-
−
1: Light Secure
+
| 1
−
2: Heavy Secure
+
| RSTAT0_DMA_STALL
 
|-
 
|-
−
| 4-5
+
| 2
−
| FALCON_SCTL_OLD_SEC_MODE
+
| RSTAT0_FENCE_STALL
−
0: Non-secure
  −
1: Light Secure
  −
2: Heavy Secure
   
|-
 
|-
−
| 12-13
+
| 3
−
| Unknown
+
| RSTAT0_DIV_STALL
 
|-
 
|-
−
| 14
+
| 4
−
| Initialize the transition to LS mode
+
| RSTAT0_DMA_STALL_DMAQ
−
|}
  −
 
  −
=== FALCON_SCTL_STAT ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 31
+
| 5
−
| Set on memory protection violation
+
| RSTAT0_DMA_STALL_DMWAITING
−
|}
  −
 
  −
=== FALCON_SPROT_IMEM ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0-3
+
| 6
−
| Read access level
+
| RSTAT0_DMA_STALL_IMWAITING
 
|-
 
|-
−
| 4-7
+
| 7
−
| Write access level
+
| RSTAT0_ANY_STALL
−
|}
  −
 
  −
Controls accesses to Falcon IMEM.
  −
 
  −
=== FALCON_SPROT_DMEM ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0-3
+
| 8
−
| Read access level
+
| RSTAT0_SBFULL_STALL
 
|-
 
|-
−
| 4-7
+
| 9
−
| Write access level
+
| RSTAT0_SBHIT_STALL
−
|}
  −
 
  −
Controls accesses to Falcon DMEM.
  −
 
  −
=== FALCON_SPROT_CPUCTL ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0-3
+
| 10
−
| Read access level
+
| RSTAT0_FLOW_STALL
 +
|-
 +
| 11
 +
| RSTAT0_SP_STALL
 +
|-
 +
| 12
 +
| RSTAT0_BL_STALL
 +
|-
 +
| 13
 +
| RSTAT0_IPND_STALL
 +
|-
 +
| 14
 +
| RSTAT0_LDSTQ_STALL
 +
|-
 +
| 16
 +
| RSTAT0_NOINSTR_STALL
 +
|-
 +
| 20
 +
| RSTAT0_HALTSTOP_FLUSH
 +
|-
 +
| 21
 +
| RSTAT0_AFILL_FLUSH
 +
|-
 +
| 22
 +
| RSTAT0_EXC_FLUSH
 +
|-
 +
| 23-25
 +
| RSTAT0_IRQ_FLUSH
 +
|-
 +
| 28
 +
| RSTAT0_VALIDRD
 +
|-
 +
| 29
 +
| RSTAT0_WAITING
 +
|-
 +
| 30
 +
| RSTAT0_HALTED
 
|-
 
|-
−
| 4-7
+
| 31
−
| Write access level
+
| RSTAT0_MTHD_FULL
 
|}
 
|}
−
  −
Controls accesses to the [[#FALCON_CPUCTL|FALCON_CPUCTL]] register.
  −
  −
=== FALCON_SPROT_MISC ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,764: Line 2,090:  
|-
 
|-
 
| 0-3
 
| 0-3
−
| Read access level
+
| RSTAT1_WB_ALLOC
 
|-
 
|-
 
| 4-7
 
| 4-7
−
| Write access level
+
| RSTAT1_WB_VALID
 +
|-
 +
| 8-9
 +
| RSTAT1_WB0_SZ
 +
|-
 +
| 10-11
 +
| RSTAT1_WB1_SZ
 +
|-
 +
| 12-13
 +
| RSTAT1_WB2_SZ
 +
|-
 +
| 14-15
 +
| RSTAT1_WB3_SZ
 +
|-
 +
| 16-19
 +
| RSTAT1_WB0_IDX
 +
|-
 +
| 20-23
 +
| RSTAT1_WB1_IDX
 +
|-
 +
| 24-27
 +
| RSTAT1_WB2_IDX
 +
|-
 +
| 28-31
 +
| RSTAT1_WB3_IDX
 
|}
 
|}
−
  −
Controls accesses to the following registers:
  −
* FALCON_VM_SUPERVISOR
  −
* FALCON_SUBENGINE_RESET
  −
* FALCON_HOST_IO_INDEX
  −
* [[#FALCON_DMACTL|FALCON_DMACTL]]
  −
* [[#FALCON_IMCTL|FALCON_IMCTL]]
  −
* [[#FALCON_IMSTAT|FALCON_IMSTAT]]
  −
* FALCON_UNK_250
  −
* FALCON_UNK_2E0
  −
  −
=== FALCON_SPROT_IRQ ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,786: Line 2,124:  
|-
 
|-
 
| 0-3
 
| 0-3
−
| Read access level
+
| RSTAT2_DMAQ_NUM
 +
|-
 +
| 4
 +
| RSTAT2_DMA_ENABLE
 +
|-
 +
| 5-7
 +
| RSTAT2_LDSTQ_NUM
 +
|-
 +
| 16-19
 +
| RSTAT2_EM_BUSY
 +
|-
 +
| 20-23
 +
| RSTAT2_EM_ACKED
 +
|-
 +
| 24-27
 +
| RSTAT2_EM_ISWR
 
|-
 
|-
−
| 4-7
+
| 28-31
−
| Write access level
+
| RSTAT2_EM_DVLD
 
|}
 
|}
−
 
+
{| class="wikitable" border="1"
−
Controls accesses to the following registers:
+
!  Bits
−
* [[#FALCON_IRQMODE|FALCON_IRQMODE]]
  −
* [[#FALCON_IRQMSET|FALCON_IRQMSET]]
  −
* [[#FALCON_IRQMCLR|FALCON_IRQMCLR]]
  −
* [[#FALCON_IRQDEST|FALCON_IRQDEST]]
  −
* FALCON_GPTMR_PERIOD
  −
* FALCON_GPTMR_TIME
  −
* FALCON_GPTMR_ENABLE
  −
* FALCON_UNK_3C
  −
* FALCON_UNK_E0
  −
 
  −
=== FALCON_SPROT_MTHD ===
  −
{| class="wikitable" border="1"
  −
!  Bits
   
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 0
−
| Read access level
+
| RSTAT3_MTHD_IDLE
 
|-
 
|-
−
| 4-7
+
| 1
−
| Write access level
+
| RSTAT3_CTXSW_IDLE
−
|}
  −
 
  −
Controls accesses to the following registers:
  −
* [[#FALCON_ITFEN|FALCON_ITFEN]]
  −
* FALCON_CURCTX
  −
* FALCON_NXTCTX
  −
* FALCON_CMDCTX
  −
* FALCON_MTHD_DATA
  −
* FALCON_MTHD_CMD
  −
* FALCON_MTHD_DATA_WR
  −
* FALCON_MTHD_OCCUPIED
  −
* FALCON_MTHD_ACK
  −
* FALCON_MTHD_LIMIT
  −
* [[#FALCON_DEBUG1|FALCON_DEBUG1]]
  −
 
  −
=== FALCON_SPROT_SCTL ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0-3
+
| 2
−
| Read access level
+
| RSTAT3_DMA_IDLE
 
|-
 
|-
−
| 4-7
+
| 3
−
| Write access level
+
| RSTAT3_SCP_IDLE
 +
|-
 +
| 4
 +
| RSTAT3_LDST_IDLE
 +
|-
 +
| 5
 +
| RSTAT3_SBWB_EMPTY
 +
|-
 +
| 6-8
 +
| RSTAT3_CSWIE
 +
|-
 +
| 10
 +
| RSTAT3_CSWE
 +
|-
 +
| 12-14
 +
| RSTAT3_CTXSW_STATE
 +
0x00: IDLE
 +
0x01: SM_CHECK
 +
0x02: SM_SAVE
 +
0x03: SM_SAVE_WAIT
 +
0x04: SM_BLK_BIND
 +
0x05: SM_RESET
 +
0x06: SM_RESETWAIT
 +
0x07: SM_ACK
 +
|-
 +
| 15
 +
| RSTAT3_CTXSW_PEND
 +
|-
 +
| 17
 +
| RSTAT3_DMA_FBREQ_IDLE
 +
|-
 +
| 18
 +
| RSTAT3_DMA_ACKQ_EMPTY
 +
|-
 +
| 19
 +
| RSTAT3_DMA_RDQ_EMPTY
 +
|-
 +
| 20
 +
| RSTAT3_DMA_WR_BUSY
 +
|-
 +
| 21
 +
| RSTAT3_DMA_RD_BUSY
 +
|-
 +
| 22
 +
| RSTAT3_LDST_XT_BUSY
 +
|-
 +
| 23
 +
| RSTAT3_LDST_XT_BLOCK
 +
|-
 +
| 24
 +
| RSTAT3_ENG_IDLE
 
|}
 
|}
−
  −
Controls accesses to the [[#FALCON_SCTL|FALCON_SCTL]] register.
  −
  −
=== FALCON_SPROT_WDTMR ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 0-1
−
| Read access level
+
| RSTAT4_ICD_STATE
 +
0x00: NORMAL
 +
0x01: WAIT_ISSUE_CLEAR
 +
0x02: WAIT_EXLDQ_CLEAR
 +
0x03: FULL_DBG_MODE
 +
|-
 +
| 2-3
 +
| RSTAT4_ICD_MODE
 +
0x00: SUPPRESSICD
 +
0x01: ENTERICD_IBRK
 +
0x02: ENTERICD_STEP
 +
|-
 +
| 16
 +
| RSTAT4_ICD_EMASK_TRAP0
 +
|-
 +
| 17
 +
| RSTAT4_ICD_EMASK_TRAP1
 +
|-
 +
| 18
 +
| RSTAT4_ICD_EMASK_TRAP2
 
|-
 
|-
−
| 4-7
+
| 19
−
| Write access level
+
| RSTAT4_ICD_EMASK_TRAP3
−
|}
  −
 
  −
Controls accesses to the following registers:
  −
* FALCON_WDTMR_TIME
  −
* FALCON_WDTMR_ENABLE
  −
 
  −
=== TSEC_SCP_CTL0 ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
 
| 20
 
| 20
−
| Enable TSEC_SCP_INSN_STAT register
+
| RSTAT4_ICD_EMASK_EXC_UNIMP
−
|}
  −
 
  −
=== TSEC_SCP_CTL1 ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 11
+
| 21
−
| Enable TRNG testing mode
+
| RSTAT4_ICD_EMASK_EXC_IMISS
 
|-
 
|-
−
| 12
+
| 22
−
| Enable the TRNG
+
| RSTAT4_ICD_EMASK_EXC_IMHIT
 +
|-
 +
| 23
 +
| RSTAT4_ICD_EMASK_EXC_IBREAK
 +
|-
 +
| 24
 +
| RSTAT4_ICD_EMASK_IV0
 +
|-
 +
| 25
 +
| RSTAT4_ICD_EMASK_IV1
 +
|-
 +
| 26
 +
| RSTAT4_ICD_EMASK_IV2
 +
|-
 +
| 27
 +
| RSTAT4_ICD_EMASK_EXT0
 +
|-
 +
| 28
 +
| RSTAT4_ICD_EMASK_EXT1
 +
|-
 +
| 29
 +
| RSTAT4_ICD_EMASK_EXT2
 +
|-
 +
| 30
 +
| RSTAT4_ICD_EMASK_EXT3
 +
|-
 +
| 31
 +
| RSTAT4_ICD_EMASK_EXT4
 
|}
 
|}
−
  −
=== TSEC_SCP_CTL_STAT ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 20
+
| 0-7
−
| TSEC_SCP_CTL_STAT_DEBUG_MODE
+
| RSTAT5_LRU_STATE
 
|}
 
|}
   −
=== TSEC_SCP_CTL_LOCK ===
+
=== FALCON_SCTL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-1
−
| Disable reads for the SCP and TRNG register blocks
+
| FALCON_SCTL_SEC_MODE
 +
0: Non-secure
 +
1: Light Secure
 +
2: Heavy Secure
 
|-
 
|-
−
| 1
+
| 4-5
−
| Disable reads for the TFBIF register block
+
| FALCON_SCTL_OLD_SEC_MODE
 +
0: Non-secure
 +
1: Light Secure
 +
2: Heavy Secure
 
|-
 
|-
−
| 2
+
| 12-13
−
| Disable reads for the DMA register block
+
| Unknown
 
|-
 
|-
−
| 3
+
| 14
−
| Disable reads for the TEGRA register block
+
| Initialize the transition to LS mode
−
|-
  −
| 4
  −
| Disable writes for the SCP and TRNG register blocks
  −
|-
  −
| 5
  −
| Disable writes for the TFBIF register block
  −
|-
  −
| 6
  −
| Disable writes for the DMA register block
  −
|-
  −
| 7
  −
| Disable writes for the TEGRA register block
   
|}
 
|}
   −
Locks accesses to sub-engines and can only be cleared in Heavy Secure mode.
+
=== FALCON_SSTAT ===
−
 
  −
=== TSEC_SCP_CTL_PKEY ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 31
−
| TSEC_SCP_CTL_PKEY_REQUEST_RELOAD
+
| Set on memory protection violation
−
|-
  −
| 1
  −
| TSEC_SCP_CTL_PKEY_LOADED
   
|}
 
|}
   −
=== TSEC_SCP_SEQ_CTL ===
+
=== FALCON_SPROT_IMEM ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,938: Line 2,322:  
|-
 
|-
 
| 0-3
 
| 0-3
−
| Sequence's instruction index
+
| Read access level
 
|-
 
|-
 
| 4-7
 
| 4-7
−
| Target and control flags
+
| Write access level
−
|-
  −
| 8-11
  −
| Sequence's size
   
|}
 
|}
   −
Controls the last crypto sequence (cs0 or cs1) created.
+
Controls accesses to Falcon IMEM.
   −
=== TSEC_SCP_SEQ_VAL ===
+
=== FALCON_SPROT_DMEM ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,955: Line 2,336:  
|-
 
|-
 
| 0-3
 
| 0-3
−
| Sequence instruction's first operand
+
| Read access level
 
|-
 
|-
−
| 4-9
+
| 4-7
−
| Sequence instruction's second operand
+
| Write access level
−
|-
  −
| 10-14
  −
| Sequence instruction's opcode
   
|}
 
|}
   −
Contains information on the last crypto sequence (cs0 or cs1) created.
+
Controls accesses to Falcon DMEM.
   −
=== TSEC_SCP_SEQ_STAT ===
+
=== FALCON_SPROT_CPUCTL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-3
−
| Set if crypto sequence recording (cs0begin/cs1begin) is active
+
| Read access level
 
|-
 
|-
 
| 4-7
 
| 4-7
−
| Number of instructions left for the crypto sequence
+
| Write access level
 +
|}
 +
 
 +
Controls accesses to the [[#FALCON_CPUCTL|FALCON_CPUCTL]] register.
 +
 
 +
=== FALCON_SPROT_MISC ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 
|-
 
|-
−
| 12-15
+
| 4-7
−
| Active crypto key register
+
| Write access level
 
|}
 
|}
   −
Contains information on the last crypto sequence (cs0 or cs1) executed.
+
Controls accesses to the following registers:
 +
* FALCON_PRIVSTATE
 +
* FALCON_SFTRESET
 +
* FALCON_ADDR
 +
* [[#FALCON_DMACTL|FALCON_DMACTL]]
 +
* [[#FALCON_IMCTL|FALCON_IMCTL]]
 +
* [[#FALCON_IMSTAT|FALCON_IMSTAT]]
 +
* FALCON_UNK_250
 +
* FALCON_DMAINFO_CTL
   −
=== TSEC_SCP_INSN_STAT ===
+
=== FALCON_SPROT_IRQ ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,989: Line 2,386:  
|-
 
|-
 
| 0-3
 
| 0-3
−
| Destination register or immediate value
+
| Read access level
 
|-
 
|-
−
| 8-13
+
| 4-7
−
| Source register or immediate value
+
| Write access level
−
|-
  −
| 20-24
  −
| Operation
  −
0x0:  nop (fuc5 opcode 0x00)
  −
0x1:  cmov (fuc5 opcode 0x84)
  −
0x2:  cxsin (fuc5 opcode 0x88) or xdst (with cxset)
  −
0x3:  cxsout (fuc5 opcode 0x8C) or xdld (with cxset)
  −
0x4:  crnd (fuc5 opcode 0x90)
  −
0x5:  cs0begin (fuc5 opcode 0x94)
  −
0x6:  cs0exec (fuc5 opcode 0x98)
  −
0x7:  cs1begin (fuc5 opcode 0x9C)
  −
0x8:  cs1exec (fuc5 opcode 0xA0)
  −
0x9:  invalid (fuc5 opcode 0xA4)
  −
0xA:  cchmod (fuc5 opcode 0xA8)
  −
0xB:  cxor (fuc5 opcode 0xAC)
  −
0xC:  cadd (fuc5 opcode 0xB0)
  −
0xD:  cand (fuc5 opcode 0xB4)
  −
0xE:  crev (fuc5 opcode 0xB8)
  −
0xF:  cprecmac (fuc5 opcode 0xBC)
  −
0x10: csecret (fuc5 opcode 0xC0)
  −
0x11: ckeyreg (fuc5 opcode 0xC4)
  −
0x12: ckexp (fuc5 opcode 0xC8)
  −
0x13: ckrexp (fuc5 opcode 0xCC)
  −
0x14: cenc (fuc5 opcode 0xD0)
  −
0x15: cdec (fuc5 opcode 0xD4)
  −
0x16: csigauth (fuc5 opcode 0xD8)
  −
0x17: csigenc (fuc5 opcode 0xDC)
  −
0x18: csigclr (fuc5 opcode 0xE0)
  −
|-
  −
| 28
  −
| Set if the instruction is valid
  −
|-
  −
| 31
  −
| Set if running in HS mode
   
|}
 
|}
   −
Contains information on the last crypto instruction executed.
+
Controls accesses to the following registers:
 +
* [[#FALCON_IRQMODE|FALCON_IRQMODE]]
 +
* [[#FALCON_IRQMSET|FALCON_IRQMSET]]
 +
* [[#FALCON_IRQMCLR|FALCON_IRQMCLR]]
 +
* [[#FALCON_IRQDEST|FALCON_IRQDEST]]
 +
* FALCON_GPTMRINT
 +
* FALCON_GPTMRVAL
 +
* FALCON_GPTMRCTL
 +
* FALCON_IRQDEST2
 +
* FALCON_UNK_E0
   −
=== TSEC_SCP_AUTH_STAT ===
+
=== FALCON_SPROT_MTHD ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-1
+
| 0-3
−
| Signature comparison result (3=succeeded, 2=failed)
+
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 
|}
 
|}
   −
Contains information on the last authentication attempt.
+
Controls accesses to the following registers:
 +
* [[#FALCON_ITFEN|FALCON_ITFEN]]
 +
* FALCON_CURCTX
 +
* FALCON_NXTCTX
 +
* FALCON_CTXACK
 +
* FALCON_MTHDDATA
 +
* FALCON_MTHDID
 +
* FALCON_MTHDWDAT
 +
* FALCON_MTHDCOUNT
 +
* FALCON_MTHDPOP
 +
* FALCON_MTHDRAMSZ
 +
* [[#FALCON_DEBUG1|FALCON_DEBUG1]]
   −
=== TSEC_SCP_AES_STAT ===
+
=== FALCON_SPROT_SCTL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-4
+
| 0-3
−
| First opcode
+
| Read access level
 
|-
 
|-
−
| 5-9
+
| 4-7
−
| Second opcode
+
| Write access level
−
|-
+
|}
−
| 15-16
  −
| AES operation
  −
0: Encryption
  −
1: Decryption
  −
2: Key expansion
  −
3: Key reverse expansion
  −
|}
     −
Contains information on the last AES sequence executed.
+
Controls accesses to the [[#FALCON_SCTL|FALCON_SCTL]] register.
   −
=== TSEC_SCP_IRQSTAT ===
+
=== FALCON_SPROT_WDTMR ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-3
−
| TSEC_SCP_IRQSTAT_TRNG
+
| Read access level
 
|-
 
|-
−
| 8
+
| 4-7
−
| TSEC_SCP_IRQSTAT_ACL_ERROR
+
| Write access level
−
|-
+
|}
−
| 12
+
 
−
| Unknown
+
Controls accesses to the following registers:
−
|-
+
* FALCON_WDTMRVAL
−
| 16
+
* FALCON_WDTMRCTL
−
| TSEC_SCP_IRQSTAT_INSN_ERROR
+
 
 +
=== TSEC_SCP_CTL0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
 
| 20
 
| 20
−
| TSEC_SCP_IRQSTAT_SINGLE_STEP
+
| Enable TSEC_SCP_INSN_STAT register
 +
|}
 +
 
 +
=== TSEC_SCP_CTL1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| 24
+
| 11
−
| Unknown
+
| Enable TRNG testing mode
 
|-
 
|-
−
| 28
+
| 12
−
| Unknown
+
| Enable the TRNG
 
|}
 
|}
   −
Used for getting the status of crypto IRQs.
+
=== TSEC_SCP_CTL_STAT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 20
 +
| TSEC_SCP_CTL_STAT_DEBUG_MODE
 +
|}
   −
=== TSEC_SCP_IRQMASK ===
+
=== TSEC_SCP_CTL_LOCK ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 2,098: Line 2,494:  
|-
 
|-
 
| 0
 
| 0
−
| TSEC_SCP_IRQMASK_TRNG
+
| Disable reads for the SCP and TRNG register blocks
 
|-
 
|-
−
| 8
+
| 1
−
| TSEC_SCP_IRQMASK_ACL_ERROR
+
| Disable reads for the TFBIF register block
 
|-
 
|-
−
| 12
+
| 2
−
| Unknown
+
| Disable reads for the DMA register block
 +
|-
 +
| 3
 +
| Disable reads for the TEGRA register block
 
|-
 
|-
−
| 16
+
| 4
−
| TSEC_SCP_IRQMASK_INSN_ERROR
+
| Disable writes for the SCP and TRNG register blocks
 
|-
 
|-
−
| 20
+
| 5
−
| TSEC_SCP_IRQMASK_SINGLE_STEP
+
| Disable writes for the TFBIF register block
 
|-
 
|-
−
| 24
+
| 6
−
| Unknown
+
| Disable writes for the DMA register block
 
|-
 
|-
−
| 28
+
| 7
−
| Unknown
+
| Disable writes for the TEGRA register block
 
|}
 
|}
   −
Used for getting the value of the mask for crypto IRQs.
+
Locks accesses to sub-engines and can only be cleared in Heavy Secure mode.
   −
=== TSEC_SCP_ACL_ERR ===
+
=== TSEC_SCP_CTL_PKEY ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 2,127: Line 2,526:  
|-
 
|-
 
| 0
 
| 0
−
| Set when writing to a crypto register without the correct ACL
+
| TSEC_SCP_CTL_PKEY_REQUEST_RELOAD
 
|-
 
|-
−
| 4
+
| 1
−
| Set when reading from a crypto register without the correct ACL
+
| TSEC_SCP_CTL_PKEY_LOADED
 +
|}
 +
 
 +
=== TSEC_SCP_SEQ_CTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Sequence's instruction index
 
|-
 
|-
−
| 8
+
| 4-7
−
| Set on an invalid ACL change (cchmod)
+
| Target and control flags
 
|-
 
|-
−
| 31
+
| 8-11
−
| An ACL error occurred
+
| Sequence's size
 
|}
 
|}
   −
Contains information on the status generated by the [[#TSEC_SCP_IRQSTAT|TSEC_SCP_IRQSTAT_ACL_ERROR]] IRQ.
+
Controls the last crypto sequence (cs0 or cs1) created.
   −
=== TSEC_SCP_INSN_ERR ===
+
=== TSEC_SCP_SEQ_VAL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-3
−
| Invalid instruction
+
| Sequence instruction's first operand
 
|-
 
|-
−
| 4
+
| 4-9
−
| Empty crypto sequence
+
| Sequence instruction's second operand
 
|-
 
|-
−
| 8
+
| 10-14
−
| Crypto sequence is too long
+
| Sequence instruction's opcode
 +
|}
 +
 
 +
Contains information on the last crypto sequence (cs0 or cs1) created.
 +
 
 +
=== TSEC_SCP_SEQ_STAT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| 12
+
| 0
−
| Crypto sequence was not finished
+
| Set if crypto sequence recording (cs0begin/cs1begin) is active
 
|-
 
|-
−
| 16
+
| 4-7
−
| Insecure signature (csigenc, csigclr or csigauth)
+
| Number of instructions left for the crypto sequence
 
|-
 
|-
−
| 20
+
| 12-15
−
| Invalid signature (csigauth in HS mode)
+
| Active crypto key register
−
|-
  −
| 24
  −
| Forbidden ACL change (cchmod in NS mode)
   
|}
 
|}
   −
Contains information on crypto errors generated by the [[#TSEC_SCP_IRQSTAT|TSEC_SCP_IRQSTAT_INSN_ERROR]] IRQ.
+
Contains information on the last crypto sequence (cs0 or cs1) executed.
   −
=== TSEC_TFBIF_MCCIF_FIFOCTRL ===
+
=== TSEC_SCP_INSN_STAT ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-3
−
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVERRIDE
+
| Destination register or immediate value
 
|-
 
|-
−
| 1
+
| 8-13
−
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVERRIDE
+
| Source register or immediate value
 
|-
 
|-
−
| 2
+
| 20-24
−
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRCL_MCLE2X
+
| Operation
 +
0x0:  nop (fuc5 opcode 0x00)
 +
0x1:  cmov (fuc5 opcode 0x84)
 +
0x2:  cxsin (fuc5 opcode 0x88) or xdst (with cxset)
 +
0x3:  cxsout (fuc5 opcode 0x8C) or xdld (with cxset)
 +
0x4:  crnd (fuc5 opcode 0x90)
 +
0x5:  cs0begin (fuc5 opcode 0x94)
 +
0x6:  cs0exec (fuc5 opcode 0x98)
 +
0x7:  cs1begin (fuc5 opcode 0x9C)
 +
0x8:  cs1exec (fuc5 opcode 0xA0)
 +
0x9:  invalid (fuc5 opcode 0xA4)
 +
0xA:  cchmod (fuc5 opcode 0xA8)
 +
0xB:  cxor (fuc5 opcode 0xAC)
 +
0xC:  cadd (fuc5 opcode 0xB0)
 +
0xD:  cand (fuc5 opcode 0xB4)
 +
0xE:  crev (fuc5 opcode 0xB8)
 +
0xF:  cprecmac (fuc5 opcode 0xBC)
 +
0x10: csecret (fuc5 opcode 0xC0)
 +
0x11: ckeyreg (fuc5 opcode 0xC4)
 +
0x12: ckexp (fuc5 opcode 0xC8)
 +
0x13: ckrexp (fuc5 opcode 0xCC)
 +
0x14: cenc (fuc5 opcode 0xD0)
 +
0x15: cdec (fuc5 opcode 0xD4)
 +
0x16: csigauth (fuc5 opcode 0xD8)
 +
0x17: csigenc (fuc5 opcode 0xDC)
 +
0x18: csigclr (fuc5 opcode 0xE0)
 
|-
 
|-
−
| 3
+
| 28
−
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDMC_RDFAST
+
| Set if the instruction is valid
−
|-
+
|-
−
| 4
+
| 31
−
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRMC_CLLE2X
+
| Set if running in HS mode
−
|-
+
|}
−
| 5
+
 
−
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDCL_RDFAST
+
Contains information on the last crypto instruction executed.
−
|-
+
 
−
| 6
+
=== TSEC_SCP_AUTH_STAT ===
−
| TSEC_TFBIF_MCCIF_FIFOCTRL_CCLK_OVERRIDE
+
{| class="wikitable" border="1"
−
|-
+
!  Bits
−
| 7
+
!  Description
−
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVR_MODE
+
|-
−
|-
+
| 0-1
−
| 8
+
| Signature comparison result (3=succeeded, 2=failed)
−
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVR_MODE
+
|}
−
|}
+
 
−
 
+
Contains information on the last authentication attempt.
−
=== TSEC_TFBIF_MCCIF_FIFOCTRL1 ===
+
 
−
{| class="wikitable" border="1"
+
=== TSEC_SCP_AES_STAT ===
−
!  Bits
+
{| class="wikitable" border="1"
−
!  Description
+
!  Bits
−
|-
+
!  Description
−
| 0-15
+
|-
−
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SRD2MC_REORDER_DEPTH_LIMIT
+
| 0-4
−
|-
+
| First opcode
−
| 16-31
+
|-
−
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SWR2MC_REORDER_DEPTH_LIMIT
+
| 5-9
−
|}
+
| Second opcode
−
 
+
|-
−
=== TSEC_TFBIF_UNK_44 ===
+
| 15-16
−
Used to control accesses to DRAM.
+
| AES operation
 +
0: Encryption
 +
1: Decryption
 +
2: Key expansion
 +
3: Key reverse expansion
 +
|}
 +
 
 +
Contains information on the last AES sequence executed.
 +
 
 +
=== TSEC_SCP_IRQSTAT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_SCP_IRQSTAT_TRNG
 +
|-
 +
| 8
 +
| TSEC_SCP_IRQSTAT_ACL_ERROR
 +
|-
 +
| 12
 +
| Unknown
 +
|-
 +
| 16
 +
| TSEC_SCP_IRQSTAT_INSN_ERROR
 +
|-
 +
| 20
 +
| TSEC_SCP_IRQSTAT_SINGLE_STEP
 +
|-
 +
| 24
 +
| Unknown
 +
|-
 +
| 28
 +
| Unknown
 +
|}
 +
 
 +
Used for getting the status of crypto IRQs.
 +
 
 +
=== TSEC_SCP_IRQMASK ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_SCP_IRQMASK_TRNG
 +
|-
 +
| 8
 +
| TSEC_SCP_IRQMASK_ACL_ERROR
 +
|-
 +
| 12
 +
| Unknown
 +
|-
 +
| 16
 +
| TSEC_SCP_IRQMASK_INSN_ERROR
 +
|-
 +
| 20
 +
| TSEC_SCP_IRQMASK_SINGLE_STEP
 +
|-
 +
| 24
 +
| Unknown
 +
|-
 +
| 28
 +
| Unknown
 +
|}
 +
 
 +
Used for getting the value of the mask for crypto IRQs.
 +
 
 +
=== TSEC_SCP_ACL_ERR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Set when writing to a crypto register without the correct ACL
 +
|-
 +
| 4
 +
| Set when reading from a crypto register without the correct ACL
 +
|-
 +
| 8
 +
| Set on an invalid ACL change (cchmod)
 +
|-
 +
| 31
 +
| An ACL error occurred
 +
|}
 +
 
 +
Contains information on the status generated by the [[#TSEC_SCP_IRQSTAT|TSEC_SCP_IRQSTAT_ACL_ERROR]] IRQ.
 +
 
 +
=== TSEC_SCP_INSN_ERR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Invalid instruction
 +
|-
 +
| 4
 +
| Empty crypto sequence
 +
|-
 +
| 8
 +
| Crypto sequence is too long
 +
|-
 +
| 12
 +
| Crypto sequence was not finished
 +
|-
 +
| 16
 +
| Insecure signature (csigenc, csigclr or csigauth)
 +
|-
 +
| 20
 +
| Invalid signature (csigauth in HS mode)
 +
|-
 +
| 24
 +
| Forbidden ACL change (cchmod in NS mode)
 +
|}
 +
 
 +
Contains information on crypto errors generated by the [[#TSEC_SCP_IRQSTAT|TSEC_SCP_IRQSTAT_INSN_ERROR]] IRQ.
 +
 
 +
=== TSEC_TFBIF_CTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_CTL_CLR_BWCOUNT
 +
|-
 +
| 1
 +
| TSEC_TFBIF_CTL_ENABLE
 +
|-
 +
| 2
 +
| TSEC_TFBIF_CTL_CLR_IDLEWDERR
 +
|-
 +
| 3
 +
| TSEC_TFBIF_CTL_RESET
 +
|-
 +
| 4
 +
| TSEC_TFBIF_CTL_IDLE
 +
|-
 +
| 5
 +
| TSEC_TFBIF_CTL_IDLEWDERR
 +
|-
 +
| 6
 +
| TSEC_TFBIF_CTL_SRTOUT
 +
|-
 +
| 7
 +
| TSEC_TFBIF_CTL_CLR_SRTOUT
 +
|-
 +
| 8-11
 +
| TSEC_TFBIF_CTL_SRTOVAL
 +
|-
 +
| 12
 +
| TSEC_TFBIF_CTL_VPR
 +
|}
 +
 
 +
=== TSEC_TFBIF_MCCIF_FIFOCTRL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVERRIDE
 +
|-
 +
| 1
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVERRIDE
 +
|-
 +
| 2
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRCL_MCLE2X
 +
|-
 +
| 3
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDMC_RDFAST
 +
|-
 +
| 4
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRMC_CLLE2X
 +
|-
 +
| 5
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDCL_RDFAST
 +
|-
 +
| 6
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_CCLK_OVERRIDE
 +
|-
 +
| 7
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVR_MODE
 +
|-
 +
| 8
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVR_MODE
 +
|}
 +
 
 +
=== TSEC_TFBIF_MCCIF_FIFOCTRL1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-15
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SRD2MC_REORDER_DEPTH_LIMIT
 +
|-
 +
| 16-31
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SWR2MC_REORDER_DEPTH_LIMIT
 +
|}
 +
 
 +
=== TSEC_TFBIF_THROTTLE ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-11
 +
| TSEC_TFBIF_THROTTLE_BUCKET_SIZE
 +
|-
 +
| 16-27
 +
| TSEC_TFBIF_THROTTLE_LEAK_COUNT
 +
|-
 +
| 30-31
 +
| TSEC_TFBIF_THROTTLE_LEAK_SIZE
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_STAT0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_DBG_STAT0_1K_TRANSFER
 +
|-
 +
| 1
 +
| TSEC_TFBIF_DBG_STAT0_RREQ_ISSUED
 +
|-
 +
| 2
 +
| TSEC_TFBIF_DBG_STAT0_WREQ_ISSUED
 +
|-
 +
| 3
 +
| TSEC_TFBIF_DBG_STAT0_TAGQ_ISSUED
 +
|-
 +
| 4
 +
| TSEC_TFBIF_DBG_STAT0_STALL_RDATQ
 +
|-
 +
| 5
 +
| TSEC_TFBIF_DBG_STAT0_STALL_RACKQ
 +
|-
 +
| 6
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WREQQ
 +
|-
 +
| 7
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WDATQ
 +
|-
 +
| 8
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WACKQ
 +
|-
 +
| 9
 +
| TSEC_TFBIF_DBG_STAT0_STALL_RREQ_PENDING
 +
|-
 +
| 10
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WREQ_PENDING
 +
|-
 +
| 11
 +
| TSEC_TFBIF_DBG_STAT0_STALL_MREQ
 +
|-
 +
| 12
 +
| TSEC_TFBIF_DBG_STAT0_ENGINE_IDLE
 +
|-
 +
| 13
 +
| TSEC_TFBIF_DBG_STAT0_RMCCIF_IDLE
 +
|-
 +
| 14
 +
| TSEC_TFBIF_DBG_STAT0_WMCCIF_IDLE
 +
|-
 +
| 15
 +
| TSEC_TFBIF_DBG_STAT0_CSB_IDLE
 +
|-
 +
| 16
 +
| TSEC_TFBIF_DBG_STAT0_RU_IDLE
 +
|-
 +
| 17
 +
| TSEC_TFBIF_DBG_STAT0_WU_IDLE
 +
|-
 +
| 19
 +
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_ACTIVE
 +
|-
 +
| 20
 +
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_MCB
 +
|}
 +
 
 +
=== TSEC_TFBIF_SPROT_EMEM ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to external memory regions. Accessible in HS mode only.
 +
 
 +
=== TSEC_TFBIF_TRANSCFG ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_TRANSCFG_ATT0_SWID
 +
|-
 +
| 4
 +
| TSEC_TFBIF_TRANSCFG_ATT1_SWID
 +
|-
 +
| 8
 +
| TSEC_TFBIF_TRANSCFG_ATT2_SWID
 +
|-
 +
| 12
 +
| TSEC_TFBIF_TRANSCFG_ATT3_SWID
 +
|-
 +
| 16
 +
| TSEC_TFBIF_TRANSCFG_ATT4_SWID
 +
|-
 +
| 20
 +
| TSEC_TFBIF_TRANSCFG_ATT5_SWID
 +
|-
 +
| 24
 +
| TSEC_TFBIF_TRANSCFG_ATT6_SWID
 +
|-
 +
| 28
 +
| TSEC_TFBIF_TRANSCFG_ATT7_SWID
 +
|}
 +
 
 +
Configures the software ID per CTXDMA port for memory transactions. Software ID 0 (HW_SWID) forces all transactions to go through the SMMU while software ID 1 (PHY_SWID) bypasses it. Accessible in HS mode only.
 +
 
 +
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
 +
 
 +
=== TSEC_TFBIF_REGIONCFG ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-2
 +
| TSEC_TFBIF_REGIONCFG_T0_APERT_ID
 +
|-
 +
| 3
 +
| TSEC_TFBIF_REGIONCFG_T0_VPR
 +
|-
 +
| 4-6
 +
| TSEC_TFBIF_REGIONCFG_T1_APERT_ID
 +
|-
 +
| 7
 +
| TSEC_TFBIF_REGIONCFG_T1_VPR
 +
|-
 +
| 8-10
 +
| TSEC_TFBIF_REGIONCFG_T2_APERT_ID
 +
|-
 +
| 11
 +
| TSEC_TFBIF_REGIONCFG_T2_VPR
 +
|-
 +
| 12-14
 +
| TSEC_TFBIF_REGIONCFG_T3_APERT_ID
 +
|-
 +
| 15
 +
| TSEC_TFBIF_REGIONCFG_T3_VPR
 +
|-
 +
| 16-18
 +
| TSEC_TFBIF_REGIONCFG_T4_APERT_ID
 +
|-
 +
| 19
 +
| TSEC_TFBIF_REGIONCFG_T4_VPR
 +
|-
 +
| 20-22
 +
| TSEC_TFBIF_REGIONCFG_T5_APERT_ID
 +
|-
 +
| 23
 +
| TSEC_TFBIF_REGIONCFG_T5_VPR
 +
|-
 +
| 24-26
 +
| TSEC_TFBIF_REGIONCFG_T6_APERT_ID
 +
|-
 +
| 27
 +
| TSEC_TFBIF_REGIONCFG_T6_VPR
 +
|-
 +
| 28-30
 +
| TSEC_TFBIF_REGIONCFG_T7_APERT_ID
 +
|-
 +
| 31
 +
| TSEC_TFBIF_REGIONCFG_T7_VPR
 +
|}
 +
 
 +
Configures the aperture ID and VPR mode per CTXDMA port for memory region accessing. Accessible in HS mode only.
 +
 
 +
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
   −
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
+
=== TSEC_TFBIF_ACTMON_ACTIVE_MASK ===
 +
Takes the memory access mask for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
   −
=== TSEC_TFBIF_UNK_48 ===
+
=== TSEC_TFBIF_ACTMON_ACTIVE_BORPS ===
−
Used to control accesses to DRAM.
+
Takes the billions of records per second count for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
   −
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
+
=== TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT ===
 +
Controls the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
    
=== TSEC_CG ===
 
=== TSEC_CG ===
Line 2,243: Line 3,065:  
|}
 
|}
   −
=== TSEC_DMA_CMD ===
+
=== TSEC_BAR0_CTL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 2,249: Line 3,071:  
|-
 
|-
 
| 0
 
| 0
−
| TSEC_DMA_CMD_READ
+
| TSEC_BAR0_CTL_READ
 
|-
 
|-
 
| 1
 
| 1
−
| TSEC_DMA_CMD_WRITE
+
| TSEC_BAR0_CTL_WRITE
 
|-
 
|-
 
| 4-7
 
| 4-7
−
| TSEC_DMA_CMD_BYTE_MASK
+
| TSEC_BAR0_CTL_BYTE_MASK
 
|-
 
|-
 
| 12-13
 
| 12-13
−
| TSEC_DMA_CMD_STATUS
+
| TSEC_BAR0_CTL_STATUS
 
  0: Idle
 
  0: Idle
 
  1: Busy
 
  1: Busy
Line 2,265: Line 3,087:  
|-
 
|-
 
| 31
 
| 31
−
| TSEC_DMA_CMD_INIT
+
| TSEC_BAR0_CTL_INIT
 
|}
 
|}
   −
A DMA read/write operation requires bits TSEC_DMA_CMD_INIT and TSEC_DMA_CMD_READ/TSEC_DMA_CMD_WRITE to be set in TSEC_DMA_CMD.
+
A BAR0 DMA read/write operation requires bits TSEC_BAR0_CTL_INIT and TSEC_BAR0_CTL_READ/TSEC_BAR0_CTL_WRITE to be set in TSEC_BAR0_CTL.
   −
During the transfer, TSEC_DMA_CMD_STATUS is set to "Busy".
+
During the transfer, TSEC_BAR0_CTL_STATUS is set to "Busy".
   −
Accessing an invalid address sets TSEC_DMA_CMD_STATUS to "Error".
+
Accessing an invalid address sets TSEC_BAR0_CTL_STATUS to "Error".
   −
=== TSEC_DMA_ADDR ===
+
=== TSEC_BAR0_ADDR ===
 
Takes the address for DMA transfers between TSEC and HOST1X (master and clients).
 
Takes the address for DMA transfers between TSEC and HOST1X (master and clients).
   −
=== TSEC_DMA_DATA ===
+
=== TSEC_BAR0_DATA ===
 
Takes the data for DMA transfers between TSEC and HOST1X (master and clients).
 
Takes the data for DMA transfers between TSEC and HOST1X (master and clients).
   −
=== TSEC_DMA_TIMEOUT ===
+
=== TSEC_BAR0_TIMEOUT ===
−
Always 0xFFF.
+
Takes the timeout value for DMA transfers between TSEC and HOST1X (master and clients).
    
=== TSEC_TEGRA_CTL ===
 
=== TSEC_TEGRA_CTL ===
Line 2,488: Line 3,310:  
Falcon's Authenticated Mode has access to 64 128-bit keys which are burned at factory. These keys can be loaded by using the $csecret instruction which takes the target crypto register and the key index as arguments.
 
Falcon's Authenticated Mode has access to 64 128-bit keys which are burned at factory. These keys can be loaded by using the $csecret instruction which takes the target crypto register and the key index as arguments.
   −
All secrets appear to be common across Falcon units of the same version, with the exception of secret 0x3F. This secret is effectively empty (all zeros), but is configured to be overwritten with the KFUSE private key once the KFUSE clock is enabled. The KFUSE private key is console-unique.
+
Secrets are specific to each Falcon unit with the exception of secret 0x3F. This secret is effectively empty (all zeros), but is configured to be overwritten with the KFUSE private key once the KFUSE clock is enabled. The KFUSE private key is console-unique.
    
{| class=wikitable
 
{| class=wikitable
Retrieved from "https://switchbrew.org/wiki/Special:MobileDiff/6365...7496"

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