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TSEC (view source)

Revision as of 18:49, 23 August 2019

14,502 bytes added ,  18:49, 23 August 2019
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Line 8: Line 8:     
Registers from 0x54501000 to 0x54502000 are a MMIO window for communicating with the Falcon microprocessor. From this range, the subset of registers from 0x54501400 to 0x54501FE8 are specific to the TSEC and are subdivided into:
 
Registers from 0x54501000 to 0x54502000 are a MMIO window for communicating with the Falcon microprocessor. From this range, the subset of registers from 0x54501400 to 0x54501FE8 are specific to the TSEC and are subdivided into:
−
* 0x54501400 to 0x54501500: SCP (Secure Crypto Processor?).
+
* 0x54501400 to 0x54501500: SCP (Secure Co-Processor).
 
* 0x54501500 to 0x54501600: TRNG (True Random Number Generator).
 
* 0x54501500 to 0x54501600: TRNG (True Random Number Generator).
−
* 0x54501600 to 0x54501700: TFBIF (Tegra Framebuffer Interface).
+
* 0x54501600 to 0x54501700: TFBIF (Tegra Framebuffer Interface) and CG (Clock Gate).
−
* 0x54501700 to 0x54501800: DMA.
+
* 0x54501700 to 0x54501800: BAR0.
 
* 0x54501800 to 0x54501900: TEGRA (miscellaneous interfaces).  
 
* 0x54501800 to 0x54501900: TEGRA (miscellaneous interfaces).  
   Line 21: Line 21:  
| TSEC_THI_INCR_SYNCPT
 
| TSEC_THI_INCR_SYNCPT
 
| 0x54500000
 
| 0x54500000
 +
| 0x04
 +
|-
 +
| TSEC_THI_INCR_SYNCPT_CTRL
 +
| 0x54500004
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 33: Line 37:  
| TSEC_THI_CTXSW
 
| TSEC_THI_CTXSW
 
| 0x54500020
 
| 0x54500020
 +
| 0x04
 +
|-
 +
| TSEC_THI_CTXSW_NEXT
 +
| 0x54500024
 
| 0x04
 
| 0x04
 
|-
 
|-
 
| TSEC_THI_CONT_SYNCPT_EOF
 
| TSEC_THI_CONT_SYNCPT_EOF
 
| 0x54500028
 
| 0x54500028
 +
| 0x04
 +
|-
 +
| TSEC_THI_CONT_SYNCPT_L1
 +
| 0x5450002C
 +
| 0x04
 +
|-
 +
| TSEC_THI_STREAMID0
 +
| 0x54500030
 +
| 0x04
 +
|-
 +
| TSEC_THI_STREAMID1
 +
| 0x54500034
 +
| 0x04
 +
|-
 +
| TSEC_THI_THI_SEC
 +
| 0x54500038
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 45: Line 69:  
| [[#TSEC_THI_METHOD1|TSEC_THI_METHOD1]]
 
| [[#TSEC_THI_METHOD1|TSEC_THI_METHOD1]]
 
| 0x54500044
 
| 0x54500044
 +
| 0x04
 +
|-
 +
| TSEC_THI_CONTEXT_SWITCH
 +
| 0x54500060
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 55: Line 83:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_THI_SLCG_STATUS
+
| TSEC_THI_CONFIG0
 +
| 0x54500080
 +
| 0x04
 +
|-
 +
| TSEC_THI_DBG_MISC
 
| 0x54500084
 
| 0x54500084
 
| 0x04
 
| 0x04
Line 103: Line 135:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_GPTMR_PERIOD
+
| FALCON_GPTMRINT
 
| 0x54501020
 
| 0x54501020
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_GPTMR_TIME
+
| FALCON_GPTMRVAL
 
| 0x54501024
 
| 0x54501024
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_GPTMR_ENABLE
+
| FALCON_GPTMRCTL
 
| 0x54501028
 
| 0x54501028
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_TIME_LOW
+
| FALCON_PTIMER0
 
| 0x5450102C
 
| 0x5450102C
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_TIME_HIGH
+
| FALCON_PTIMER1
 
| 0x54501030
 
| 0x54501030
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_WDTMR_TIME
+
| FALCON_WDTMRVAL
 
| 0x54501034
 
| 0x54501034
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_WDTMR_ENABLE
+
| FALCON_WDTMRCTL
 
| 0x54501038
 
| 0x54501038
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_3C
+
| [[#FALCON_IRQDEST2|FALCON_IRQDEST2]]
 
| 0x5450103C
 
| 0x5450103C
 
| 0x04
 
| 0x04
Line 159: Line 191:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_CMDCTX
+
| FALCON_CTXACK
 
| 0x54501058
 
| 0x54501058
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_STATUS_MASK
+
| FALCON_FHSTATE
 
| 0x5450105C
 
| 0x5450105C
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_VM_SUPERVISOR
+
| FALCON_PRIVSTATE
 
| 0x54501060
 
| 0x54501060
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_MTHD_DATA
+
| FALCON_MTHDDATA
 
| 0x54501064
 
| 0x54501064
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_MTHD_CMD
+
| FALCON_MTHDID
 
| 0x54501068
 
| 0x54501068
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_MTHD_DATA_WR
+
| FALCON_MTHDWDAT
 
| 0x5450106C
 
| 0x5450106C
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_MTHD_OCCUPIED
+
| FALCON_MTHDCOUNT
 
| 0x54501070
 
| 0x54501070
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_MTHD_ACK
+
| FALCON_MTHDPOP
 
| 0x54501074
 
| 0x54501074
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_MTHD_LIMIT
+
| FALCON_MTHDRAMSZ
 
| 0x54501078
 
| 0x54501078
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_SUBENGINE_RESET
+
| FALCON_SFTRESET
 
| 0x5450107C
 
| 0x5450107C
 
| 0x04
 
| 0x04
Line 203: Line 235:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DEBUG0
+
| FALCON_RM
 
| 0x54501084
 
| 0x54501084
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_PM_SIGNAL
+
| FALCON_SOFT_PM
 
| 0x54501088
 
| 0x54501088
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_PM_MODE
+
| FALCON_SOFT_MODE
 
| 0x5450108C
 
| 0x5450108C
 
| 0x04
 
| 0x04
Line 223: Line 255:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_BREAKPOINT0
+
| FALCON_IBRKPT1
 
| 0x54501098
 
| 0x54501098
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_BREAKPOINT1
+
| FALCON_IBRKPT2
 
| 0x5450109C
 
| 0x5450109C
 
| 0x04
 
| 0x04
Line 239: Line 271:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_PM_SEL
+
| FALCON_PMM
 
| 0x545010A8
 
| 0x545010A8
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_HOST_IO_INDEX
+
| FALCON_ADDR
 
| 0x545010AC
 
| 0x545010AC
 +
| 0x04
 +
|-
 +
| FALCON_IBRKPT3
 +
| 0x545010B0
 +
| 0x04
 +
|-
 +
| FALCON_IBRKPT4
 +
| 0x545010B4
 +
| 0x04
 +
|-
 +
| FALCON_IBRKPT5
 +
| 0x545010B8
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 251: Line 295:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_D4
+
| [[#FALCON_SVEC_SPR|FALCON_SVEC_SPR]]
 
| 0x545010D4
 
| 0x545010D4
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_D8
+
| [[#FALCON_RSTAT0|FALCON_RSTAT0]]
 
| 0x545010D8
 
| 0x545010D8
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_DC
+
| [[#FALCON_RSTAT3|FALCON_RSTAT3]]
 
| 0x545010DC
 
| 0x545010DC
 
| 0x04
 
| 0x04
Line 283: Line 327:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_DMATRF_EXTBASE|FALCON_DMATRF_EXTBASE]]
+
| [[#FALCON_DMATRFBASE|FALCON_DMATRFBASE]]
 
| 0x54501110
 
| 0x54501110
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_DMATRF_VOFF|FALCON_DMATRF_VOFF]]
+
| [[#FALCON_DMATRFMOFFS|FALCON_DMATRFMOFFS]]
 
| 0x54501114
 
| 0x54501114
 
| 0x04
 
| 0x04
Line 295: Line 339:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_DMATRF_POFF|FALCON_DMATRF_POFF]]
+
| [[#FALCON_DMATRFFBOFFS|FALCON_DMATRFFBOFFS]]
 
| 0x5450111C
 
| 0x5450111C
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_DMATRFSTAT|FALCON_DMATRFSTAT]]
+
| [[#FALCON_DMAPOLL_FB|FALCON_DMAPOLL_FB]]
 
| 0x54501120
 
| 0x54501120
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_CRYPTTRFSTAT|FALCON_CRYPTTRFSTAT]]
+
| [[#FALCON_DMAPOLL_CP|FALCON_DMAPOLL_CP]]
 
| 0x54501124
 
| 0x54501124
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_CPUSTAT
+
| FALCON_DBG_STATE
 
| 0x54501128
 
| 0x54501128
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_HWCFG2|FALCON_HWCFG2]]
+
| [[#FALCON_HWCFG1|FALCON_HWCFG1]]
 
| 0x5450112C
 
| 0x5450112C
 
| 0x04
 
| 0x04
Line 317: Line 361:  
| FALCON_CPUCTL_ALIAS
 
| FALCON_CPUCTL_ALIAS
 
| 0x54501130
 
| 0x54501130
 +
| 0x04
 +
|-
 +
| FALCON_STACKCFG
 +
| 0x54501138
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 351: Line 399:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_EXTERRWIN
+
| FALCON_CMEMBASE
 
| 0x54501160
 
| 0x54501160
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_EXTERRCFG
+
| FALCON_DMEMAPERT
 
| 0x54501164
 
| 0x54501164
 
| 0x04
 
| 0x04
Line 371: Line 419:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_CODE_INDEX
+
| [[#FALCON_IMEMC0|FALCON_IMEMC0]]
 
| 0x54501180
 
| 0x54501180
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_CODE
+
| [[#FALCON_IMEMD0|FALCON_IMEMD0]]
 
| 0x54501184
 
| 0x54501184
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_CODE_VIRT_ADDR
+
| [[#FALCON_IMEMT0|FALCON_IMEMT0]]
 
| 0x54501188
 
| 0x54501188
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DATA_INDEX0
+
| FALCON_IMEMC1
−
| 0x545011C0
+
| 0x54501190
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DATA0
+
| FALCON_IMEMD1
−
| 0x545011C4
+
| 0x54501194
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DATA_INDEX1
+
| FALCON_IMEMT1
−
| 0x545011C8
+
| 0x54501198
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DATA1
+
| FALCON_IMEMC2
−
| 0x545011CC
+
| 0x545011A0
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DATA_INDEX2
+
| FALCON_IMEMD2
−
| 0x545011D0
+
| 0x545011A4
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DATA2
+
| FALCON_IMEMT2
−
| 0x545011D4
+
| 0x545011A8
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DATA_INDEX3
+
| FALCON_IMEMC3
−
| 0x545011D8
+
| 0x545011B0
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DATA3
+
| FALCON_IMEMD3
−
| 0x545011DC
+
| 0x545011B4
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DATA_INDEX4
+
| FALCON_IMEMT3
 +
| 0x545011B8
 +
| 0x04
 +
|-
 +
| [[#FALCON_DMEMC0|FALCON_DMEMC0]]
 +
| 0x545011C0
 +
| 0x04
 +
|-
 +
| [[#FALCON_DMEMD0|FALCON_DMEMD0]]
 +
| 0x545011C4
 +
| 0x04
 +
|-
 +
| FALCON_DMEMC1
 +
| 0x545011C8
 +
| 0x04
 +
|-
 +
| FALCON_DMEMD1
 +
| 0x545011CC
 +
| 0x04
 +
|-
 +
| FALCON_DMEMC2
 +
| 0x545011D0
 +
| 0x04
 +
|-
 +
| FALCON_DMEMD2
 +
| 0x545011D4
 +
| 0x04
 +
|-
 +
| FALCON_DMEMC3
 +
| 0x545011D8
 +
| 0x04
 +
|-
 +
| FALCON_DMEMD3
 +
| 0x545011DC
 +
| 0x04
 +
|-
 +
| FALCON_DMEMC4
 
| 0x545011E0
 
| 0x545011E0
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DATA4
+
| FALCON_DMEMD4
 
| 0x545011E4
 
| 0x545011E4
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DATA_INDEX5
+
| FALCON_DMEMC5
 
| 0x545011E8
 
| 0x545011E8
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DATA5
+
| FALCON_DMEMD5
 
| 0x545011EC
 
| 0x545011EC
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DATA_INDEX6
+
| FALCON_DMEMC6
 
| 0x545011F0
 
| 0x545011F0
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DATA6
+
| FALCON_DMEMD6
 
| 0x545011F4
 
| 0x545011F4
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DATA_INDEX7
+
| FALCON_DMEMC7
 
| 0x545011F8
 
| 0x545011F8
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_DATA7
+
| FALCON_DMEMD7
 
| 0x545011FC
 
| 0x545011FC
 
| 0x04
 
| 0x04
Line 451: Line 535:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_ICD_ADDR
+
| [[#FALCON_ICD_ADDR|FALCON_ICD_ADDR]]
 
| 0x54501204
 
| 0x54501204
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_ICD_WDATA
+
| [[#FALCON_ICD_WDATA|FALCON_ICD_WDATA]]
 
| 0x54501208
 
| 0x54501208
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_ICD_RDATA
+
| [[#FALCON_ICD_RDATA|FALCON_ICD_RDATA]]
 
| 0x5450120C
 
| 0x5450120C
 
| 0x04
 
| 0x04
Line 467: Line 551:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_SCTL_STAT|FALCON_SCTL_STAT]]
+
| [[#FALCON_SSTAT|FALCON_SSTAT]]
 
| 0x54501244
 
| 0x54501244
 
| 0x04
 
| 0x04
Line 481: Line 565:  
| FALCON_UNK_250
 
| FALCON_UNK_250
 
| 0x54501250
 
| 0x54501250
 +
| 0x04
 +
|-
 +
| FALCON_UNK_260
 +
| 0x54501260
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 515: Line 603:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_2E0
+
| FALCON_DMAINFO_FINISHED_FBRD_LOW
−
| 0x545012E0
+
| 0x545012C0
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_SCP_CTL0|TSEC_SCP_CTL0]]
+
| FALCON_DMAINFO_FINISHED_FBRD_HIGH
−
| 0x54501400
+
| 0x545012C4
 +
| 0x04
 +
|-
 +
| FALCON_DMAINFO_FINISHED_FBWR_LOW
 +
| 0x545012C8
 +
| 0x04
 +
|-
 +
| FALCON_DMAINFO_FINISHED_FBWR_HIGH
 +
| 0x545012CC
 +
| 0x04
 +
|-
 +
| FALCON_DMAINFO_CURRENT_FBRD_LOW
 +
| 0x545012D0
 +
| 0x04
 +
|-
 +
| FALCON_DMAINFO_CURRENT_FBRD_HIGH
 +
| 0x545012D4
 +
| 0x04
 +
|-
 +
| FALCON_DMAINFO_CURRENT_FBWR_LOW
 +
| 0x545012D8
 +
| 0x04
 +
|-
 +
| FALCON_DMAINFO_CURRENT_FBWR_HIGH
 +
| 0x545012DC
 +
| 0x04
 +
|-
 +
| FALCON_DMAINFO_CTL
 +
| 0x545012E0
 +
| 0x04
 +
|-
 +
| [[#TSEC_SCP_CTL0|TSEC_SCP_CTL0]]
 +
| 0x54501400
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 537: Line 657:  
| TSEC_SCP_UNK_10
 
| TSEC_SCP_UNK_10
 
| 0x54501410
 
| 0x54501410
 +
| 0x04
 +
|-
 +
| TSEC_SCP_UNK_14
 +
| 0x54501414
 
| 0x04
 
| 0x04
 
|-
 
|-
 
| [[#TSEC_SCP_CTL_PKEY|TSEC_SCP_CTL_PKEY]]
 
| [[#TSEC_SCP_CTL_PKEY|TSEC_SCP_CTL_PKEY]]
 
| 0x54501418
 
| 0x54501418
 +
| 0x04
 +
|-
 +
| TSEC_SCP_UNK_1C
 +
| 0x5450141C
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 557: Line 685:  
| [[#TSEC_SCP_INSN_STAT|TSEC_SCP_INSN_STAT]]
 
| [[#TSEC_SCP_INSN_STAT|TSEC_SCP_INSN_STAT]]
 
| 0x54501430
 
| 0x54501430
 +
| 0x04
 +
|-
 +
| TSEC_SCP_UNK_50
 +
| 0x54501450
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 579: Line 711:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_SCP_RES|TSEC_SCP_RES]]
+
| [[#TSEC_SCP_ACL_ERR|TSEC_SCP_ACL_ERR]]
 
| 0x54501490
 
| 0x54501490
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_SCP_ERR|TSEC_SCP_ERR]]
+
| TSEC_SCP_UNK_94
 +
| 0x54501494
 +
| 0x04
 +
|-
 +
| [[#TSEC_SCP_INSN_ERR|TSEC_SCP_INSN_ERR]]
 
| 0x54501498
 
| 0x54501498
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TRNG_CLKDIV
+
| TSEC_TRNG_CLK_LIMIT_LOW
 
| 0x54501500
 
| 0x54501500
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TRNG_UNK_04
+
| TSEC_TRNG_CLK_LIMIT_HIGH
 
| 0x54501504
 
| 0x54501504
 +
| 0x04
 +
|-
 +
| TSEC_TRNG_UNK_08
 +
| 0x54501508
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 613: Line 753:  
| TSEC_TRNG_TEST_SEED1
 
| TSEC_TRNG_TEST_SEED1
 
| 0x5450151C
 
| 0x5450151C
 +
| 0x04
 +
|-
 +
| TSEC_TRNG_UNK_20
 +
| 0x54501520
 +
| 0x04
 +
|-
 +
| TSEC_TRNG_UNK_24
 +
| 0x54501524
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 619: Line 767:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TRNG_UNK_2C
+
| TSEC_TRNG_CTL
 
| 0x5450152C
 
| 0x5450152C
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TFBIF_UNK_00
+
| [[#TSEC_TFBIF_CTL|TSEC_TFBIF_CTL]]
 
| 0x54501600
 
| 0x54501600
 
| 0x04
 
| 0x04
Line 631: Line 779:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TFBIF_UNK_08
+
| [[#TSEC_TFBIF_THROTTLE|TSEC_TFBIF_THROTTLE]]
 
| 0x54501608
 
| 0x54501608
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TFBIF_UNK_0C
+
| [[#TSEC_TFBIF_DBG_STAT0|TSEC_TFBIF_DBG_STAT0]]
 
| 0x5450160C
 
| 0x5450160C
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_STAT1
 +
| 0x54501610
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_RDCOUNT_LO
 +
| 0x54501614
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_RDCOUNT_HI
 +
| 0x54501618
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_WRCOUNT_LO
 +
| 0x5450161C
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_WRCOUNT_HI
 +
| 0x54501620
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_R32COUNT
 +
| 0x54501624
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_R64COUNT
 +
| 0x54501628
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_R128COUNT
 +
| 0x5450162C
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 647: Line 827:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TFBIF_UNK_40
+
| TSEC_TFBIF_WRR_RDP
 +
| 0x54501638
 +
| 0x04
 +
|-
 +
| [[#TSEC_TFBIF_SPROT_EMEM|TSEC_TFBIF_SPROT_EMEM]]
 
| 0x54501640
 
| 0x54501640
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_TFBIF_UNK_44|TSEC_TFBIF_UNK_44]]
+
| [[#TSEC_TFBIF_TRANSCFG|TSEC_TFBIF_TRANSCFG]]
 
| 0x54501644
 
| 0x54501644
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_TFBIF_UNK_48|TSEC_TFBIF_UNK_48]]
+
| [[#TSEC_TFBIF_REGIONCFG|TSEC_TFBIF_REGIONCFG]]
 
| 0x54501648
 
| 0x54501648
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_DMA_CMD|TSEC_DMA_CMD]]
+
| [[#TSEC_TFBIF_ACTMON_ACTIVE_MASK|TSEC_TFBIF_ACTMON_ACTIVE_MASK]]
−
| 0x54501700
+
| 0x5450164C
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_DMA_ADDR|TSEC_DMA_ADDR]]
+
| [[#TSEC_TFBIF_ACTMON_ACTIVE_BORPS|TSEC_TFBIF_ACTMON_ACTIVE_BORPS]]
−
| 0x54501704
+
| 0x54501650
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_DMA_VAL|TSEC_DMA_VAL]]
+
| [[#TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT|TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT]]
−
| 0x54501708
+
| 0x54501654
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_DMA_CFG|TSEC_DMA_CFG]]
+
| TSEC_TFBIF_ACTMON_MCB_MASK
−
| 0x5450170C
+
| 0x54501660
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_FALCON_IP_VER
+
| TSEC_TFBIF_ACTMON_MCB_BORPS
−
| 0x54501800
+
| 0x54501664
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_UNK_24
+
| TSEC_TFBIF_ACTMON_MCB_WEIGHT
−
| 0x54501824
+
| 0x54501668
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_UNK_28
+
| TSEC_TFBIF_THI_TRANSPROP
−
| 0x54501828
+
| 0x54501670
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_UNK_2C
+
| [[#TSEC_CG|TSEC_CG]]
−
| 0x5450182C
+
| 0x545016D0
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_TEGRA_CTL|TSEC_TEGRA_CTL]]
+
| [[#TSEC_BAR0_CTL|TSEC_BAR0_CTL]]
−
| 0x54501838
+
| 0x54501700
 
| 0x04
 
| 0x04
−
|}
  −
  −
=== TSEC_THI_METHOD0 ===
  −
{| class="wikitable" border="1"
  −
!  ID
  −
!  Method
   
|-
 
|-
−
| 0x200
+
| [[#TSEC_BAR0_ADDR|TSEC_BAR0_ADDR]]
−
| SET_APPLICATION_ID
+
| 0x54501704
 +
| 0x04
 
|-
 
|-
−
| 0x300
+
| [[#TSEC_BAR0_DATA|TSEC_BAR0_DATA]]
−
| EXECUTE
+
| 0x54501708
 +
| 0x04
 
|-
 
|-
−
| 0x500
+
| [[#TSEC_BAR0_TIMEOUT|TSEC_BAR0_TIMEOUT]]
−
| HDCP_INIT
+
| 0x5450170C
 +
| 0x04
 
|-
 
|-
−
| 0x504
+
| TSEC_TEGRA_FALCON_IP_VER
−
| HDCP_CREATE_SESSION
+
| 0x54501800
 +
| 0x04
 
|-
 
|-
−
| 0x508
+
| TSEC_TEGRA_UNK_04
−
| HDCP_VERIFY_CERT_RX
+
| 0x54501804
 +
| 0x04
 
|-
 
|-
−
| 0x50C
+
| TSEC_TEGRA_UNK_08
−
| HDCP_GENERATE_EKM
+
| 0x54501808
 +
| 0x04
 
|-
 
|-
−
| 0x510
+
| TSEC_TEGRA_UNK_0C
−
| HDCP_REVOCATION_CHECK
+
| 0x5450180C
 +
| 0x04
 
|-
 
|-
−
| 0x514
+
| TSEC_TEGRA_UNK_10
−
| HDCP_VERIFY_HPRIME
+
| 0x54501810
 +
| 0x04
 
|-
 
|-
−
| 0x518
+
| TSEC_TEGRA_UNK_14
−
| HDCP_ENCRYPT_PAIRING_INFO
+
| 0x54501814
 +
| 0x04
 
|-
 
|-
−
| 0x51C
+
| TSEC_TEGRA_UNK_18
−
| HDCP_DECRYPT_PAIRING_INFO
+
| 0x54501818
 +
| 0x04
 
|-
 
|-
−
| 0x520
+
| TSEC_TEGRA_UNK_1C
−
| HDCP_UPDATE_SESSION
+
| 0x5450181C
 +
| 0x04
 
|-
 
|-
−
| 0x524
+
| TSEC_TEGRA_UNK_20
−
| HDCP_GENERATE_LC_INIT
+
| 0x54501820
 +
| 0x04
 
|-
 
|-
−
| 0x528
+
| TSEC_TEGRA_UNK_24
−
| HDCP_VERIFY_LPRIME
+
| 0x54501824
 +
| 0x04
 
|-
 
|-
−
| 0x52C
+
| TSEC_TEGRA_UNK_28
−
| HDCP_GENERATE_SKE_INIT
+
| 0x54501828
 +
| 0x04
 
|-
 
|-
−
| 0x530
+
| TSEC_TEGRA_UNK_2C
−
| HDCP_VERIFY_VPRIME
+
| 0x5450182C
 +
| 0x04
 
|-
 
|-
−
| 0x534
+
| TSEC_TEGRA_UNK_30
−
| HDCP_ENCRYPTION_RUN_CTRL
+
| 0x54501830
 +
| 0x04
 
|-
 
|-
−
| 0x538
+
| TSEC_TEGRA_UNK_34
−
| HDCP_SESSION_CTRL
+
| 0x54501834
 +
| 0x04
 
|-
 
|-
−
| 0x53C
+
| [[#TSEC_TEGRA_CTL|TSEC_TEGRA_CTL]]
−
| HDCP_COMPUTE_SPRIME
+
| 0x54501838
 +
| 0x04
 +
|}
 +
 
 +
=== TSEC_THI_METHOD0 ===
 +
{| class="wikitable" border="1"
 +
!  ID
 +
!  Method
 
|-
 
|-
−
| 0x540
+
| 0x100
−
| HDCP_GET_CERT_RX
+
| NOP
 
|-
 
|-
−
| 0x544
+
| 0x140
−
| HDCP_EXCHANGE_INFO
+
| PM_TRIGGER
 
|-
 
|-
−
| 0x548
+
| 0x200
−
| HDCP_DECRYPT_KM
+
| SET_APPLICATION_ID
 
|-
 
|-
−
| 0x54C
+
| 0x204
−
| HDCP_GET_HPRIME
+
| SET_WATCHDOG_TIMER
 
|-
 
|-
−
| 0x550
+
| 0x240
−
| HDCP_GENERATE_EKH_KM
+
| SEMAPHORE_A
 
|-
 
|-
−
| 0x554
+
| 0x244
−
| HDCP_VERIFY_RTT_CHALLENGE
+
| SEMAPHORE_B
 
|-
 
|-
−
| 0x558
+
| 0x248
−
| HDCP_GET_LPRIME
+
| SEMAPHORE_C
 
|-
 
|-
−
| 0x55C
+
| 0x24C
−
| HDCP_DECRYPT_KS
+
|  
 
|-
 
|-
−
| 0x560
+
| 0x250
−
| HDCP_DECRYPT
+
|  
 
|-
 
|-
−
| 0x564
+
| 0x300
−
| HDCP_GET_RRX
+
| EXECUTE
 
|-
 
|-
−
| 0x568
+
| 0x304
−
| HDCP_DECRYPT_REENCRYPT
+
| SEMAPHORE_D
 
|-
 
|-
−
| 0x56C
+
| 0x500
−
|  
+
| HDCP_INIT
 
|-
 
|-
−
| 0x570
+
| 0x504
−
|  
+
| HDCP_CREATE_SESSION
 
|-
 
|-
−
| 0x574
+
| 0x508
−
|  
+
| HDCP_VERIFY_CERT_RX
 
|-
 
|-
−
| 0x578
+
| 0x50C
−
|  
+
| HDCP_GENERATE_EKM
 
|-
 
|-
−
| 0x57C
+
| 0x510
−
|  
+
| HDCP_REVOCATION_CHECK
 
|-
 
|-
−
| 0x700
+
| 0x514
−
| HDCP_VALIDATE_SRM
+
| HDCP_VERIFY_HPRIME
 
|-
 
|-
−
| 0x704
+
| 0x518
−
| HDCP_VALIDATE_STREAM
+
| HDCP_ENCRYPT_PAIRING_INFO
 
|-
 
|-
−
| 0x708
+
| 0x51C
−
| HDCP_TEST_SECURE_STATUS
+
| HDCP_DECRYPT_PAIRING_INFO
 
|-
 
|-
−
| 0x70C
+
| 0x520
−
| HDCP_SET_DCP_KPUB
+
| HDCP_UPDATE_SESSION
 
|-
 
|-
−
| 0x710
+
| 0x524
−
| HDCP_SET_RX_KPUB
+
| HDCP_GENERATE_LC_INIT
 
|-
 
|-
−
| 0x714
+
| 0x528
−
| HDCP_SET_CERT_RX
+
| HDCP_VERIFY_LPRIME
 
|-
 
|-
−
| 0x718
+
| 0x52C
−
| HDCP_SET_SCRATCH_BUFFER
+
| HDCP_GENERATE_SKE_INIT
 
|-
 
|-
−
| 0x71C
+
| 0x530
−
| HDCP_SET_SRM
+
| HDCP_VERIFY_VPRIME
 
|-
 
|-
−
| 0x720
+
| 0x534
−
| HDCP_SET_RECEIVER_ID_LIST
+
| HDCP_ENCRYPTION_RUN_CTRL
 
|-
 
|-
−
| 0x724
+
| 0x538
−
| HDCP_SET_SPRIME
+
| HDCP_SESSION_CTRL
 
|-
 
|-
−
| 0x728
+
| 0x53C
−
| HDCP_SET_ENC_INPUT_BUFFER
+
| HDCP_COMPUTE_SPRIME
 
|-
 
|-
−
| 0x72C
+
| 0x540
−
| HDCP_SET_ENC_OUTPUT_BUFFER
+
| HDCP_GET_CERT_RX
 
|-
 
|-
−
| 0x730
+
| 0x544
−
| HDCP_GET_RTT_CHALLENGE
+
| HDCP_EXCHANGE_INFO
 
|-
 
|-
−
| 0x734
+
| 0x548
−
| HDCP_STREAM_MANAGE
+
| HDCP_DECRYPT_KM
 
|-
 
|-
−
| 0x738
+
| 0x54C
−
| HDCP_READ_CAPS
+
| HDCP_GET_HPRIME
 
|-
 
|-
−
| 0x73C
+
| 0x550
−
| HDCP_ENCRYPT
+
| HDCP_GENERATE_EKH_KM
 
|-
 
|-
−
| 0x740
+
| 0x554
−
| [6.0.0+] HDCP_GET_CURRENT_NONCE
+
| HDCP_VERIFY_RTT_CHALLENGE
−
|}
+
|-
−
 
+
| 0x558
−
Used to encode and send a method's ID over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
+
| HDCP_GET_LPRIME
−
 
  −
=== TSEC_THI_METHOD1 ===
  −
Used to encode and send a method's data over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
  −
 
  −
=== TSEC_THI_INT_STATUS ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0
+
| 0x55C
−
| TSEC_THI_INT_STATUS_FALCON_INT
+
| HDCP_DECRYPT_KS
−
|}
  −
 
  −
=== TSEC_THI_INT_MASK ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0
+
| 0x560
−
| TSEC_THI_INT_MASK_FALCON_INT
+
| HDCP_DECRYPT
−
|}
  −
 
  −
=== FALCON_IRQSSET ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0
+
| 0x564
−
| FALCON_IRQSSET_GPTMR
+
| HDCP_GET_RRX
 
|-
 
|-
−
| 1
+
| 0x568
−
| FALCON_IRQSSET_WDTMR
+
| HDCP_DECRYPT_REENCRYPT
 
|-
 
|-
−
| 2
+
| 0x56C
−
| FALCON_IRQSSET_MTHD
+
|  
 
|-
 
|-
−
| 3
+
| 0x570
−
| FALCON_IRQSSET_CTXSW
+
|  
 
|-
 
|-
−
| 4
+
| 0x574
−
| FALCON_IRQSSET_HALT
+
|  
 
|-
 
|-
−
| 5
+
| 0x578
−
| FALCON_IRQSSET_EXTERR
+
|  
 
|-
 
|-
−
| 6
+
| 0x57C
−
| FALCON_IRQSSET_SWGEN0
+
|  
 
|-
 
|-
−
| 7
+
| 0x700
−
| FALCON_IRQSSET_SWGEN1
+
| HDCP_VALIDATE_SRM
 
|-
 
|-
−
| 8-15
+
| 0x704
−
| FALCON_IRQSSET_EXT
+
| HDCP_VALIDATE_STREAM
−
|}
  −
 
  −
Used for setting Falcon's IRQs.
  −
 
  −
=== FALCON_IRQSCLR ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0
+
| 0x708
−
| FALCON_IRQSCLR_GPTMR
+
| HDCP_TEST_SECURE_STATUS
 
|-
 
|-
−
| 1
+
| 0x70C
−
| FALCON_IRQSCLR_WDTMR
+
| HDCP_SET_DCP_KPUB
 
|-
 
|-
−
| 2
+
| 0x710
−
| FALCON_IRQSCLR_MTHD
+
| HDCP_SET_RX_KPUB
 
|-
 
|-
−
| 3
+
| 0x714
−
| FALCON_IRQSCLR_CTXSW
+
| HDCP_SET_CERT_RX
 
|-
 
|-
−
| 4
+
| 0x718
−
| FALCON_IRQSCLR_HALT
+
| HDCP_SET_SCRATCH_BUFFER
 
|-
 
|-
−
| 5
+
| 0x71C
−
| FALCON_IRQSCLR_EXTERR
+
| HDCP_SET_SRM
 
|-
 
|-
−
| 6
+
| 0x720
−
| FALCON_IRQSCLR_SWGEN0
+
| HDCP_SET_RECEIVER_ID_LIST
 
|-
 
|-
−
| 7
+
| 0x724
−
| FALCON_IRQSCLR_SWGEN1
+
| HDCP_SET_SPRIME
 
|-
 
|-
−
| 8-15
+
| 0x728
−
| FALCON_IRQSCLR_EXT
+
| HDCP_SET_ENC_INPUT_BUFFER
−
|}
  −
 
  −
Used for clearing Falcon's IRQs.
  −
 
  −
=== FALCON_IRQSTAT ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0
+
| 0x72C
−
| FALCON_IRQSTAT_GPTMR
+
| HDCP_SET_ENC_OUTPUT_BUFFER
 
|-
 
|-
−
| 1
+
| 0x730
−
| FALCON_IRQSTAT_WDTMR
+
| HDCP_GET_RTT_CHALLENGE
 
|-
 
|-
−
| 2
+
| 0x734
−
| FALCON_IRQSTAT_MTHD
+
| HDCP_STREAM_MANAGE
 
|-
 
|-
−
| 3
+
| 0x738
−
| FALCON_IRQSTAT_CTXSW
+
| HDCP_READ_CAPS
 
|-
 
|-
−
| 4
+
| 0x73C
−
| FALCON_IRQSTAT_HALT
+
| HDCP_ENCRYPT
 
|-
 
|-
−
| 5
+
| 0x740
−
| FALCON_IRQSTAT_EXTERR
+
| [6.0.0+] HDCP_GET_CURRENT_NONCE
−
|-
  −
| 6
  −
| FALCON_IRQSTAT_SWGEN0
  −
|-
  −
| 7
  −
| FALCON_IRQSTAT_SWGEN1
   
|-
 
|-
−
| 8-15
+
| 0x1114
−
| FALCON_IRQSTAT_EXT
+
| PM_TRIGGER_END
 
|}
 
|}
   −
Used for getting the status of Falcon's IRQs.
+
Used to encode and send a method's ID over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
   −
=== FALCON_IRQMODE ===
+
=== TSEC_THI_METHOD1 ===
 +
Used to encode and send a method's data over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
 +
 
 +
=== TSEC_THI_INT_STATUS ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_THI_INT_STATUS_FALCON_INT
 +
|}
 +
 
 +
=== TSEC_THI_INT_MASK ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_THI_INT_MASK_FALCON_INT
 +
|}
 +
 
 +
=== FALCON_IRQSSET ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 989: Line 1,170:  
|-
 
|-
 
| 0
 
| 0
−
| FALCON_IRQMODE_GPTMR
+
| FALCON_IRQSSET_GPTMR
 
|-
 
|-
 
| 1
 
| 1
−
| FALCON_IRQMODE_WDTMR
+
| FALCON_IRQSSET_WDTMR
 
|-
 
|-
 
| 2
 
| 2
−
| FALCON_IRQMODE_MTHD
+
| FALCON_IRQSSET_MTHD
 
|-
 
|-
 
| 3
 
| 3
−
| FALCON_IRQMODE_CTXSW
+
| FALCON_IRQSSET_CTXSW
 
|-
 
|-
 
| 4
 
| 4
−
| FALCON_IRQMODE_HALT
+
| FALCON_IRQSSET_HALT
 
|-
 
|-
 
| 5
 
| 5
−
| FALCON_IRQMODE_EXTERR
+
| FALCON_IRQSSET_EXTERR
 
|-
 
|-
 
| 6
 
| 6
−
| FALCON_IRQMODE_SWGEN0
+
| FALCON_IRQSSET_SWGEN0
 
|-
 
|-
 
| 7
 
| 7
−
| FALCON_IRQMODE_SWGEN1
+
| FALCON_IRQSSET_SWGEN1
 
|-
 
|-
 
| 8-15
 
| 8-15
−
| FALCON_IRQMODE_EXT
+
| FALCON_IRQSSET_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQSSET_DMA
 
|}
 
|}
   −
Used for changing the mode Falcon's IRQs. A value of 1 means level triggered while a value of 0 means edge triggered.
+
Used for setting Falcon's IRQs.
   −
=== FALCON_IRQMSET ===
+
=== FALCON_IRQSCLR ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,024: Line 1,208:  
|-
 
|-
 
| 0
 
| 0
−
| FALCON_IRQMSET_GPTMR
+
| FALCON_IRQSCLR_GPTMR
 
|-
 
|-
 
| 1
 
| 1
−
| FALCON_IRQMSET_WDTMR
+
| FALCON_IRQSCLR_WDTMR
 
|-
 
|-
 
| 2
 
| 2
−
| FALCON_IRQMSET_MTHD
+
| FALCON_IRQSCLR_MTHD
 
|-
 
|-
 
| 3
 
| 3
−
| FALCON_IRQMSET_CTXSW
+
| FALCON_IRQSCLR_CTXSW
 
|-
 
|-
 
| 4
 
| 4
−
| FALCON_IRQMSET_HALT
+
| FALCON_IRQSCLR_HALT
 
|-
 
|-
 
| 5
 
| 5
−
| FALCON_IRQMSET_EXTERR
+
| FALCON_IRQSCLR_EXTERR
 
|-
 
|-
 
| 6
 
| 6
−
| FALCON_IRQMSET_SWGEN0
+
| FALCON_IRQSCLR_SWGEN0
 
|-
 
|-
 
| 7
 
| 7
−
| FALCON_IRQMSET_SWGEN1
+
| FALCON_IRQSCLR_SWGEN1
 
|-
 
|-
 
| 8-15
 
| 8-15
−
| FALCON_IRQMSET_EXT
+
| FALCON_IRQSCLR_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQSCLR_DMA
 
|}
 
|}
   −
Used for setting the mask for Falcon's IRQs.
+
Used for clearing Falcon's IRQs.
   −
=== FALCON_IRQMCLR ===
+
=== FALCON_IRQSTAT ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,059: Line 1,246:  
|-
 
|-
 
| 0
 
| 0
−
| FALCON_IRQMCLR_GPTMR
+
| FALCON_IRQSTAT_GPTMR
 
|-
 
|-
 
| 1
 
| 1
−
| FALCON_IRQMCLR_WDTMR
+
| FALCON_IRQSTAT_WDTMR
 
|-
 
|-
 
| 2
 
| 2
−
| FALCON_IRQMCLR_MTHD
+
| FALCON_IRQSTAT_MTHD
 
|-
 
|-
 
| 3
 
| 3
−
| FALCON_IRQMCLR_CTXSW
+
| FALCON_IRQSTAT_CTXSW
 
|-
 
|-
 
| 4
 
| 4
−
| FALCON_IRQMCLR_HALT
+
| FALCON_IRQSTAT_HALT
 
|-
 
|-
 
| 5
 
| 5
−
| FALCON_IRQMCLR_EXTERR
+
| FALCON_IRQSTAT_EXTERR
 
|-
 
|-
 
| 6
 
| 6
−
| FALCON_IRQMCLR_SWGEN0
+
| FALCON_IRQSTAT_SWGEN0
 
|-
 
|-
 
| 7
 
| 7
−
| FALCON_IRQMCLR_SWGEN1
+
| FALCON_IRQSTAT_SWGEN1
 
|-
 
|-
 
| 8-15
 
| 8-15
−
| FALCON_IRQMCLR_EXT
+
| FALCON_IRQSTAT_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQSTAT_DMA
 
|}
 
|}
   −
Used for clearing the mask for Falcon's IRQs.
+
Used for getting the status of Falcon's IRQs.
   −
=== FALCON_IRQMASK ===
+
=== FALCON_IRQMODE ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,094: Line 1,284:  
|-
 
|-
 
| 0
 
| 0
−
| FALCON_IRQMASK_GPTMR
+
| FALCON_IRQMODE_LVL_GPTMR
 
|-
 
|-
 
| 1
 
| 1
−
| FALCON_IRQMASK_WDTMR
+
| FALCON_IRQMODE_LVL_WDTMR
 
|-
 
|-
 
| 2
 
| 2
−
| FALCON_IRQMASK_MTHD
+
| FALCON_IRQMODE_LVL_MTHD
 
|-
 
|-
 
| 3
 
| 3
−
| FALCON_IRQMASK_CTXSW
+
| FALCON_IRQMODE_LVL_CTXSW
 
|-
 
|-
 
| 4
 
| 4
−
| FALCON_IRQMASK_HALT
+
| FALCON_IRQMODE_LVL_HALT
 
|-
 
|-
 
| 5
 
| 5
−
| FALCON_IRQMASK_EXTERR
+
| FALCON_IRQMODE_LVL_EXTERR
 
|-
 
|-
 
| 6
 
| 6
−
| FALCON_IRQMASK_SWGEN0
+
| FALCON_IRQMODE_LVL_SWGEN0
 
|-
 
|-
 
| 7
 
| 7
−
| FALCON_IRQMASK_SWGEN1
+
| FALCON_IRQMODE_LVL_SWGEN1
 
|-
 
|-
 
| 8-15
 
| 8-15
−
| FALCON_IRQMASK_EXT
+
| FALCON_IRQMODE_LVL_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQMODE_LVL_DMA
 
|}
 
|}
   −
Used for getting the value of the mask for Falcon's IRQs.
+
Used for changing the mode Falcon's IRQs. A value of 1 means level triggered while a value of 0 means edge triggered.
   −
=== FALCON_IRQDEST ===
+
=== FALCON_IRQMSET ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,129: Line 1,322:  
|-
 
|-
 
| 0
 
| 0
−
| FALCON_IRQDEST_HOST_GPTMR
+
| FALCON_IRQMSET_GPTMR
 
|-
 
|-
 
| 1
 
| 1
−
| FALCON_IRQDEST_HOST_WDTMR
+
| FALCON_IRQMSET_WDTMR
 
|-
 
|-
 
| 2
 
| 2
−
| FALCON_IRQDEST_HOST_MTHD
+
| FALCON_IRQMSET_MTHD
 
|-
 
|-
 
| 3
 
| 3
−
| FALCON_IRQDEST_HOST_CTXSW
+
| FALCON_IRQMSET_CTXSW
 
|-
 
|-
 
| 4
 
| 4
−
| FALCON_IRQDEST_HOST_HALT
+
| FALCON_IRQMSET_HALT
 
|-
 
|-
 
| 5
 
| 5
−
| FALCON_IRQDEST_HOST_EXTERR
+
| FALCON_IRQMSET_EXTERR
 
|-
 
|-
 
| 6
 
| 6
−
| FALCON_IRQDEST_HOST_SWGEN0
+
| FALCON_IRQMSET_SWGEN0
 
|-
 
|-
 
| 7
 
| 7
−
| FALCON_IRQDEST_HOST_SWGEN1
+
| FALCON_IRQMSET_SWGEN1
 
|-
 
|-
 
| 8-15
 
| 8-15
−
| FALCON_IRQDEST_HOST_EXT
+
| FALCON_IRQMSET_EXT
 
|-
 
|-
 
| 16
 
| 16
−
| FALCON_IRQDEST_TARGET_GPTMR
+
| FALCON_IRQMSET_DMA
 +
|}
 +
 
 +
Used for setting the mask for Falcon's IRQs.
 +
 
 +
=== FALCON_IRQMCLR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| 17
+
| 0
−
| FALCON_IRQDEST_TARGET_WDTMR
+
| FALCON_IRQMCLR_GPTMR
 
|-
 
|-
−
| 18
+
| 1
−
| FALCON_IRQDEST_TARGET_MTHD
+
| FALCON_IRQMCLR_WDTMR
 
|-
 
|-
−
| 19
+
| 2
−
| FALCON_IRQDEST_TARGET_CTXSW
+
| FALCON_IRQMCLR_MTHD
 
|-
 
|-
−
| 20
+
| 3
−
| FALCON_IRQDEST_TARGET_HALT
+
| FALCON_IRQMCLR_CTXSW
 
|-
 
|-
−
| 21
+
| 4
−
| FALCON_IRQDEST_TARGET_EXTERR
+
| FALCON_IRQMCLR_HALT
 
|-
 
|-
−
| 22
+
| 5
−
| FALCON_IRQDEST_TARGET_SWGEN0
+
| FALCON_IRQMCLR_EXTERR
 
|-
 
|-
−
| 23
+
| 6
−
| FALCON_IRQDEST_TARGET_SWGEN1
+
| FALCON_IRQMCLR_SWGEN0
 
|-
 
|-
−
| 24-31
+
| 7
−
| FALCON_IRQDEST_TARGET_EXT
+
| FALCON_IRQMCLR_SWGEN1
 +
|-
 +
| 8-15
 +
| FALCON_IRQMCLR_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQMCLR_DMA
 
|}
 
|}
   −
Used for routing Falcon's IRQs.
+
Used for clearing the mask for Falcon's IRQs.
   −
=== FALCON_MAILBOX0 ===
+
=== FALCON_IRQMASK ===
−
Scratch register for reading/writing data to Falcon.
  −
 
  −
=== FALCON_MAILBOX1 ===
  −
Scratch register for reading/writing data to Falcon.
  −
 
  −
=== FALCON_ITFEN ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,197: Line 1,398:  
|-
 
|-
 
| 0
 
| 0
−
| FALCON_ITFEN_CTXEN
+
| FALCON_IRQMASK_GPTMR
 
|-
 
|-
 
| 1
 
| 1
−
| FALCON_ITFEN_MTHDEN
+
| FALCON_IRQMASK_WDTMR
−
|}
  −
 
  −
Used for enabling/disabling Falcon interfaces.
  −
 
  −
=== FALCON_IDLESTATE ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0
+
| 2
−
| FALCON_IDLESTATE_FALCON_BUSY
+
| FALCON_IRQMASK_MTHD
 
|-
 
|-
−
| 1-15
+
| 3
−
| FALCON_IDLESTATE_EXT_BUSY
+
| FALCON_IRQMASK_CTXSW
 +
|-
 +
| 4
 +
| FALCON_IRQMASK_HALT
 +
|-
 +
| 5
 +
| FALCON_IRQMASK_EXTERR
 +
|-
 +
| 6
 +
| FALCON_IRQMASK_SWGEN0
 +
|-
 +
| 7
 +
| FALCON_IRQMASK_SWGEN1
 +
|-
 +
| 8-15
 +
| FALCON_IRQMASK_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQMASK_DMA
 
|}
 
|}
   −
Used for detecting if Falcon is busy or not.
+
Used for getting the value of the mask for Falcon's IRQs.
   −
=== FALCON_DEBUG1 ===
+
=== FALCON_IRQDEST ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 16
+
| 0
−
| FALCON_DEBUG1_CTXSW_MODE
+
| FALCON_IRQDEST_HOST_GPTMR
−
|}
+
|-
−
 
+
| 1
−
=== FALCON_DEBUGINFO ===
+
| FALCON_IRQDEST_HOST_WDTMR
−
Used for UCODE self revocation. This register takes the base address of the GSC carveout shifted right by 8.
  −
 
  −
[6.0.0+] [[NV_services|nvservices]] sets this to 0x8005FF00 >> 8 (physical DRAM address inside the GPU UCODE carveout) before starting the nvhost_tsec firmware.
  −
 
  −
=== FALCON_EXCI ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
  −
|-
  −
| 0-19
  −
| PC that originated the exception
  −
|-
  −
| 20-23
  −
| Exception type
  −
0x00: Trap 0
  −
0x01: Trap 1
  −
0x02: Trap 2
  −
0x03: Trap 3
  −
0x08: Invalid opcode
  −
0x09: Authentication failure
  −
0x0A: Page fault (no hit)
  −
0x0B: Page fault (multi hit)
  −
0x0F: Breakpoint
  −
|}
  −
 
  −
Contains information about raised exceptions.
  −
 
  −
=== FALCON_CPUCTL ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
  −
|-
  −
| 0
  −
| FALCON_CPUCTL_IINVAL
  −
|-
  −
| 1
  −
| FALCON_CPUCTL_STARTCPU
   
|-
 
|-
 
| 2
 
| 2
−
| FALCON_CPUCTL_SRESET
+
| FALCON_IRQDEST_HOST_MTHD
 
|-
 
|-
 
| 3
 
| 3
−
| FALCON_CPUCTL_HRESET
+
| FALCON_IRQDEST_HOST_CTXSW
 
|-
 
|-
 
| 4
 
| 4
−
| FALCON_CPUCTL_HALTED
+
| FALCON_IRQDEST_HOST_HALT
 
|-
 
|-
 
| 5
 
| 5
−
| FALCON_CPUCTL_STOPPED
+
| FALCON_IRQDEST_HOST_EXTERR
 
|-
 
|-
 
| 6
 
| 6
−
| FALCON_CPUCTL_STARTCPU_SECURE
+
| FALCON_IRQDEST_HOST_SWGEN0
−
|}
+
|-
−
 
+
| 7
−
Used for signaling the Falcon CPU.
+
| FALCON_IRQDEST_HOST_SWGEN1
−
 
  −
=== FALCON_BOOTVEC ===
  −
Takes the Falcon's boot vector address.
  −
 
  −
=== FALCON_HWCFG ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0-8
+
| 8-15
−
| FALCON_HWCFG_IMEM_SIZE
+
| FALCON_IRQDEST_HOST_EXT
 
|-
 
|-
−
| 9-17
+
| 16
−
| FALCON_HWCFG_DMEM_SIZE
+
| FALCON_IRQDEST_TARGET_GPTMR
 
|-
 
|-
−
| 18-25
+
| 17
−
| FALCON_HWCFG_MTHD_SIZE
+
| FALCON_IRQDEST_TARGET_WDTMR
 
|-
 
|-
−
| 26-31
+
| 18
−
| FALCON_HWCFG_DMATRF_SLOTS
+
| FALCON_IRQDEST_TARGET_MTHD
−
|}
+
|-
−
 
+
| 19
−
=== FALCON_DMACTL ===
+
| FALCON_IRQDEST_TARGET_CTXSW
−
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0
+
| 20
−
| FALCON_DMACTL_REQUIRE_CTX
+
| FALCON_IRQDEST_TARGET_HALT
 
|-
 
|-
−
| 1
+
| 21
−
| FALCON_DMACTL_DMEM_SCRUBBING
+
| FALCON_IRQDEST_TARGET_EXTERR
 
|-
 
|-
−
| 2
+
| 22
−
| FALCON_DMACTL_IMEM_SCRUBBING
+
| FALCON_IRQDEST_TARGET_SWGEN0
 
|-
 
|-
−
| 3-6
+
| 23
−
| FALCON_DMACTL_DMAQ_NUM
+
| FALCON_IRQDEST_TARGET_SWGEN1
 
|-
 
|-
−
| 7
+
| 24-31
−
| FALCON_DMACTL_SECURE_STAT
+
| FALCON_IRQDEST_TARGET_EXT
 
|}
 
|}
   −
Used for configuring the Falcon's DMA engine.
+
Used for routing Falcon's IRQs.
   −
=== FALCON_DMATRF_EXTBASE ===
+
=== FALCON_IRQDEST2 ===
−
Base of the external memory buffer.
+
{| class="wikitable" border="1"
−
 
+
!  Bits
−
The base of the transfer is calculated by adding [[#FALCON_DMATRF_POFF]] to the base.
+
!  Description
 +
|-
 +
| 0
 +
| FALCON_IRQDEST2_HOST_DMA
 +
|-
 +
| 16
 +
| FALCON_IRQDEST2_TARGET_DMA
 +
|}
 +
 
 +
Used for routing Falcon's IRQs.
   −
=== FALCON_DMATRF_VOFF ===
+
=== FALCON_MAILBOX0 ===
−
For transfers to DMEM: the destination address.
+
Scratch register for reading/writing data to Falcon.
−
For transfers to IMEM: the destination virtual IMEM page.
     −
=== FALCON_DMATRF_POFF ===
+
=== FALCON_MAILBOX1 ===
−
For transfers to IMEM: the destination physical IMEM page.
+
Scratch register for reading/writing data to Falcon.
   −
=== FALCON_DMATRFCMD ===
+
=== FALCON_ITFEN ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,347: Line 1,518:  
|-
 
|-
 
| 0
 
| 0
−
| FALCON_DMATRFCMD_FULL
+
| FALCON_ITFEN_CTXEN
 
|-
 
|-
 
| 1
 
| 1
−
| FALCON_DMATRFCMD_IDLE
+
| FALCON_ITFEN_MTHDEN
 +
|}
 +
 
 +
Used for enabling/disabling Falcon interfaces.
 +
 
 +
=== FALCON_IDLESTATE ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| 2-3
+
| 0
−
| FALCON_DMATRFCMD_SEC
+
| FALCON_IDLESTATE_FALCON_BUSY
 
|-
 
|-
−
| 4
+
| 1-15
−
| FALCON_DMATRFCMD_IMEM
+
| FALCON_IDLESTATE_EXT_BUSY
−
|-
  −
| 5
  −
| FALCON_DMATRFCMD_WRITE
  −
|-
  −
| 8-10
  −
| FALCON_DMATRFCMD_SIZE
  −
|-
  −
| 12-14
  −
| FALCON_DMATRFCMD_CTXDMA
   
|}
 
|}
   −
Used for configuring DMA transfers.
+
Used for detecting if Falcon is busy or not.
   −
=== FALCON_DMATRFSTAT ===
+
=== FALCON_DEBUG1 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-15
−
| FALCON_DMATRFSTAT_PENDING
+
| FALCON_DEBUG1_MTHD_DRAIN_TIME
 
|-
 
|-
−
| 16-18
+
| 16
−
| FALCON_DMATRFSTAT_NUM_STORES_PENDING
+
| FALCON_DEBUG1_CTXSW_MODE
 
|-
 
|-
−
| 24-26
+
| 17
−
| FALCON_DMATRFSTAT_NUM_LOADS_PENDING
+
| FALCON_DEBUG1_TRACE_FORMAT
 
|}
 
|}
   −
=== FALCON_CRYPTTRFSTAT ===
+
=== FALCON_DEBUGINFO ===
 +
Used for UCODE self revocation. This register takes the base address of the GSC carveout shifted right by 8.
 +
 
 +
[6.0.0+] [[NV_services|nvservices]] sets this to 0x8005FF00 >> 8 (physical DRAM address inside the GPU UCODE carveout) before starting the nvhost_tsec firmware.
 +
 
 +
=== FALCON_EXCI ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 1
+
| 0-19
−
| FALCON_CRYPTTRFSTAT_PENDING
+
| FALCON_EXCI_EXPC
 
|-
 
|-
−
| 5
+
| 20-23
−
| FALCON_CRYPTTRFSTAT_ENABLED
+
| FALCON_EXCI_EXCAUSE
−
|-
+
0x00: TRAP0
−
| 16-18
+
0x01: TRAP1
−
| FALCON_CRYPTTRFSTAT_NUM_STORES_PENDING
+
0x02: TRAP2
−
|-
+
0x03: TRAP3
−
| 24-26
+
0x08: ILL_INS (invalid opcode)
−
| FALCON_CRYPTTRFSTAT_NUM_LOADS_PENDING
+
0x09: INV_INS (authentication entry)
 +
0x0A: MISS_INS (page miss)
 +
0x0B: DHIT_INS (page multiple hit)
 +
0x0F: BRKPT_INS (breakpoint hit)
 
|}
 
|}
   −
=== FALCON_HWCFG2 ===
+
Contains information about raised exceptions.
 +
 
 +
=== FALCON_SVEC_SPR ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 18
−
| FALCON_HWCFG2_VERSION
+
| FALCON_SVEC_SPR_SIGPASS
−
|-
  −
| 4-5
  −
| FALCON_HWCFG2_SCP_MODE
  −
|-
  −
| 6-7
  −
| FALCON_HWCFG2_SUBVERSION
  −
|-
  −
| 8-11
  −
| FALCON_HWCFG2_IMEM_PORTS
  −
|-
  −
| 12-15
  −
| FALCON_HWCFG2_DMEM_PORTS
  −
|-
  −
| 16-19
  −
| FALCON_HWCFG2_VM_PAGES_LOG2
   
|}
 
|}
   −
=== FALCON_IMCTL ===
+
=== FALCON_RSTAT0 ===
 +
Mirror of the ICD status register 0.
 +
 
 +
=== FALCON_RSTAT3 ===
 +
Mirror of the ICD status register 3.
 +
 
 +
=== FALCON_CPUCTL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-23
+
| 0
−
| Address
+
| FALCON_CPUCTL_IINVAL
 
|-
 
|-
−
| 24-26
+
| 1
−
| Command
+
| FALCON_CPUCTL_STARTCPU
−
1: ITLB
+
|-
−
2: PTLB
+
| 2
−
3: VTLB
+
| FALCON_CPUCTL_SRESET
−
|}
+
|-
 +
| 3
 +
| FALCON_CPUCTL_HRESET
 +
|-
 +
| 4
 +
| FALCON_CPUCTL_HALTED
 +
|-
 +
| 5
 +
| FALCON_CPUCTL_STOPPED
 +
|-
 +
| 6
 +
| FALCON_CPUCTL_ALIAS_EN
 +
|}
   −
Controls the Falcon TLB.
+
Used for signaling the Falcon CPU.
   −
=== FALCON_IMSTAT ===
+
=== FALCON_BOOTVEC ===
−
Returns the result of the last command from [[#FALCON_IMCTL|FALCON_IMCTL]].
+
Takes the Falcon's boot vector address.
   −
=== FALCON_TRACEIDX ===
+
=== FALCON_HWCFG ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-7
+
| 0-8
−
| Index
+
| FALCON_HWCFG_IMEM_SIZE
 +
|-
 +
| 9-17
 +
| FALCON_HWCFG_DMEM_SIZE
 +
|-
 +
| 18-26
 +
| FALCON_HWCFG_METHODFIFO_DEPTH
 
|-
 
|-
−
| 16-23
+
| 27-31
−
| Maximum valid index
+
| FALCON_HWCFG_DMAQUEUE_DEPTH
 
|}
 
|}
   −
Controls the index for tracing with [[#FALCON_TRACEPC|FALCON_TRACEPC]].
+
=== FALCON_DMACTL ===
−
 
  −
=== FALCON_TRACEPC ===
  −
Returns the PC of the last instruction executed.
  −
 
  −
=== FALCON_ICD_CMD ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 0
−
| FALCON_ICD_CMD_OPC
+
| FALCON_DMACTL_REQUIRE_CTX
−
0x0: BREAK
  −
0x1: CONTINUE_FROM_PC
  −
0x2: CONTINUE_FROM_ADDR
  −
0x3: CONTINUE_UNK1_FROM_PC
  −
0x4: CONTINUE_UNK1_FROM_ADDR
  −
0x5: SINGLE_STEP_FROM_PC
  −
0x6: SINGLE_STEP_FROM_ADDR
  −
0x7: SET_BREAK_MASK
  −
0x8: REG_READ
  −
0x9: REG_WRITE
  −
0xA: DATA_READ
  −
0xB: DATA_WRITE
  −
0xC: IO_READ
  −
0xD: IO_WRITE
  −
0xE: STATUS_READ
   
|-
 
|-
−
| 6-7
+
| 1
−
| FALCON_ICD_CMD_DATA_SIZE
+
| FALCON_DMACTL_DMEM_SCRUBBING
 
|-
 
|-
−
| 8-12
+
| 2
−
| FALCON_ICD_CMD_IDX
+
| FALCON_DMACTL_IMEM_SCRUBBING
 
|-
 
|-
−
| 14
+
| 3-6
−
| FALCON_ICD_CMD_ERROR
+
| FALCON_DMACTL_DMAQ_NUM
 
|-
 
|-
−
| 15
+
| 7
−
| FALCON_ICD_CMD_DONE
+
| FALCON_DMACTL_SECURE_STAT
−
|-
  −
| 16-31
  −
| FALCON_ICD_CMD_BREAK_MASK
   
|}
 
|}
   −
=== FALCON_SCTL ===
+
Used for configuring the Falcon's DMA engine.
−
{| class="wikitable" border="1"
+
 
−
!  Bits
+
=== FALCON_DMATRFBASE ===
 +
Base address of the external memory buffer, shifted right by 8.
 +
 
 +
The current transfer address is calculated by adding [[#FALCON_DMATRFFBOFFS|FALCON_DMATRFFBOFFS]] to the base.
 +
 
 +
=== FALCON_DMATRFMOFFS ===
 +
For transfers to DMEM: the destination address.
 +
For transfers to IMEM: the destination virtual IMEM page.
 +
 
 +
=== FALCON_DMATRFCMD ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-1
+
| 0
−
| FALCON_SCTL_SEC_MODE
+
| FALCON_DMATRFCMD_FULL
−
0: Non-secure
  −
1: Light Secure
  −
2: Heavy Secure
   
|-
 
|-
−
| 4-5
+
| 1
−
| FALCON_SCTL_OLD_SEC_MODE
+
| FALCON_DMATRFCMD_IDLE
−
0: Non-secure
  −
1: Light Secure
  −
2: Heavy Secure
   
|-
 
|-
−
| 12-13
+
| 2-3
−
| Unknown
+
| FALCON_DMATRFCMD_SEC
−
|-
  −
| 14
  −
| Initialize the transition to LS mode
  −
|}
  −
 
  −
=== FALCON_SCTL_STAT ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 31
+
| 4
−
| Set on memory protection violation
+
| FALCON_DMATRFCMD_IMEM
−
|}
+
|-
−
 
+
| 5
−
=== FALCON_SPROT_IMEM ===
+
| FALCON_DMATRFCMD_WRITE
−
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0-3
+
| 8-10
−
| Read access level
+
| FALCON_DMATRFCMD_SIZE
 
|-
 
|-
−
| 4-7
+
| 12-14
−
| Write access level
+
| FALCON_DMATRFCMD_CTXDMA
 
|}
 
|}
   −
Controls accesses to Falcon IMEM.
+
Used for configuring DMA transfers.
 +
 
 +
=== FALCON_DMATRFFBOFFS ===
 +
For transfers to IMEM: the destination physical IMEM page.
   −
=== FALCON_SPROT_DMEM ===
+
=== FALCON_DMAPOLL_FB ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 0
−
| Read access level
+
| FALCON_DMAPOLL_FB_FENCE_ACTIVE
 +
|-
 +
| 1
 +
| FALCON_DMAPOLL_FB_DMA_ACTIVE
 
|-
 
|-
−
| 4-7
+
| 4
−
| Write access level
+
| FALCON_DMAPOLL_FB_CFG_R_FENCE
 +
|-
 +
| 5
 +
| FALCON_DMAPOLL_FB_CFG_W_FENCE
 +
|-
 +
| 16-23
 +
| FALCON_DMAPOLL_FB_WCOUNT
 +
|-
 +
| 24-31
 +
| FALCON_DMAPOLL_FB_RCOUNT
 
|}
 
|}
   −
Controls accesses to Falcon DMEM.
+
Contains the status of a DMA transfer between the Falcon and external memory.
   −
=== FALCON_SPROT_CPUCTL ===
+
=== FALCON_DMAPOLL_CP ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 0
−
| Read access level
+
| FALCON_DMAPOLL_CP_FENCE_ACTIVE
 +
|-
 +
| 1
 +
| FALCON_DMAPOLL_CP_DMA_ACTIVE
 +
|-
 +
| 4
 +
| FALCON_DMAPOLL_CP_CFG_R_FENCE
 +
|-
 +
| 5
 +
| FALCON_DMAPOLL_CP_CFG_W_FENCE
 +
|-
 +
| 16-23
 +
| FALCON_DMAPOLL_CP_WCOUNT
 
|-
 
|-
−
| 4-7
+
| 24-31
−
| Write access level
+
| FALCON_DMAPOLL_CP_RCOUNT
 
|}
 
|}
   −
Controls accesses to the [[#FALCON_CPUCTL|FALCON_CPUCTL]] register.
+
Contains the status of a DMA transfer between the Falcon and the SCP.
   −
=== FALCON_SPROT_MISC ===
+
=== FALCON_HWCFG1 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,584: Line 1,770:  
|-
 
|-
 
| 0-3
 
| 0-3
−
| Read access level
+
| FALCON_HWCFG1_CORE_REV
 +
|-
 +
| 4-5
 +
| FALCON_HWCFG1_SECURITY_MODEL
 
|-
 
|-
−
| 4-7
+
| 6-7
−
| Write access level
+
| FALCON_HWCFG1_CORE_REV_SUBVERSION
 +
|-
 +
| 8-11
 +
| FALCON_HWCFG1_IMEM_PORTS
 +
|-
 +
| 12-15
 +
| FALCON_HWCFG1_DMEM_PORTS
 +
|-
 +
| 16-20
 +
| FALCON_HWCFG1_TAG_WIDTH
 +
|-
 +
| 27
 +
| FALCON_HWCFG1_DBG_PRIV_BUS
 +
|-
 +
| 28
 +
| FALCON_HWCFG1_CSB_SIZE_16M
 +
|-
 +
| 29
 +
| FALCON_HWCFG1_PRIV_DIRECT
 +
|-
 +
| 30
 +
| FALCON_HWCFG1_DMEM_APERTURES
 +
|-
 +
| 31
 +
| FALCON_HWCFG1_IMEM_AUTOFILL
 
|}
 
|}
   −
Controls accesses to the following registers:
+
=== FALCON_IMCTL ===
−
* FALCON_VM_SUPERVISOR
  −
* FALCON_SUBENGINE_RESET
  −
* FALCON_HOST_IO_INDEX
  −
* [[#FALCON_DMACTL|FALCON_DMACTL]]
  −
* FALCON_TLB_CMD
  −
* FALCON_TLB_CMD_RES
  −
* FALCON_UNK_250
  −
* FALCON_UNK_2E0
  −
 
  −
=== FALCON_SPROT_IRQ ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 0-23
−
| Read access level
+
| FALCON_IMCTL_ADDR_BLK
 
|-
 
|-
−
| 4-7
+
| 24-26
−
| Write access level
+
| FALCON_IMCTL_CMD
 +
0x00: NOP
 +
0x01: IMINV (ITLB)
 +
0x02: IMBLK (PTLB)
 +
0x03: IMTAG (VTLB)
 +
0x04: IMTAG_SETVLD
 
|}
 
|}
   −
Controls accesses to the following registers:
+
Controls the Falcon TLB.
−
* [[#FALCON_IRQMODE|FALCON_IRQMODE]]
  −
* [[#FALCON_IRQMSET|FALCON_IRQMSET]]
  −
* [[#FALCON_IRQMCLR|FALCON_IRQMCLR]]
  −
* [[#FALCON_IRQDEST|FALCON_IRQDEST]]
  −
* FALCON_GPTMR_PERIOD
  −
* FALCON_GPTMR_TIME
  −
* FALCON_GPTMR_ENABLE
  −
* FALCON_UNK_3C
  −
* FALCON_UNK_E0
     −
=== FALCON_SPROT_MTHD ===
+
=== FALCON_IMSTAT ===
 +
Returns the result of the last command from [[#FALCON_IMCTL|FALCON_IMCTL]].
 +
 
 +
=== FALCON_TRACEIDX ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 0-7
−
| Read access level
+
| FALCON_TRACEIDX_IDX
 +
|-
 +
| 16-23
 +
| FALCON_TRACEIDX_MAXIDX
 
|-
 
|-
−
| 4-7
+
| 24-31
−
| Write access level
+
| FALCON_TRACEIDX_CNT
 
|}
 
|}
   −
Controls accesses to the following registers:
+
Controls the index for tracing with [[#FALCON_TRACEPC|FALCON_TRACEPC]].
−
* [[#FALCON_ITFEN|FALCON_ITFEN]]
+
 
−
* FALCON_CURCTX
+
=== FALCON_TRACEPC ===
−
* FALCON_NXTCTX
+
Returns the PC of the last call or branch executed.
−
* FALCON_CMDCTX
  −
* FALCON_MTHD_DATA
  −
* FALCON_MTHD_CMD
  −
* FALCON_MTHD_DATA_WR
  −
* FALCON_MTHD_OCCUPIED
  −
* FALCON_MTHD_ACK
  −
* FALCON_MTHD_LIMIT
  −
* FALCON_DEBUG1
     −
=== FALCON_SPROT_SCTL ===
+
=== FALCON_IMEMC0 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 2-7
−
| Read access level
+
| FALCON_IMEMC_OFFS
 +
|-
 +
| 8-15
 +
| FALCON_IMEMC_BLK
 +
|-
 +
| 24
 +
| FALCON_IMEMC_AINCW
 
|-
 
|-
−
| 4-7
+
| 25
−
| Write access level
+
| FALCON_IMEMC_AINCR
−
|}
+
|-
−
 
+
| 28
−
Controls accesses to the [[#FALCON_SCTL|FALCON_SCTL]] register.
+
| FALCON_IMEMC_SECURE
−
 
+
|-
−
=== FALCON_SPROT_WDTMR ===
+
| 29
−
{| class="wikitable" border="1"
+
| FALCON_IMEMC_SEC_ATOMIC
−
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0-3
+
| 30
−
| Read access level
+
| FALCON_IMEMC_SEC_WR_VIO
 
|-
 
|-
−
| 4-7
+
| 31
−
| Write access level
+
| FALCON_IMEMC_SEC_LOCK
 
|}
 
|}
   −
Controls accesses to the following registers:
+
Used for configuring access to Falcon's IMEM.
−
* FALCON_WDTMR_TIME
+
 
−
* FALCON_WDTMR_ENABLE
+
=== FALCON_IMEMD0 ===
 +
Returns or takes the value for an IMEM read/write operation.
 +
 
 +
=== FALCON_IMEMT0 ===
 +
Returns or takes the virtual page index for an IMEM read/write operation.
   −
=== TSEC_SCP_CTL0 ===
+
=== FALCON_DMEMC0 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 20
+
| 2-7
−
| Enable TSEC_SCP_INSN_STAT register
+
| FALCON_DMEMC_OFFS
 +
|-
 +
| 8-15
 +
| FALCON_DMEMC_BLK
 +
|-
 +
| 24
 +
| FALCON_DMEMC_AINCW
 +
|-
 +
| 25
 +
| FALCON_DMEMC_AINCR
 
|}
 
|}
   −
=== TSEC_SCP_CTL1 ===
+
Used for configuring access to Falcon's DMEM.
 +
 
 +
=== FALCON_DMEMD0 ===
 +
Returns or takes the value for a DMEM read/write operation.
 +
 
 +
=== FALCON_ICD_CMD ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 11
+
| 0-3
−
| Enable TRNG testing mode
+
| FALCON_ICD_CMD_OPC
 +
0x00: STOP
 +
0x01: RUN (run from PC)
 +
0x02: JRUN (run from address)
 +
0x03: RUNB (run from PC)
 +
0x04: JRUNB (run from address)
 +
0x05: STEP (step from PC)
 +
0x06: JSTEP (step from address)
 +
0x07: EMASK (set exception mask)
 +
0x08: RREG (read register)
 +
0x09: WREG (write register)
 +
0x0A: RDM (read data memory)
 +
0x0B: WDM (write data memory)
 +
0x0C: RCM (read MMIO/configuration memory)
 +
0x0D: WCM (write MMIO/configuration memory)
 +
0x0E: RSTAT (read status)
 +
0x0F: SBU
 +
|-
 +
| 6-7
 +
| FALCON_ICD_CMD_SZ
 +
0x00: B (byte
 +
0x01: HW (half word)
 +
0x02: W (word)
 +
|-
 +
| 8-12
 +
| FALCON_ICD_CMD_IDX
 +
0x00: REG0 | RSTAT0 | WB0
 +
0x01: REG1 | RSTAT1 | WB1
 +
0x02: REG2 | RSTAT2 | WB2
 +
0x03: REG3 | RSTAT3 | WB3
 +
0x04: REG4 | RSTAT4
 +
0x05: REG5 | RSTAT5
 +
0x06: REG6
 +
0x07: REG7
 +
0x08: REG8
 +
0x09: REG9
 +
0x0A: REG10
 +
0x0B: REG11
 +
0x0C: REG12
 +
0x0D: REG13
 +
0x0E: REG14
 +
0x0F: REG15
 +
0x10: IV0
 +
0x11: IV1
 +
0x12: UNDEFINED
 +
0x13: EV
 +
0x14: SP
 +
0x15: PC
 +
0x16: IMB
 +
0x17: DMB
 +
0x18: CSW
 +
0x19: CCR
 +
0x1A: SEC
 +
0x1B: CTX
 +
0x1C: EXCI
 +
0x1D: SEC1
 +
0x1E: IMB1
 +
0x1F: DMB1
 +
|-
 +
| 14
 +
| FALCON_ICD_CMD_ERROR
 +
|-
 +
| 15
 +
| FALCON_ICD_CMD_RDVLD
 
|-
 
|-
−
| 12
+
| 16-31
−
| Enable the TRNG
+
| FALCON_ICD_CMD_PARM
 +
0x0001: EMASK_TRAP0
 +
0x0002: EMASK_TRAP1
 +
0x0004: EMASK_TRAP2
 +
0x0008: EMASK_TRAP3
 +
0x0010: EMASK_EXC_UNIMP
 +
0x0020: EMASK_EXC_IMISS
 +
0x0040: EMASK_EXC_IMHIT
 +
0x0080: EMASK_EXC_IBREAK
 +
0x0100: EMASK_IV0
 +
0x0200: EMASK_IV1
 +
0x0400: EMASK_IV2
 +
0x0800: EMASK_EXT0
 +
0x1000: EMASK_EXT1
 +
0x2000: EMASK_EXT2
 +
0x4000: EMASK_EXT3
 +
0x8000: EMASK_EXT4
 
|}
 
|}
   −
=== TSEC_SCP_CTL_STAT ===
+
Used for sending commands to the Falcon's in-chip debugger.
−
{| class="wikitable" border="1"
+
 
−
!  Bits
+
=== FALCON_ICD_ADDR ===
−
!  Description
+
Takes the target address for the Falcon's in-chip debugger.
−
|-
+
 
−
| 20
+
=== FALCON_ICD_WDATA ===
−
| TSEC_SCP_CTL_STAT_DEBUG_MODE
+
Takes the data for writing using the Falcon's in-chip debugger.
−
|}
+
 
 +
=== FALCON_ICD_RDATA ===
 +
Returns the data read using the Falcon's in-chip debugger.
   −
=== TSEC_SCP_CTL_LOCK ===
+
When reading from an internal status register (STAT), the following applies:
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,714: Line 2,014:  
|-
 
|-
 
| 0
 
| 0
−
| Disable reads for the TRNG register block
+
| RSTAT0_MEM_STALL
 
|-
 
|-
 
| 1
 
| 1
−
| Disable reads for the TFBIF register block
+
| RSTAT0_DMA_STALL
 
|-
 
|-
 
| 2
 
| 2
−
| Disable reads for the DMA register block
+
| RSTAT0_FENCE_STALL
 
|-
 
|-
 
| 3
 
| 3
−
| Disable reads for the TEGRA register block
+
| RSTAT0_DIV_STALL
 
|-
 
|-
 
| 4
 
| 4
−
| Disable writes for the TRNG register block
+
| RSTAT0_DMA_STALL_DMAQ
 
|-
 
|-
 
| 5
 
| 5
−
| Disable writes for the TFBIF register block
+
| RSTAT0_DMA_STALL_DMWAITING
 
|-
 
|-
 
| 6
 
| 6
−
| Disable writes for the DMA register block
+
| RSTAT0_DMA_STALL_IMWAITING
 
|-
 
|-
 
| 7
 
| 7
−
| Disable writes for the TEGRA register block
+
| RSTAT0_ANY_STALL
−
|}
+
|-
−
 
+
| 8
−
Locks accesses to the other sub-engines and can only be cleared in Heavy Secure mode.
+
| RSTAT0_SBFULL_STALL
−
 
+
|-
−
=== TSEC_SCP_CTL_PKEY ===
+
| 9
−
{| class="wikitable" border="1"
+
| RSTAT0_SBHIT_STALL
−
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0
+
| 10
−
| TSEC_SCP_CTL_PKEY_REQUEST_RELOAD
+
| RSTAT0_FLOW_STALL
 
|-
 
|-
−
| 1
+
| 11
−
| TSEC_SCP_CTL_PKEY_LOADED
+
| RSTAT0_SP_STALL
−
|}
  −
 
  −
=== TSEC_SCP_SEQ_CTL ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0-3
+
| 12
−
| Sequence's instruction index
+
| RSTAT0_BL_STALL
 
|-
 
|-
−
| 4-7
+
| 13
−
| Target and control flags
+
| RSTAT0_IPND_STALL
 
|-
 
|-
−
| 8-11
+
| 14
−
| Sequence's size
+
| RSTAT0_LDSTQ_STALL
−
|}
+
|-
−
 
+
| 16
−
Controls the last crypto sequence (cs0 or cs1) created.
+
| RSTAT0_NOINSTR_STALL
−
 
+
|-
−
=== TSEC_SCP_SEQ_VAL ===
+
| 20
−
{| class="wikitable" border="1"
+
| RSTAT0_HALTSTOP_FLUSH
−
!  Bits
+
|-
−
!  Description
+
| 21
 +
| RSTAT0_AFILL_FLUSH
 +
|-
 +
| 22
 +
| RSTAT0_EXC_FLUSH
 +
|-
 +
| 23-25
 +
| RSTAT0_IRQ_FLUSH
 +
|-
 +
| 28
 +
| RSTAT0_VALIDRD
 
|-
 
|-
−
| 0-3
+
| 29
−
| Sequence instruction's first operand
+
| RSTAT0_WAITING
 
|-
 
|-
−
| 4-9
+
| 30
−
| Sequence instruction's second operand
+
| RSTAT0_HALTED
 
|-
 
|-
−
| 10-14
+
| 31
−
| Sequence instruction's opcode
+
| RSTAT0_MTHD_FULL
 
|}
 
|}
−
  −
Contains information on the last crypto sequence (cs0 or cs1) created.
  −
  −
=== TSEC_SCP_SEQ_STAT ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-3
−
| Set if crypto sequence recording (cs0begin/cs1begin) is active
+
| RSTAT1_WB_ALLOC
 
|-
 
|-
 
| 4-7
 
| 4-7
−
| Number of instructions left for the crypto sequence
+
| RSTAT1_WB_VALID
 +
|-
 +
| 8-9
 +
| RSTAT1_WB0_SZ
 +
|-
 +
| 10-11
 +
| RSTAT1_WB1_SZ
 +
|-
 +
| 12-13
 +
| RSTAT1_WB2_SZ
 +
|-
 +
| 14-15
 +
| RSTAT1_WB3_SZ
 +
|-
 +
| 16-19
 +
| RSTAT1_WB0_IDX
 +
|-
 +
| 20-23
 +
| RSTAT1_WB1_IDX
 +
|-
 +
| 24-27
 +
| RSTAT1_WB2_IDX
 
|-
 
|-
−
| 12-15
+
| 28-31
−
| Active crypto key register
+
| RSTAT1_WB3_IDX
 
|}
 
|}
−
  −
Contains information on the last crypto sequence (cs0 or cs1) executed.
  −
  −
=== TSEC_SCP_INSN_STAT ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,809: Line 2,124:  
|-
 
|-
 
| 0-3
 
| 0-3
−
| Destination register or immediate value
+
| RSTAT2_DMAQ_NUM
 +
|-
 +
| 4
 +
| RSTAT2_DMA_ENABLE
 +
|-
 +
| 5-7
 +
| RSTAT2_LDSTQ_NUM
 +
|-
 +
| 16-19
 +
| RSTAT2_EM_BUSY
 +
|-
 +
| 20-23
 +
| RSTAT2_EM_ACKED
 
|-
 
|-
−
| 8-13
+
| 24-27
−
| Source register or immediate value
+
| RSTAT2_EM_ISWR
 
|-
 
|-
−
| 20-24
+
| 28-31
−
| Operation
+
| RSTAT2_EM_DVLD
−
0x0:  nop (fuc5 opcode 0x00)
  −
0x1:  cmov (fuc5 opcode 0x84)
  −
0x2:  cxsin (fuc5 opcode 0x88) or xdst (with cxset)
  −
0x3:  cxsout (fuc5 opcode 0x8C) or xdld (with cxset)
  −
0x4:  crnd (fuc5 opcode 0x90)
  −
0x5:  cs0begin (fuc5 opcode 0x94)
  −
0x6:  cs0exec (fuc5 opcode 0x98)
  −
0x7:  cs1begin (fuc5 opcode 0x9C)
  −
0x8:  cs1exec (fuc5 opcode 0xA0)
  −
0x9:  invalid (fuc5 opcode 0xA4)
  −
0xA:  cchmod (fuc5 opcode 0xA8)
  −
0xB:  cxor (fuc5 opcode 0xAC)
  −
0xC:  cadd (fuc5 opcode 0xB0)
  −
0xD:  cand (fuc5 opcode 0xB4)
  −
0xE:  crev (fuc5 opcode 0xB8)
  −
0xF:  cprecmac (fuc5 opcode 0xBC)
  −
0x10: csecret (fuc5 opcode 0xC0)
  −
0x11: ckeyreg (fuc5 opcode 0xC4)
  −
0x12: ckexp (fuc5 opcode 0xC8)
  −
0x13: ckrexp (fuc5 opcode 0xCC)
  −
0x14: cenc (fuc5 opcode 0xD0)
  −
0x15: cdec (fuc5 opcode 0xD4)
  −
0x16: csigauth (fuc5 opcode 0xD8)
  −
0x17: csigenc (fuc5 opcode 0xDC)
  −
0x18: csigclr (fuc5 opcode 0xE0)
  −
|-
  −
| 28
  −
| Unknown
  −
|-
  −
| 31
  −
| Set if running in secure mode (cauth)
   
|}
 
|}
−
  −
Contains information on the last crypto instruction executed.
  −
  −
=== TSEC_SCP_AUTH_STAT ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-1
+
| 0
−
| Signature comparison result (3=succeeded, 2=failed)
+
| RSTAT3_MTHD_IDLE
−
|}
  −
 
  −
Contains information on the last authentication attempt.
  −
 
  −
=== TSEC_SCP_AES_STAT ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0-4
+
| 1
−
| First opcode
+
| RSTAT3_CTXSW_IDLE
 
|-
 
|-
−
| 5-9
+
| 2
−
| Second opcode
+
| RSTAT3_DMA_IDLE
 
|-
 
|-
−
| 15-16
+
| 3
−
| AES operation
+
| RSTAT3_SCP_IDLE
−
0: Encryption
  −
1: Decryption
  −
2: Key expansion
  −
3: Key reverse expansion
  −
|}
  −
 
  −
Contains information on the last AES sequence executed.
  −
 
  −
=== TSEC_SCP_IRQSTAT ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 1
+
| 4
−
| TSEC_SCP_IRQSTAT_TRNG
+
| RSTAT3_LDST_IDLE
 
|-
 
|-
−
| 8
+
| 5
−
| TSEC_SCP_IRQSTAT_HALT
+
| RSTAT3_SBWB_EMPTY
 
|-
 
|-
−
| 12
+
| 6-8
−
| Unknown
+
| RSTAT3_CSWIE
 
|-
 
|-
−
| 16
+
| 10
−
| TSEC_SCP_IRQSTAT_INSN_ERROR
+
| RSTAT3_CSWE
 
|-
 
|-
−
| 20
+
| 12-14
−
| TSEC_SCP_IRQSTAT_SINGLE_STEP
+
| RSTAT3_CTXSW_STATE
 +
0x00: IDLE
 +
0x01: SM_CHECK
 +
0x02: SM_SAVE
 +
0x03: SM_SAVE_WAIT
 +
0x04: SM_BLK_BIND
 +
0x05: SM_RESET
 +
0x06: SM_RESETWAIT
 +
0x07: SM_ACK
 
|-
 
|-
−
| 24
+
| 15
−
| Unknown
+
| RSTAT3_CTXSW_PEND
 
|-
 
|-
−
| 28
+
| 17
−
| Unknown
+
| RSTAT3_DMA_FBREQ_IDLE
−
|}
  −
 
  −
Used for getting the status of crypto IRQs.
  −
 
  −
=== TSEC_SCP_IRQMASK ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 1
+
| 18
−
| TSEC_SCP_IRQMASK_TRNG
+
| RSTAT3_DMA_ACKQ_EMPTY
 
|-
 
|-
−
| 8
+
| 19
−
| TSEC_SCP_IRQMASK_HALT
+
| RSTAT3_DMA_RDQ_EMPTY
 
|-
 
|-
−
| 12
+
| 20
−
| Unknown
+
| RSTAT3_DMA_WR_BUSY
 +
|-
 +
| 21
 +
| RSTAT3_DMA_RD_BUSY
 
|-
 
|-
−
| 16
+
| 22
−
| TSEC_SCP_IRQMASK_INSN_ERROR
+
| RSTAT3_LDST_XT_BUSY
 
|-
 
|-
−
| 20
+
| 23
−
| TSEC_SCP_IRQMASK_SINGLE_STEP
+
| RSTAT3_LDST_XT_BLOCK
 
|-
 
|-
 
| 24
 
| 24
−
| Unknown
+
| RSTAT3_ENG_IDLE
−
|-
  −
| 28
  −
| Unknown
   
|}
 
|}
−
  −
Used for getting the value of the mask for crypto IRQs.
  −
  −
=== TSEC_SCP_RES ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 31
+
| 0-1
−
| SCP is halted
+
| RSTAT4_ICD_STATE
−
|}
+
0x00: NORMAL
−
 
+
0x01: WAIT_ISSUE_CLEAR
−
Contains information on the status generated by the [[#TSEC_SCP_IRQSTAT|TSEC_SCP_IRQSTAT_HALT]] IRQ.
+
  0x02: WAIT_EXLDQ_CLEAR
−
 
+
  0x03: FULL_DBG_MODE
−
=== TSEC_SCP_ERR ===
  −
{| class="wikitable" border="1"
  −
! Bits
  −
! Description
   
|-
 
|-
−
| 0
+
| 2-3
−
| Invalid instruction
+
| RSTAT4_ICD_MODE
 +
0x00: SUPPRESSICD
 +
0x01: ENTERICD_IBRK
 +
0x02: ENTERICD_STEP
 
|-
 
|-
−
| 4
+
| 16
−
| Empty crypto sequence
+
| RSTAT4_ICD_EMASK_TRAP0
 
|-
 
|-
−
| 8
+
| 17
−
| Crypto sequence is too long
+
| RSTAT4_ICD_EMASK_TRAP1
 
|-
 
|-
−
| 12
+
| 18
−
| Crypto sequence was not finished
+
| RSTAT4_ICD_EMASK_TRAP2
 
|-
 
|-
−
| 16
+
| 19
−
| Invalid cauth signature (during csigenc, csigclr or csigauth)
+
| RSTAT4_ICD_EMASK_TRAP3
 
|-
 
|-
 
| 20
 
| 20
−
| Wrong access level (during csigauth)
+
| RSTAT4_ICD_EMASK_EXC_UNIMP
 +
|-
 +
| 21
 +
| RSTAT4_ICD_EMASK_EXC_IMISS
 +
|-
 +
| 22
 +
| RSTAT4_ICD_EMASK_EXC_IMHIT
 +
|-
 +
| 23
 +
| RSTAT4_ICD_EMASK_EXC_IBREAK
 
|-
 
|-
 
| 24
 
| 24
−
| Forbidden instruction
+
| RSTAT4_ICD_EMASK_IV0
 +
|-
 +
| 25
 +
| RSTAT4_ICD_EMASK_IV1
 +
|-
 +
| 26
 +
| RSTAT4_ICD_EMASK_IV2
 +
|-
 +
| 27
 +
| RSTAT4_ICD_EMASK_EXT0
 +
|-
 +
| 28
 +
| RSTAT4_ICD_EMASK_EXT1
 +
|-
 +
| 29
 +
| RSTAT4_ICD_EMASK_EXT2
 +
|-
 +
| 30
 +
| RSTAT4_ICD_EMASK_EXT3
 +
|-
 +
| 31
 +
| RSTAT4_ICD_EMASK_EXT4
 
|}
 
|}
−
  −
Contains information on crypto errors generated by the [[#TSEC_SCP_IRQSTAT|TSEC_SCP_IRQSTAT_INSN_ERROR]] IRQ.
  −
  −
=== TSEC_TFBIF_MCCIF_FIFOCTRL ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-7
−
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVERRIDE
+
| RSTAT5_LRU_STATE
−
|-
  −
| 1
  −
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVERRIDE
  −
|-
  −
| 2
  −
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRCL_MCLE2X
  −
|-
  −
| 3
  −
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDMC_RDFAST
  −
|-
  −
| 4
  −
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRMC_CLLE2X
  −
|-
  −
| 5
  −
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDCL_RDFAST
  −
|-
  −
| 6
  −
| TSEC_TFBIF_MCCIF_FIFOCTRL_CCLK_OVERRIDE
  −
|-
  −
| 7
  −
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVR_MODE
  −
|-
  −
| 8
  −
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVR_MODE
   
|}
 
|}
   −
=== TSEC_TFBIF_MCCIF_FIFOCTRL1 ===
+
=== FALCON_SCTL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-15
+
| 0-1
−
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SRD2MC_REORDER_DEPTH_LIMIT
+
| FALCON_SCTL_SEC_MODE
 +
0: Non-secure
 +
1: Light Secure
 +
2: Heavy Secure
 
|-
 
|-
−
| 16-31
+
| 4-5
−
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SWR2MC_REORDER_DEPTH_LIMIT
+
| FALCON_SCTL_OLD_SEC_MODE
 +
0: Non-secure
 +
1: Light Secure
 +
2: Heavy Secure
 +
|-
 +
| 12-13
 +
| Unknown
 +
|-
 +
| 14
 +
| Initialize the transition to LS mode
 
|}
 
|}
   −
=== TSEC_TFBIF_UNK_44 ===
+
=== FALCON_SSTAT ===
−
Used to control accesses to DRAM.
+
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 31
 +
| Set on memory protection violation
 +
|}
   −
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
+
=== FALCON_SPROT_IMEM ===
−
 
  −
=== TSEC_TFBIF_UNK_48 ===
  −
Used to control accesses to DRAM.
  −
 
  −
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
  −
 
  −
=== TSEC_DMA_CMD ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-3
−
| TSEC_DMA_CMD_READ
+
| Read access level
−
|-
  −
| 1
  −
| TSEC_DMA_CMD_WRITE
   
|-
 
|-
 
| 4-7
 
| 4-7
−
| TSEC_DMA_CMD_UNK
+
| Write access level
 +
|}
 +
 
 +
Controls accesses to Falcon IMEM.
 +
 
 +
=== FALCON_SPROT_DMEM ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to Falcon DMEM.
 +
 
 +
=== FALCON_SPROT_CPUCTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| 12
+
| 0-3
−
| TSEC_DMA_CMD_BUSY
+
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to the [[#FALCON_CPUCTL|FALCON_CPUCTL]] register.
 +
 
 +
=== FALCON_SPROT_MISC ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to the following registers:
 +
* FALCON_PRIVSTATE
 +
* FALCON_SFTRESET
 +
* FALCON_ADDR
 +
* [[#FALCON_DMACTL|FALCON_DMACTL]]
 +
* [[#FALCON_IMCTL|FALCON_IMCTL]]
 +
* [[#FALCON_IMSTAT|FALCON_IMSTAT]]
 +
* FALCON_UNK_250
 +
* FALCON_DMAINFO_CTL
 +
 
 +
=== FALCON_SPROT_IRQ ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to the following registers:
 +
* [[#FALCON_IRQMODE|FALCON_IRQMODE]]
 +
* [[#FALCON_IRQMSET|FALCON_IRQMSET]]
 +
* [[#FALCON_IRQMCLR|FALCON_IRQMCLR]]
 +
* [[#FALCON_IRQDEST|FALCON_IRQDEST]]
 +
* FALCON_GPTMRINT
 +
* FALCON_GPTMRVAL
 +
* FALCON_GPTMRCTL
 +
* FALCON_IRQDEST2
 +
* FALCON_UNK_E0
 +
 
 +
=== FALCON_SPROT_MTHD ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to the following registers:
 +
* [[#FALCON_ITFEN|FALCON_ITFEN]]
 +
* FALCON_CURCTX
 +
* FALCON_NXTCTX
 +
* FALCON_CTXACK
 +
* FALCON_MTHDDATA
 +
* FALCON_MTHDID
 +
* FALCON_MTHDWDAT
 +
* FALCON_MTHDCOUNT
 +
* FALCON_MTHDPOP
 +
* FALCON_MTHDRAMSZ
 +
* [[#FALCON_DEBUG1|FALCON_DEBUG1]]
 +
 
 +
=== FALCON_SPROT_SCTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to the [[#FALCON_SCTL|FALCON_SCTL]] register.
 +
 
 +
=== FALCON_SPROT_WDTMR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to the following registers:
 +
* FALCON_WDTMRVAL
 +
* FALCON_WDTMRCTL
 +
 
 +
=== TSEC_SCP_CTL0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 20
 +
| Enable TSEC_SCP_INSN_STAT register
 +
|}
 +
 
 +
=== TSEC_SCP_CTL1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 11
 +
| Enable TRNG testing mode
 +
|-
 +
| 12
 +
| Enable the TRNG
 +
|}
 +
 
 +
=== TSEC_SCP_CTL_STAT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 20
 +
| TSEC_SCP_CTL_STAT_DEBUG_MODE
 +
|}
 +
 
 +
=== TSEC_SCP_CTL_LOCK ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Disable reads for the SCP and TRNG register blocks
 +
|-
 +
| 1
 +
| Disable reads for the TFBIF register block
 +
|-
 +
| 2
 +
| Disable reads for the DMA register block
 +
|-
 +
| 3
 +
| Disable reads for the TEGRA register block
 +
|-
 +
| 4
 +
| Disable writes for the SCP and TRNG register blocks
 +
|-
 +
| 5
 +
| Disable writes for the TFBIF register block
 +
|-
 +
| 6
 +
| Disable writes for the DMA register block
 +
|-
 +
| 7
 +
| Disable writes for the TEGRA register block
 +
|}
 +
 
 +
Locks accesses to sub-engines and can only be cleared in Heavy Secure mode.
 +
 
 +
=== TSEC_SCP_CTL_PKEY ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_SCP_CTL_PKEY_REQUEST_RELOAD
 +
|-
 +
| 1
 +
| TSEC_SCP_CTL_PKEY_LOADED
 +
|}
 +
 
 +
=== TSEC_SCP_SEQ_CTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Sequence's instruction index
 +
|-
 +
| 4-7
 +
| Target and control flags
 +
|-
 +
| 8-11
 +
| Sequence's size
 +
|}
 +
 
 +
Controls the last crypto sequence (cs0 or cs1) created.
 +
 
 +
=== TSEC_SCP_SEQ_VAL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Sequence instruction's first operand
 +
|-
 +
| 4-9
 +
| Sequence instruction's second operand
 +
|-
 +
| 10-14
 +
| Sequence instruction's opcode
 +
|}
 +
 
 +
Contains information on the last crypto sequence (cs0 or cs1) created.
 +
 
 +
=== TSEC_SCP_SEQ_STAT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Set if crypto sequence recording (cs0begin/cs1begin) is active
 +
|-
 +
| 4-7
 +
| Number of instructions left for the crypto sequence
 +
|-
 +
| 12-15
 +
| Active crypto key register
 +
|}
 +
 
 +
Contains information on the last crypto sequence (cs0 or cs1) executed.
 +
 
 +
=== TSEC_SCP_INSN_STAT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Destination register or immediate value
 +
|-
 +
| 8-13
 +
| Source register or immediate value
 +
|-
 +
| 20-24
 +
| Operation
 +
0x0:  nop (fuc5 opcode 0x00)
 +
0x1:  cmov (fuc5 opcode 0x84)
 +
0x2:  cxsin (fuc5 opcode 0x88) or xdst (with cxset)
 +
0x3:  cxsout (fuc5 opcode 0x8C) or xdld (with cxset)
 +
0x4:  crnd (fuc5 opcode 0x90)
 +
0x5:  cs0begin (fuc5 opcode 0x94)
 +
0x6:  cs0exec (fuc5 opcode 0x98)
 +
0x7:  cs1begin (fuc5 opcode 0x9C)
 +
0x8:  cs1exec (fuc5 opcode 0xA0)
 +
0x9:  invalid (fuc5 opcode 0xA4)
 +
0xA:  cchmod (fuc5 opcode 0xA8)
 +
0xB:  cxor (fuc5 opcode 0xAC)
 +
0xC:  cadd (fuc5 opcode 0xB0)
 +
0xD:  cand (fuc5 opcode 0xB4)
 +
0xE:  crev (fuc5 opcode 0xB8)
 +
0xF:  cprecmac (fuc5 opcode 0xBC)
 +
0x10: csecret (fuc5 opcode 0xC0)
 +
0x11: ckeyreg (fuc5 opcode 0xC4)
 +
0x12: ckexp (fuc5 opcode 0xC8)
 +
0x13: ckrexp (fuc5 opcode 0xCC)
 +
0x14: cenc (fuc5 opcode 0xD0)
 +
0x15: cdec (fuc5 opcode 0xD4)
 +
0x16: csigauth (fuc5 opcode 0xD8)
 +
0x17: csigenc (fuc5 opcode 0xDC)
 +
0x18: csigclr (fuc5 opcode 0xE0)
 +
|-
 +
| 28
 +
| Set if the instruction is valid
 +
|-
 +
| 31
 +
| Set if running in HS mode
 +
|}
 +
 
 +
Contains information on the last crypto instruction executed.
 +
 
 +
=== TSEC_SCP_AUTH_STAT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-1
 +
| Signature comparison result (3=succeeded, 2=failed)
 +
|}
 +
 
 +
Contains information on the last authentication attempt.
 +
 
 +
=== TSEC_SCP_AES_STAT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-4
 +
| First opcode
 +
|-
 +
| 5-9
 +
| Second opcode
 +
|-
 +
| 15-16
 +
| AES operation
 +
0: Encryption
 +
1: Decryption
 +
2: Key expansion
 +
3: Key reverse expansion
 +
|}
 +
 
 +
Contains information on the last AES sequence executed.
 +
 
 +
=== TSEC_SCP_IRQSTAT ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_SCP_IRQSTAT_TRNG
 +
|-
 +
| 8
 +
| TSEC_SCP_IRQSTAT_ACL_ERROR
 +
|-
 +
| 12
 +
| Unknown
 +
|-
 +
| 16
 +
| TSEC_SCP_IRQSTAT_INSN_ERROR
 +
|-
 +
| 20
 +
| TSEC_SCP_IRQSTAT_SINGLE_STEP
 +
|-
 +
| 24
 +
| Unknown
 +
|-
 +
| 28
 +
| Unknown
 +
|}
 +
 
 +
Used for getting the status of crypto IRQs.
 +
 
 +
=== TSEC_SCP_IRQMASK ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_SCP_IRQMASK_TRNG
 +
|-
 +
| 8
 +
| TSEC_SCP_IRQMASK_ACL_ERROR
 +
|-
 +
| 12
 +
| Unknown
 +
|-
 +
| 16
 +
| TSEC_SCP_IRQMASK_INSN_ERROR
 +
|-
 +
| 20
 +
| TSEC_SCP_IRQMASK_SINGLE_STEP
 +
|-
 +
| 24
 +
| Unknown
 +
|-
 +
| 28
 +
| Unknown
 +
|}
 +
 
 +
Used for getting the value of the mask for crypto IRQs.
 +
 
 +
=== TSEC_SCP_ACL_ERR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Set when writing to a crypto register without the correct ACL
 +
|-
 +
| 4
 +
| Set when reading from a crypto register without the correct ACL
 +
|-
 +
| 8
 +
| Set on an invalid ACL change (cchmod)
 +
|-
 +
| 31
 +
| An ACL error occurred
 +
|}
 +
 
 +
Contains information on the status generated by the [[#TSEC_SCP_IRQSTAT|TSEC_SCP_IRQSTAT_ACL_ERROR]] IRQ.
 +
 
 +
=== TSEC_SCP_INSN_ERR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Invalid instruction
 +
|-
 +
| 4
 +
| Empty crypto sequence
 +
|-
 +
| 8
 +
| Crypto sequence is too long
 +
|-
 +
| 12
 +
| Crypto sequence was not finished
 +
|-
 +
| 16
 +
| Insecure signature (csigenc, csigclr or csigauth)
 +
|-
 +
| 20
 +
| Invalid signature (csigauth in HS mode)
 +
|-
 +
| 24
 +
| Forbidden ACL change (cchmod in NS mode)
 +
|}
 +
 
 +
Contains information on crypto errors generated by the [[#TSEC_SCP_IRQSTAT|TSEC_SCP_IRQSTAT_INSN_ERROR]] IRQ.
 +
 
 +
=== TSEC_TFBIF_CTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_CTL_CLR_BWCOUNT
 +
|-
 +
| 1
 +
| TSEC_TFBIF_CTL_ENABLE
 +
|-
 +
| 2
 +
| TSEC_TFBIF_CTL_CLR_IDLEWDERR
 +
|-
 +
| 3
 +
| TSEC_TFBIF_CTL_RESET
 +
|-
 +
| 4
 +
| TSEC_TFBIF_CTL_IDLE
 +
|-
 +
| 5
 +
| TSEC_TFBIF_CTL_IDLEWDERR
 +
|-
 +
| 6
 +
| TSEC_TFBIF_CTL_SRTOUT
 +
|-
 +
| 7
 +
| TSEC_TFBIF_CTL_CLR_SRTOUT
 +
|-
 +
| 8-11
 +
| TSEC_TFBIF_CTL_SRTOVAL
 +
|-
 +
| 12
 +
| TSEC_TFBIF_CTL_VPR
 +
|}
 +
 
 +
=== TSEC_TFBIF_MCCIF_FIFOCTRL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVERRIDE
 +
|-
 +
| 1
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVERRIDE
 +
|-
 +
| 2
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRCL_MCLE2X
 +
|-
 +
| 3
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDMC_RDFAST
 +
|-
 +
| 4
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRMC_CLLE2X
 +
|-
 +
| 5
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDCL_RDFAST
 +
|-
 +
| 6
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_CCLK_OVERRIDE
 +
|-
 +
| 7
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVR_MODE
 +
|-
 +
| 8
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVR_MODE
 +
|}
 +
 
 +
=== TSEC_TFBIF_MCCIF_FIFOCTRL1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-15
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SRD2MC_REORDER_DEPTH_LIMIT
 +
|-
 +
| 16-31
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SWR2MC_REORDER_DEPTH_LIMIT
 +
|}
 +
 
 +
=== TSEC_TFBIF_THROTTLE ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-11
 +
| TSEC_TFBIF_THROTTLE_BUCKET_SIZE
 +
|-
 +
| 16-27
 +
| TSEC_TFBIF_THROTTLE_LEAK_COUNT
 +
|-
 +
| 30-31
 +
| TSEC_TFBIF_THROTTLE_LEAK_SIZE
 +
|}
 +
 
 +
=== TSEC_TFBIF_DBG_STAT0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_DBG_STAT0_1K_TRANSFER
 +
|-
 +
| 1
 +
| TSEC_TFBIF_DBG_STAT0_RREQ_ISSUED
 +
|-
 +
| 2
 +
| TSEC_TFBIF_DBG_STAT0_WREQ_ISSUED
 +
|-
 +
| 3
 +
| TSEC_TFBIF_DBG_STAT0_TAGQ_ISSUED
 +
|-
 +
| 4
 +
| TSEC_TFBIF_DBG_STAT0_STALL_RDATQ
 +
|-
 +
| 5
 +
| TSEC_TFBIF_DBG_STAT0_STALL_RACKQ
 +
|-
 +
| 6
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WREQQ
 +
|-
 +
| 7
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WDATQ
 +
|-
 +
| 8
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WACKQ
 +
|-
 +
| 9
 +
| TSEC_TFBIF_DBG_STAT0_STALL_RREQ_PENDING
 +
|-
 +
| 10
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WREQ_PENDING
 +
|-
 +
| 11
 +
| TSEC_TFBIF_DBG_STAT0_STALL_MREQ
 +
|-
 +
| 12
 +
| TSEC_TFBIF_DBG_STAT0_ENGINE_IDLE
 
|-
 
|-
 
| 13
 
| 13
−
| TSEC_DMA_CMD_ERROR
+
| TSEC_TFBIF_DBG_STAT0_RMCCIF_IDLE
 +
|-
 +
| 14
 +
| TSEC_TFBIF_DBG_STAT0_WMCCIF_IDLE
 +
|-
 +
| 15
 +
| TSEC_TFBIF_DBG_STAT0_CSB_IDLE
 +
|-
 +
| 16
 +
| TSEC_TFBIF_DBG_STAT0_RU_IDLE
 +
|-
 +
| 17
 +
| TSEC_TFBIF_DBG_STAT0_WU_IDLE
 +
|-
 +
| 19
 +
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_ACTIVE
 +
|-
 +
| 20
 +
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_MCB
 +
|}
 +
 
 +
=== TSEC_TFBIF_SPROT_EMEM ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-3
 +
| Read access level
 +
|-
 +
| 4-7
 +
| Write access level
 +
|}
 +
 
 +
Controls accesses to external memory regions. Accessible in HS mode only.
 +
 
 +
=== TSEC_TFBIF_TRANSCFG ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_TRANSCFG_ATT0_SWID
 +
|-
 +
| 4
 +
| TSEC_TFBIF_TRANSCFG_ATT1_SWID
 +
|-
 +
| 8
 +
| TSEC_TFBIF_TRANSCFG_ATT2_SWID
 +
|-
 +
| 12
 +
| TSEC_TFBIF_TRANSCFG_ATT3_SWID
 +
|-
 +
| 16
 +
| TSEC_TFBIF_TRANSCFG_ATT4_SWID
 +
|-
 +
| 20
 +
| TSEC_TFBIF_TRANSCFG_ATT5_SWID
 +
|-
 +
| 24
 +
| TSEC_TFBIF_TRANSCFG_ATT6_SWID
 +
|-
 +
| 28
 +
| TSEC_TFBIF_TRANSCFG_ATT7_SWID
 +
|}
 +
 
 +
Configures the software ID per CTXDMA port for memory transactions. Software ID 0 (HW_SWID) forces all transactions to go through the SMMU while software ID 1 (PHY_SWID) bypasses it. Accessible in HS mode only.
 +
 
 +
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
 +
 
 +
=== TSEC_TFBIF_REGIONCFG ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-2
 +
| TSEC_TFBIF_REGIONCFG_T0_APERT_ID
 +
|-
 +
| 3
 +
| TSEC_TFBIF_REGIONCFG_T0_VPR
 +
|-
 +
| 4-6
 +
| TSEC_TFBIF_REGIONCFG_T1_APERT_ID
 +
|-
 +
| 7
 +
| TSEC_TFBIF_REGIONCFG_T1_VPR
 +
|-
 +
| 8-10
 +
| TSEC_TFBIF_REGIONCFG_T2_APERT_ID
 +
|-
 +
| 11
 +
| TSEC_TFBIF_REGIONCFG_T2_VPR
 +
|-
 +
| 12-14
 +
| TSEC_TFBIF_REGIONCFG_T3_APERT_ID
 +
|-
 +
| 15
 +
| TSEC_TFBIF_REGIONCFG_T3_VPR
 +
|-
 +
| 16-18
 +
| TSEC_TFBIF_REGIONCFG_T4_APERT_ID
 +
|-
 +
| 19
 +
| TSEC_TFBIF_REGIONCFG_T4_VPR
 +
|-
 +
| 20-22
 +
| TSEC_TFBIF_REGIONCFG_T5_APERT_ID
 +
|-
 +
| 23
 +
| TSEC_TFBIF_REGIONCFG_T5_VPR
 +
|-
 +
| 24-26
 +
| TSEC_TFBIF_REGIONCFG_T6_APERT_ID
 +
|-
 +
| 27
 +
| TSEC_TFBIF_REGIONCFG_T6_VPR
 +
|-
 +
| 28-30
 +
| TSEC_TFBIF_REGIONCFG_T7_APERT_ID
 +
|-
 +
| 31
 +
| TSEC_TFBIF_REGIONCFG_T7_VPR
 +
|}
 +
 
 +
Configures the aperture ID and VPR mode per CTXDMA port for memory region accessing. Accessible in HS mode only.
 +
 
 +
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
 +
 
 +
=== TSEC_TFBIF_ACTMON_ACTIVE_MASK ===
 +
Takes the memory access mask for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
 +
 
 +
=== TSEC_TFBIF_ACTMON_ACTIVE_BORPS ===
 +
Takes the billions of records per second count for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
 +
 
 +
=== TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT ===
 +
Controls the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
 +
 
 +
=== TSEC_CG ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-5
 +
| TSEC_CG_IDLE_CG_DLY_CNT
 +
|-
 +
| 6
 +
| TSEC_CG_IDLE_CG_EN
 +
|-
 +
| 16-18
 +
| TSEC_CG_WAKEUP_DLY_CNT
 +
|-
 +
| 19
 +
| TSEC_CG_WAKEUP_DLY_EN
 +
|}
 +
 
 +
=== TSEC_BAR0_CTL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_BAR0_CTL_READ
 +
|-
 +
| 1
 +
| TSEC_BAR0_CTL_WRITE
 +
|-
 +
| 4-7
 +
| TSEC_BAR0_CTL_BYTE_MASK
 +
|-
 +
| 12-13
 +
| TSEC_BAR0_CTL_STATUS
 +
0: Idle
 +
1: Busy
 +
2: Error
 +
3: Disabled
 
|-
 
|-
 
| 31
 
| 31
−
| TSEC_DMA_CMD_INIT
+
| TSEC_BAR0_CTL_INIT
 
|}
 
|}
   −
A DMA read/write operation requires bits TSEC_DMA_CMD_INIT and TSEC_DMA_CMD_READ/TSEC_DMA_CMD_WRITE to be set in TSEC_DMA_CMD.
+
A BAR0 DMA read/write operation requires bits TSEC_BAR0_CTL_INIT and TSEC_BAR0_CTL_READ/TSEC_BAR0_CTL_WRITE to be set in TSEC_BAR0_CTL.
   −
During the transfer, the TSEC_DMA_CMD_BUSY bit is set.
+
During the transfer, TSEC_BAR0_CTL_STATUS is set to "Busy".
   −
Accessing an invalid address causes bit TSEC_DMA_CMD_ERROR to be set.
+
Accessing an invalid address sets TSEC_BAR0_CTL_STATUS to "Error".
   −
=== TSEC_DMA_ADDR ===
+
=== TSEC_BAR0_ADDR ===
 
Takes the address for DMA transfers between TSEC and HOST1X (master and clients).
 
Takes the address for DMA transfers between TSEC and HOST1X (master and clients).
   −
=== TSEC_DMA_VAL ===
+
=== TSEC_BAR0_DATA ===
−
Takes the value for DMA transfers between TSEC and HOST1X (master and clients).
+
Takes the data for DMA transfers between TSEC and HOST1X (master and clients).
   −
=== TSEC_DMA_CFG ===
+
=== TSEC_BAR0_TIMEOUT ===
−
Always 0xFFF.
+
Takes the timeout value for DMA transfers between TSEC and HOST1X (master and clients).
    
=== TSEC_TEGRA_CTL ===
 
=== TSEC_TEGRA_CTL ===
Line 2,195: Line 3,225:     
Executing this instruction only succeeds if the TRNG is enabled for the SCP, which requires taking the following steps:
 
Executing this instruction only succeeds if the TRNG is enabled for the SCP, which requires taking the following steps:
−
* Write 0x7FFF to TSEC_TRNG_CLKDIV.
+
* Write 0x7FFF to TSEC_TRNG_CLK_LIMIT_LOW.
−
* Write 0x3FF0000 to TSEC_TRNG_UNK_00.
+
* Write 0x3FF0000 to TSEC_TRNG_CLK_LIMIT_HIGH.
−
* Write 0xFF00 to TSEC_TRNG_UNK_2C.
+
* Write 0xFF00 to TSEC_TRNG_CTL.
 
* Write 0x1000 to [[#TSEC_SCP_CTL1|TSEC_SCP_CTL1]].
 
* Write 0x1000 to [[#TSEC_SCP_CTL1|TSEC_SCP_CTL1]].
   Line 2,242: Line 3,272:  
| 17 || Region is encrypted
 
| 17 || Region is encrypted
 
|-
 
|-
−
| 18 || Unknown
+
| 18 || Unknown (set in HS mode)
 
|-
 
|-
−
| 19 || Unknown
+
| 19 || Block traps and interrupts (set in HS mode)
 
|-
 
|-
 
| 20-23 || Unknown
 
| 20-23 || Unknown
Line 2,280: Line 3,310:  
Falcon's Authenticated Mode has access to 64 128-bit keys which are burned at factory. These keys can be loaded by using the $csecret instruction which takes the target crypto register and the key index as arguments.
 
Falcon's Authenticated Mode has access to 64 128-bit keys which are burned at factory. These keys can be loaded by using the $csecret instruction which takes the target crypto register and the key index as arguments.
   −
All secrets appear to be common across Falcon units of the same version, with the exception of secret 0x3F. This secret is effectively empty (all zeros), but is configured to be overwritten with the KFUSE private key once the KFUSE clock is enabled. The KFUSE private key is console-unique.
+
Secrets are specific to each Falcon unit with the exception of secret 0x3F. This secret is effectively empty (all zeros), but is configured to be overwritten with the KFUSE private key once the KFUSE clock is enabled. The KFUSE private key is console-unique.
    
{| class=wikitable
 
{| class=wikitable
Retrieved from "https://switchbrew.org/wiki/Special:MobileDiff/6043...7496"