2,787
edits
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Line 8:
Line 8: − + − + Line 447:
Line 447: − + Line 459:
Line 459: − + Line 467:
Line 467: − + Line 479:
Line 479: − + Line 487:
Line 487: − + Line 499:
Line 499: − + Line 507:
Line 507: − + − + − + − + − + − + − + − + − + Line 1,373:
Line 1,373: + + + + + + + + + + + + Line 1,390:
Line 1,402: − + Line 1,402:
Line 1,414: − + Line 1,496:
Line 1,508: − + Line 1,525:
Line 1,537: − + Line 2,930:
Line 2,942: − + + + + + + +
( ͡° ͜ʖ ͡°)
Registers from 0x54501000 to 0x54502000 are a MMIO window for communicating with the Falcon microprocessor. From this range, the subset of registers from 0x54501400 to 0x54501FE8 are specific to the TSEC and are subdivided into:
Registers from 0x54501000 to 0x54502000 are a MMIO window for communicating with the Falcon microprocessor. From this range, the subset of registers from 0x54501400 to 0x54501FE8 are specific to the TSEC and are subdivided into:
* 0x54501400 to 0x54501500: SCP (secure crypto processor?).
* 0x54501400 to 0x54501500: SCP (Secure Crypto Processor?).
* 0x54501500 to 0x54501600: Unknown.
* 0x54501500 to 0x54501600: TRNG (True Random Number Generator).
* 0x54501600 to 0x54501700: TFBIF (Tegra Framebuffer Interface).
* 0x54501600 to 0x54501700: TFBIF (Tegra Framebuffer Interface).
* 0x54501700 to 0x54501800: DMA.
* 0x54501700 to 0x54501800: DMA.
| 0x04
| 0x04
|-
|-
| TSEC_SCP_UNK0
| [[#TSEC_SCP_CTL_TRNG|TSEC_SCP_CTL_TRNG]]
| 0x54501404
| 0x54501404
| 0x04
| 0x04
| 0x04
| 0x04
|-
|-
| TSEC_SCP_UNK1
| TSEC_SCP_UNK0
| 0x54501410
| 0x54501410
| 0x04
| 0x04
| 0x04
| 0x04
|-
|-
| TSEC_SCP_UNK2
| TSEC_SCP_UNK1
| 0x54501420
| 0x54501420
| 0x04
| 0x04
| 0x04
| 0x04
|-
|-
| TSEC_SCP_UNK3
| TSEC_SCP_UNK2
| 0x54501454
| 0x54501454
| 0x04
| 0x04
| 0x04
| 0x04
|-
|-
| TSEC_SCP_UNK4
| TSEC_SCP_UNK3
| 0x54501470
| 0x54501470
| 0x04
| 0x04
| 0x04
| 0x04
|-
|-
| TSEC_SCP_UNK5
| TSEC_SCP_UNK4
| 0x54501490
| 0x54501490
| 0x04
| 0x04
| 0x04
| 0x04
|-
|-
| TSEC_UNK0
| TSEC_TRNG_CLKDIV
| 0x54501500
| 0x54501500
| 0x04
| 0x04
|-
|-
| TSEC_UNK1
| TSEC_TRNG_UNK0
| 0x54501504
| 0x54501504
| 0x04
| 0x04
|-
|-
| TSEC_UNK2
| TSEC_TRNG_UNK1
| 0x5450150C
| 0x5450150C
| 0x04
| 0x04
|-
|-
| TSEC_UNK3
| TSEC_TRNG_UNK2
| 0x54501510
| 0x54501510
| 0x04
| 0x04
|-
|-
| TSEC_UNK4
| TSEC_TRNG_UNK3
| 0x54501514
| 0x54501514
| 0x04
| 0x04
|-
|-
| TSEC_UNK5
| TSEC_TRNG_UNK4
| 0x54501518
| 0x54501518
| 0x04
| 0x04
|-
|-
| TSEC_UNK6
| TSEC_TRNG_UNK5
| 0x5450151C
| 0x5450151C
| 0x04
| 0x04
|-
|-
| TSEC_UNK7
| TSEC_TRNG_UNK6
| 0x54501528
| 0x54501528
| 0x04
| 0x04
|-
|-
| TSEC_UNK8
| TSEC_TRNG_UNK7
| 0x5450152C
| 0x5450152C
| 0x04
| 0x04
| 20
| 20
| Enable TSEC_SCP_INSN_STAT register
| Enable TSEC_SCP_INSN_STAT register
|}
=== TSEC_SCP_CTL_TRNG ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 11
| Unknown
|-
| 12
| Enable the TRNG
|}
|}
|-
|-
| 0
| 0
| Disable reads for the UNK register block
| Disable reads for the TRNG register block
|-
|-
| 1
| 1
|-
|-
| 4
| 4
| Disable writes for the UNK register block
| Disable writes for the TRNG register block
|-
|-
| 5
| 5
|-
|-
| 1
| 1
| Unknown
| TSEC_SCP_IRQSTAT_TRNG
|-
|-
| 8
| 8
|-
|-
| 1
| 1
| Unknown
| TSEC_SCP_IRQMASK_TRNG
|-
|-
| 8
| 8
<code>00000000: f5 3c 0X 90 crng $cX</code>
<code>00000000: f5 3c 0X 90 crng $cX</code>
This instruction takes no operands and appears to initialize a crypto register with random data.
This instruction initializes a crypto register with random data.
Executing this instruction only succeeds if the TRNG is enabled for the SCP, which requires taking the following steps:
* Write 0x7FFF to TSEC_TRNG_CLKDIV.
* Write 0x3FF0000 to TSEC_TRNG_UNK0.
* Write 0xFF00 to TSEC_TRNG_UNK7.
* Write 0x1000 to [[#TSEC_SCP_CTL_TRNG|TSEC_SCP_CTL_TRNG]].
=== cxset ===
=== cxset ===