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TSEC (view source)

Revision as of 21:34, 24 September 2022

1,625 bytes added ,  21:34, 24 September 2022
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Line 49: Line 49:  
| [[#TSEC_THI_CONT_SYNCPT_L1|TSEC_THI_CONT_SYNCPT_L1]]
 
| [[#TSEC_THI_CONT_SYNCPT_L1|TSEC_THI_CONT_SYNCPT_L1]]
 
| 0x5450002C
 
| 0x5450002C
−
| 0x04
  −
|-
  −
| [[#TSEC_THI_STREAMID0|TSEC_THI_STREAMID0]]
  −
| 0x54500030
  −
| 0x04
  −
|-
  −
| [[#TSEC_THI_STREAMID1|TSEC_THI_STREAMID1]]
  −
| 0x54500034
  −
| 0x04
  −
|-
  −
| [[#TSEC_THI_THI_SEC|TSEC_THI_THI_SEC]]
  −
| 0x54500038
   
| 0x04
 
| 0x04
 
|-
 
|-
Line 307: Line 295:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_FALCON_UNK_E0
+
| [[#TSEC_FALCON_SIRQMASK|TSEC_FALCON_SIRQMASK]]
 
| 0x545010E0
 
| 0x545010E0
 
| 0x04
 
| 0x04
Line 547: Line 535:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_FALCON_SSTAT|TSEC_FALCON_SSTAT]]
+
| [[#TSEC_FALCON_SERRSTAT|TSEC_FALCON_SERRSTAT]]
 
| 0x54501244
 
| 0x54501244
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_FALCON_UNK_250
+
| [[#TSEC_FALCON_SERRVAL|TSEC_FALCON_SERRVAL]]
 +
| 0x54501248
 +
| 0x04
 +
|-
 +
| [[#TSEC_FALCON_SERRADDR|TSEC_FALCON_SERRADDR]]
 +
| 0x5450124C
 +
| 0x04
 +
|-
 +
| [[#TSEC_FALCON_SCTL1|TSEC_FALCON_SCTL1]]
 
| 0x54501250
 
| 0x54501250
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_FALCON_UNK_260
+
| [[#TSEC_FALCON_STEST|TSEC_FALCON_STEST]]
 +
| 0x54501258
 +
| 0x04
 +
|-
 +
| [[#TSEC_FALCON_SICD|TSEC_FALCON_SICD]]
 
| 0x54501260
 
| 0x54501260
 
| 0x04
 
| 0x04
Line 813: Line 813:  
| [[#TSEC_TFBIF_MCCIF_FIFOCTRL1|TSEC_TFBIF_MCCIF_FIFOCTRL1]]
 
| [[#TSEC_TFBIF_MCCIF_FIFOCTRL1|TSEC_TFBIF_MCCIF_FIFOCTRL1]]
 
| 0x54501634
 
| 0x54501634
−
| 0x04
  −
|-
  −
| [[#TSEC_TFBIF_WRR_RDP|TSEC_TFBIF_WRR_RDP]]
  −
| 0x54501638
   
| 0x04
 
| 0x04
 
|-
 
|-
Line 829: Line 825:  
| [[#TSEC_TFBIF_REGIONCFG|TSEC_TFBIF_REGIONCFG]]
 
| [[#TSEC_TFBIF_REGIONCFG|TSEC_TFBIF_REGIONCFG]]
 
| 0x54501648
 
| 0x54501648
−
| 0x04
  −
|-
  −
| [[#TSEC_TFBIF_ACTMON_ACTIVE_MASK|TSEC_TFBIF_ACTMON_ACTIVE_MASK]]
  −
| 0x5450164C
  −
| 0x04
  −
|-
  −
| [[#TSEC_TFBIF_ACTMON_ACTIVE_BORPS|TSEC_TFBIF_ACTMON_ACTIVE_BORPS]]
  −
| 0x54501650
  −
| 0x04
  −
|-
  −
| [[#TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT|TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT]]
  −
| 0x54501654
  −
| 0x04
  −
|-
  −
| [[#TSEC_TFBIF_ACTMON_MCB_MASK|TSEC_TFBIF_ACTMON_MCB_MASK]]
  −
| 0x54501660
  −
| 0x04
  −
|-
  −
| [[#TSEC_TFBIF_ACTMON_MCB_BORPS|TSEC_TFBIF_ACTMON_MCB_BORPS]]
  −
| 0x54501664
  −
| 0x04
  −
|-
  −
| [[#TSEC_TFBIF_ACTMON_MCB_WEIGHT|TSEC_TFBIF_ACTMON_MCB_WEIGHT]]
  −
| 0x54501668
  −
| 0x04
  −
|-
  −
| [[#TSEC_TFBIF_THI_TRANSPROP|TSEC_TFBIF_THI_TRANSPROP]]
  −
| 0x54501670
   
| 0x04
 
| 0x04
 
|-
 
|-
Line 879: Line 847:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_UNK_00
+
| [[#TSEC_VERSION|TSEC_VERSION]]
 
| 0x54501800
 
| 0x54501800
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_UNK_04
+
| [[#TSEC_SCRATCH0|TSEC_SCRATCH0]]
 
| 0x54501804
 
| 0x54501804
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_UNK_08
+
| [[#TSEC_SCRATCH1|TSEC_SCRATCH1]]
 
| 0x54501808
 
| 0x54501808
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_UNK_0C
+
| [[#TSEC_SCRATCH2|TSEC_SCRATCH2]]
 
| 0x5450180C
 
| 0x5450180C
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_UNK_10
+
| [[#TSEC_SCRATCH3|TSEC_SCRATCH3]]
 
| 0x54501810
 
| 0x54501810
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_UNK_14
+
| [[#TSEC_SCRATCH4|TSEC_SCRATCH4]]
 
| 0x54501814
 
| 0x54501814
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_UNK_18
+
| [[#TSEC_SCRATCH5|TSEC_SCRATCH5]]
 
| 0x54501818
 
| 0x54501818
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_UNK_1C
+
| [[#TSEC_SCRATCH6|TSEC_SCRATCH6]]
 
| 0x5450181C
 
| 0x5450181C
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_UNK_20
+
| [[#TSEC_SCRATCH7|TSEC_SCRATCH7]]
 
| 0x54501820
 
| 0x54501820
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_UNK_24
+
| [[#TSEC_GPTMRINT|TSEC_GPTMRINT]]
 
| 0x54501824
 
| 0x54501824
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_UNK_28
+
| [[#TSEC_GPTMRVAL|TSEC_GPTMRVAL]]
 
| 0x54501828
 
| 0x54501828
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_UNK_2C
+
| [[#TSEC_GPTMRCTL|TSEC_GPTMRCTL]]
 
| 0x5450182C
 
| 0x5450182C
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_UNK_30
+
| [[#TSEC_ITFEN|TSEC_ITFEN]]
 
| 0x54501830
 
| 0x54501830
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TEGRA_UNK_34
+
| [[#TSEC_ITFSTAT|TSEC_ITFSTAT]]
 
| 0x54501834
 
| 0x54501834
 
| 0x04
 
| 0x04
Line 1,075: Line 1,043:  
|}
 
|}
   −
=== TSEC_THI_STREAMID0 ===
+
=== TSEC_THI_METHOD0 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-6
+
| 0-11
−
| TSEC_THI_STREAMID0_ID
+
| TSEC_THI_METHOD0_OFFSET
 
|}
 
|}
   −
=== TSEC_THI_STREAMID1 ===
+
Used to encode and send a method's ID over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
−
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
  −
|-
  −
| 0-6
  −
| TSEC_THI_STREAMID1_ID
  −
|}
     −
=== TSEC_THI_THI_SEC ===
+
The following methods are available:
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
−
!  Bits
+
!  ID
−
!  Description
+
!  Method
 
|-
 
|-
−
| 0
+
| 0x100
−
| TSEC_THI_THI_SEC_TZ_LOCK
+
| NOP
 
|-
 
|-
−
| 4
+
| 0x140
−
| TSEC_THI_THI_SEC_TZ_AUTH
  −
|-
  −
| 8
  −
| TSEC_THI_THI_SEC_CH_LOCK
  −
|}
  −
 
  −
=== TSEC_THI_METHOD0 ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
  −
|-
  −
| 0-11
  −
| TSEC_THI_METHOD0_OFFSET
  −
|}
  −
 
  −
Used to encode and send a method's ID over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
  −
 
  −
The following methods are available:
  −
{| class="wikitable" border="1"
  −
!  ID
  −
!  Method
  −
|-
  −
| 0x100
  −
| NOP
  −
|-
  −
| 0x140
   
| PM_TRIGGER
 
| PM_TRIGGER
 
|-
 
|-
Line 2,054: Line 1,989:  
| 16
 
| 16
 
| TSEC_FALCON_DEBUG1_CTXSW_MODE
 
| TSEC_FALCON_DEBUG1_CTXSW_MODE
−
|-
  −
| 17
  −
| TSEC_FALCON_DEBUG1_TRACE_FORMAT
   
|}
 
|}
   Line 2,337: Line 2,269:  
=== TSEC_FALCON_RSTAT3 ===
 
=== TSEC_FALCON_RSTAT3 ===
 
Mirror of the [[#TSEC_FALCON_ICD_RDATA|ICD status register 3]].
 
Mirror of the [[#TSEC_FALCON_ICD_RDATA|ICD status register 3]].
 +
 +
=== TSEC_FALCON_SIRQMASK ===
 +
Unofficial name.
 +
 +
Same as [[#TSEC_FALCON_IRQMASK|TSEC_FALCON_IRQMASK]], but for LS mode.
    
=== TSEC_FALCON_CPUCTL ===
 
=== TSEC_FALCON_CPUCTL ===
Line 3,308: Line 3,245:  
|-
 
|-
 
| 4-5
 
| 4-5
 +
| Current access level
 +
|-
 +
| 8-9
 +
| Unknown access level
 +
|-
 +
| 12
 
| Unknown
 
| Unknown
 
|-
 
|-
−
| 12-13
+
| 13
 
| Unknown
 
| Unknown
 
|-
 
|-
Line 3,317: Line 3,260:  
|}
 
|}
   −
=== TSEC_FALCON_SSTAT ===
+
=== TSEC_FALCON_SERRSTAT ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 +
|-
 +
| 0-23
 +
| Unknown
 
|-
 
|-
 
| 30
 
| 30
Line 3,329: Line 3,275:  
|}
 
|}
   −
=== TSEC_FALCON_SPROT_IMEM ===
+
Unofficial name.
 +
 
 +
Used for detecting invalid CSB accesses in LS mode.
 +
 
 +
=== TSEC_FALCON_SERRVAL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 0-31
−
| Read access level
+
| Error code
−
|-
+
|}
−
| 4-7
+
 
−
| Write access level
+
Unofficial name.
−
|}
  −
 
  −
Controls accesses to Falcon IMEM.
     −
=== TSEC_FALCON_SPROT_DMEM ===
+
=== TSEC_FALCON_SERRADDR ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 0-31
−
| Read access level
+
| Error address
−
|-
  −
| 4-7
  −
| Write access level
   
|}
 
|}
   −
Controls accesses to Falcon DMEM.
+
Unofficial name.
   −
=== TSEC_FALCON_SPROT_CPUCTL ===
+
=== TSEC_FALCON_SCTL1 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 0-1
−
| Read access level
+
| CSB access level
 
|-
 
|-
−
| 4-7
+
| 2-3
−
| Write access level
+
| Unknown access level
 
|}
 
|}
   −
Controls accesses to the [[#TSEC_FALCON_CPUCTL|TSEC_FALCON_CPUCTL]] register.
+
Unofficial name.
   −
=== TSEC_FALCON_SPROT_MISC ===
+
=== TSEC_FALCON_STEST ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 0-31
−
| Read access level
+
| Unknown
−
|-
  −
| 4-7
  −
| Write access level
   
|}
 
|}
   −
Controls accesses to the following registers:
+
Unofficial name.
−
* [[#TSEC_FALCON_PRIVSTATE|TSEC_FALCON_PRIVSTATE]]
  −
* [[#TSEC_FALCON_SFTRESET|TSEC_FALCON_SFTRESET]]
  −
* [[#TSEC_FALCON_ADDR|TSEC_FALCON_ADDR]]
  −
* [[#TSEC_FALCON_DMACTL|TSEC_FALCON_DMACTL]]
  −
* [[#TSEC_FALCON_IMCTL|TSEC_FALCON_IMCTL]]
  −
* [[#TSEC_FALCON_IMSTAT|TSEC_FALCON_IMSTAT]]
  −
* TSEC_FALCON_UNK_250
  −
* [[#TSEC_FALCON_DMAINFO_CTL|TSEC_FALCON_DMAINFO_CTL]]
     −
=== TSEC_FALCON_SPROT_IRQ ===
+
=== TSEC_FALCON_SICD ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 0
−
| Read access level
+
| Enable access to ICD command STOP
 +
|-
 +
| 1
 +
| Enable access to ICD command RUN
 
|-
 
|-
−
| 4-7
+
| 2
−
| Write access level
+
| Enable access to ICD command RUNB
 +
|-
 +
| 3
 +
| Enable access to ICD command STEP
 +
|-
 +
| 4
 +
| Enable access to ICD command EMASK
 +
|-
 +
| 5
 +
| Enable access to ICD command RREG (only for SPRs)
 +
|-
 +
| 6
 +
| Enable access to ICD command RSTAT
 +
|-
 +
| 7
 +
| Enable access to IBRKPT registers
 +
|-
 +
| 8
 +
| Enable access to ICD command RREG (only for GPRs)
 +
|-
 +
| 9
 +
| Enable access to ICD command RDM
 
|}
 
|}
   −
Controls accesses to the following registers:
+
Unofficial name.
−
* [[#TSEC_FALCON_IRQMODE|TSEC_FALCON_IRQMODE]]
+
 
−
* [[#TSEC_FALCON_IRQMSET|TSEC_FALCON_IRQMSET]]
+
Controls access to the ICD in LS mode.
−
* [[#TSEC_FALCON_IRQMCLR|TSEC_FALCON_IRQMCLR]]
  −
* [[#TSEC_FALCON_IRQDEST|TSEC_FALCON_IRQDEST]]
  −
* [[#TSEC_FALCON_GPTMRINT|TSEC_FALCON_GPTMRINT]]
  −
* [[#TSEC_FALCON_GPTMRVAL|TSEC_FALCON_GPTMRVAL]]
  −
* [[#TSEC_FALCON_GPTMRCTL|TSEC_FALCON_GPTMRCTL]]
  −
* [[#TSEC_FALCON_IRQDEST2|TSEC_FALCON_IRQDEST2]]
  −
* TSEC_FALCON_UNK_E0
     −
=== TSEC_FALCON_SPROT_MTHD ===
+
=== TSEC_FALCON_SPROT_IMEM ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 0-2
 
| Read access level
 
| Read access level
 
|-
 
|-
−
| 4-7
+
| 3
 +
| Set on memory read access violation
 +
|-
 +
| 4-6
 
| Write access level
 
| Write access level
 +
|-
 +
| 7
 +
| Set on memory write access violation
 
|}
 
|}
   −
Controls accesses to the following registers:
+
Unofficial name.
−
* [[#TSEC_FALCON_ITFEN|TSEC_FALCON_ITFEN]]
+
 
−
* [[#TSEC_FALCON_CURCTX|TSEC_FALCON_CURCTX]]
+
Controls accesses to Falcon IMEM.
−
* [[#TSEC_FALCON_NXTCTX|TSEC_FALCON_NXTCTX]]
+
 
−
* [[#TSEC_FALCON_CTXACK|TSEC_FALCON_CTXACK]]
+
=== TSEC_FALCON_SPROT_DMEM ===
−
* [[#TSEC_FALCON_MTHDDATA|TSEC_FALCON_MTHDDATA]]
+
{| class="wikitable" border="1"
−
* [[#TSEC_FALCON_MTHDID|TSEC_FALCON_MTHDID]]
+
!  Bits
−
* [[#TSEC_FALCON_MTHDWDAT|TSEC_FALCON_MTHDWDAT]]
  −
* [[#TSEC_FALCON_MTHDCOUNT|TSEC_FALCON_MTHDCOUNT]]
  −
* [[#TSEC_FALCON_MTHDPOP|TSEC_FALCON_MTHDPOP]]
  −
* [[#TSEC_FALCON_MTHDRAMSZ|TSEC_FALCON_MTHDRAMSZ]]
  −
* [[#TSEC_FALCON_DEBUG1|TSEC_FALCON_DEBUG1]]
  −
 
  −
=== TSEC_FALCON_SPROT_SCTL ===
  −
{| class="wikitable" border="1"
  −
!  Bits
   
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 0-2
 
| Read access level
 
| Read access level
 
|-
 
|-
−
| 4-7
+
| 3
 +
| Set on memory read access violation
 +
|-
 +
| 4-6
 
| Write access level
 
| Write access level
 +
|-
 +
| 7
 +
| Set on memory write access violation
 
|}
 
|}
   −
Controls accesses to the [[#TSEC_FALCON_SCTL|TSEC_FALCON_SCTL]] register.
+
Unofficial name.
 +
 
 +
Controls accesses to Falcon DMEM.
   −
=== TSEC_FALCON_SPROT_WDTMR ===
+
=== TSEC_FALCON_SPROT_CPUCTL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 0-2
 
| Read access level
 
| Read access level
 
|-
 
|-
−
| 4-7
+
| 3
 +
| Set on memory read access violation
 +
|-
 +
| 4-6
 
| Write access level
 
| Write access level
 +
|-
 +
| 7
 +
| Set on memory write access violation
 
|}
 
|}
   −
Controls accesses to the following registers:
+
Unofficial name.
−
* [[#TSEC_FALCON_WDTMRVAL|TSEC_FALCON_WDTMRVAL]]
  −
* [[#TSEC_FALCON_WDTMRCTL|TSEC_FALCON_WDTMRCTL]]
     −
=== TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW ===
+
Controls accesses to the [[#TSEC_FALCON_CPUCTL|TSEC_FALCON_CPUCTL]] register.
−
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
  −
|-
  −
| 0-31
  −
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL
  −
|}
     −
=== TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH ===
+
=== TSEC_FALCON_SPROT_MISC ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-30
+
| 0-2
−
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL
+
| Read access level
 +
|-
 +
| 3
 +
| Set on memory read access violation
 +
|-
 +
| 4-6
 +
| Write access level
 
|-
 
|-
−
| 31
+
| 7
−
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT
+
| Set on memory write access violation
 
|}
 
|}
   −
=== TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW ===
+
Unofficial name.
 +
 
 +
Controls accesses to the following registers:
 +
* [[#TSEC_FALCON_PRIVSTATE|TSEC_FALCON_PRIVSTATE]]
 +
* [[#TSEC_FALCON_SFTRESET|TSEC_FALCON_SFTRESET]]
 +
* [[#TSEC_FALCON_ADDR|TSEC_FALCON_ADDR]]
 +
* [[#TSEC_FALCON_DMACTL|TSEC_FALCON_DMACTL]]
 +
* [[#TSEC_FALCON_IMCTL|TSEC_FALCON_IMCTL]]
 +
* [[#TSEC_FALCON_IMSTAT|TSEC_FALCON_IMSTAT]]
 +
* [[#TSEC_FALCON_SCTL1|TSEC_FALCON_SCTL1]]
 +
* [[#TSEC_FALCON_DMAINFO_CTL|TSEC_FALCON_DMAINFO_CTL]]
 +
 
 +
=== TSEC_FALCON_SPROT_IRQ ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-31
+
| 0-2
−
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL
+
| Read access level
−
|}
+
|-
−
 
+
| 3
−
=== TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH ===
+
| Set on memory read access violation
−
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0-30
+
| 4-6
−
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL
+
| Write access level
 
|-
 
|-
−
| 31
+
| 7
−
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT
+
| Set on memory write access violation
 
|}
 
|}
   −
=== TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW ===
+
Unofficial name.
 +
 
 +
Controls accesses to the following registers:
 +
* [[#TSEC_FALCON_IRQMODE|TSEC_FALCON_IRQMODE]]
 +
* [[#TSEC_FALCON_IRQMSET|TSEC_FALCON_IRQMSET]]
 +
* [[#TSEC_FALCON_IRQMCLR|TSEC_FALCON_IRQMCLR]]
 +
* [[#TSEC_FALCON_IRQDEST|TSEC_FALCON_IRQDEST]]
 +
* [[#TSEC_FALCON_GPTMRINT|TSEC_FALCON_GPTMRINT]]
 +
* [[#TSEC_FALCON_GPTMRVAL|TSEC_FALCON_GPTMRVAL]]
 +
* [[#TSEC_FALCON_GPTMRCTL|TSEC_FALCON_GPTMRCTL]]
 +
* [[#TSEC_FALCON_IRQDEST2|TSEC_FALCON_IRQDEST2]]
 +
* [[#TSEC_FALCON_SIRQMASK|TSEC_FALCON_SIRQMASK]]
 +
 
 +
=== TSEC_FALCON_SPROT_MTHD ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-31
+
| 0-2
−
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL
+
| Read access level
−
|}
+
|-
−
 
+
| 3
−
=== TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH ===
+
| Set on memory read access violation
−
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0-30
+
| 4-6
−
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL
+
| Write access level
 
|-
 
|-
−
| 31
+
| 7
−
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT
+
| Set on memory write access violation
 
|}
 
|}
   −
=== TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW ===
+
Unofficial name.
 +
 
 +
Controls accesses to the following registers:
 +
* [[#TSEC_FALCON_ITFEN|TSEC_FALCON_ITFEN]]
 +
* [[#TSEC_FALCON_CURCTX|TSEC_FALCON_CURCTX]]
 +
* [[#TSEC_FALCON_NXTCTX|TSEC_FALCON_NXTCTX]]
 +
* [[#TSEC_FALCON_CTXACK|TSEC_FALCON_CTXACK]]
 +
* [[#TSEC_FALCON_MTHDDATA|TSEC_FALCON_MTHDDATA]]
 +
* [[#TSEC_FALCON_MTHDID|TSEC_FALCON_MTHDID]]
 +
* [[#TSEC_FALCON_MTHDWDAT|TSEC_FALCON_MTHDWDAT]]
 +
* [[#TSEC_FALCON_MTHDCOUNT|TSEC_FALCON_MTHDCOUNT]]
 +
* [[#TSEC_FALCON_MTHDPOP|TSEC_FALCON_MTHDPOP]]
 +
* [[#TSEC_FALCON_MTHDRAMSZ|TSEC_FALCON_MTHDRAMSZ]]
 +
* [[#TSEC_FALCON_DEBUG1|TSEC_FALCON_DEBUG1]]
 +
 
 +
=== TSEC_FALCON_SPROT_SCTL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-31
+
| 0-2
−
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL
+
| Read access level
 +
|-
 +
| 3
 +
| Set on memory read access violation
 +
|-
 +
| 4-6
 +
| Write access level
 +
|-
 +
| 7
 +
| Set on memory write access violation
 
|}
 
|}
   −
=== TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH ===
+
Unofficial name.
 +
 
 +
Controls accesses to the [[#TSEC_FALCON_SCTL|TSEC_FALCON_SCTL]] register.
 +
 
 +
=== TSEC_FALCON_SPROT_WDTMR ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-30
+
| 0-2
−
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL
+
| Read access level
 +
|-
 +
| 3
 +
| Set on memory read access violation
 +
|-
 +
| 4-6
 +
| Write access level
 
|-
 
|-
−
| 31
+
| 7
−
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT
+
| Set on memory write access violation
 
|}
 
|}
   −
=== TSEC_FALCON_DMAINFO_CTL ===
+
Unofficial name.
 +
 
 +
Controls accesses to the following registers:
 +
* [[#TSEC_FALCON_WDTMRVAL|TSEC_FALCON_WDTMRVAL]]
 +
* [[#TSEC_FALCON_WDTMRCTL|TSEC_FALCON_WDTMRCTL]]
 +
 
 +
=== TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-31
−
| TSEC_FALCON_DMAINFO_CTL_CLR_FBRD
+
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL
−
|-
  −
| 1
  −
| TSEC_FALCON_DMAINFO_CTL_CLR_FBWR
   
|}
 
|}
   −
=== TSEC_SCP_CTL0 ===
+
=== TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 10
+
| 0-30
−
| Enable [[#LOAD|Falcon<->LOAD]] interface
+
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL
 
|-
 
|-
−
| 12
+
| 31
−
| Enable [[#STORE|Falcon<->STORE]] interface
+
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT
−
|-
  −
| 14
  −
| Enable [[#CMD|Falcon<->CMD]] interface
  −
|-
  −
| 16
  −
| Enable [[#SEQ|SEQ]]
  −
|-
  −
| 20
  −
| Enable [[#CTL|CTL]]
   
|}
 
|}
   −
=== TSEC_SCP_CTL1 ===
+
=== TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-31
−
| Clear [[#SEQ|SEQ]]
+
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL
−
|-
  −
| 8
  −
| Clear [[#SCP|SCP]]'s internal pipeline
  −
|-
  −
| 11
  −
| Enable [[#RNG|RNG]]'s test mode
  −
|-
  −
| 12
  −
| Enable [[#RNG|RNG]]
  −
|-
  −
| 16
  −
| Enable [[#LOAD|Falcon<->LOAD]] interface's dummy mode (all reads return 0)
  −
|-
  −
| 20
  −
| Enable [[#LOAD|Falcon<->LOAD]] interface bypassing (all reads are dropped)
  −
|-
  −
| 24
  −
| Enable [[#STORE|Falcon<->STORE]] interface bypassing (all writes are dropped)
   
|}
 
|}
   −
=== TSEC_SCP_CTL_STAT ===
+
=== TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 20
+
| 0-30
−
| TSEC_SCP_CTL_STAT_DEBUG_MODE
+
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL
−
|}
+
|-
 +
| 31
 +
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT
 +
|}
 +
 
 +
=== TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL
 +
|}
   −
=== TSEC_SCP_CTL_LOCK ===
+
=== TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-30
−
| Enable lockdown mode (locks IMEM and DMEM)
+
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL
 
|-
 
|-
−
| 4
+
| 31
−
| Lock [[#SCP|SCP]]'s MMIO register space
+
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT
 
|}
 
|}
   −
Controls lockdown mode and can only be cleared in Heavy Secure mode.
+
=== TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-31
 +
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL
 +
|}
   −
=== TSEC_SCP_CFG ===
+
=== TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-30
−
| Endianness for ADD
+
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL
−
0: Little
  −
1: Big
   
|-
 
|-
−
| 1
+
| 31
−
| Endianness for GFMUL
+
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT
−
0: Little
+
|}
−
1: Big
+
 
−
|-
+
=== TSEC_FALCON_DMAINFO_CTL ===
−
| 2
  −
| Endianness for [[#LOAD|LOAD]]
  −
0: Little
  −
1: Big
  −
|-
  −
| 3
  −
| Endianness for [[#STORE|STORE]]
  −
0: Little
  −
1: Big
  −
|-
  −
| 4
  −
| Endianness for [[#AES|AES]]
  −
0: Little
  −
1: Big
  −
|-
  −
| 8
  −
| Flush [[#CMD|CMD]]
  −
|-
  −
| 12-13
  −
| Carry chain's size
  −
0: 32 bits
  −
1: 64 bits
  −
2: 96 bits
  −
3: 128 bits
  −
|-
  −
| 16-31
  −
| [[#SCP|SCP]]'s internal pipeline stall timeout value
  −
|}
  −
 
  −
=== TSEC_SCP_CTL_SCP ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 3,688: Line 3,662:  
|-
 
|-
 
| 0
 
| 0
−
| Swap [[#SCP|SCP]]'s master
+
| TSEC_FALCON_DMAINFO_CTL_CLR_FBRD
 
|-
 
|-
 
| 1
 
| 1
−
| Current [[#SCP|SCP]]'s master
+
| TSEC_FALCON_DMAINFO_CTL_CLR_FBWR
−
0: Falcon
  −
1: External
   
|}
 
|}
   −
=== TSEC_SCP_CTL_PKEY ===
+
=== TSEC_SCP_CTL0 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 10
−
| TSEC_SCP_CTL_PKEY_REQUEST_RELOAD
+
| Enable [[#LOAD|Falcon<->LOAD]] interface
 
|-
 
|-
−
| 1
+
| 12
−
| TSEC_SCP_CTL_PKEY_LOADED
+
| Enable [[#STORE|Falcon<->STORE]] interface
 +
|-
 +
| 14
 +
| Enable [[#CMD|Falcon<->CMD]] interface
 +
|-
 +
| 16
 +
| Enable [[#SEQ|SEQ]]
 +
|-
 +
| 20
 +
| Enable [[#CTL|CTL]]
 
|}
 
|}
   −
=== TSEC_SCP_CTL_DBG ===
+
Unofficial name.
 +
 
 +
=== TSEC_SCP_CTL1 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 4
+
| 0
−
| Disable lockdown mode
+
| Clear [[#SEQ|SEQ]]
 
|-
 
|-
 
| 8
 
| 8
−
| Disable locking of [[#SCP|SCP]]'s MMIO register space
+
| Clear [[#SCP|SCP]]'s internal pipeline
 +
|-
 +
| 11
 +
| Enable [[#RNG|RNG]]'s test mode
 +
|-
 +
| 12
 +
| Enable [[#RNG|RNG]]
 +
|-
 +
| 16
 +
| Enable [[#LOAD|Falcon<->LOAD]] interface's dummy mode (all reads return 0)
 +
|-
 +
| 20
 +
| Enable [[#LOAD|Falcon<->LOAD]] interface bypassing (all reads are dropped)
 +
|-
 +
| 24
 +
| Enable [[#STORE|Falcon<->STORE]] interface bypassing (all writes are dropped)
 
|}
 
|}
   −
Overrides lockdown mode, but can only be set in debug mode.
+
Unofficial name.
   −
=== TSEC_SCP_DBG0 ===
+
=== TSEC_SCP_CTL_STAT ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 20
−
| Index
+
| TSEC_SCP_CTL_STAT_DEBUG_MODE
 +
|}
 +
 
 +
=== TSEC_SCP_CTL_LOCK ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| 4
+
| 0
−
| Auto-increment
+
| Enable lockdown mode (locks IMEM and DMEM)
 
|-
 
|-
−
| 5-6
+
| 1
−
| Target
+
| Lockdown has pending exit request
−
0: None
  −
1: STORE
  −
2: LOAD
  −
3: SEQ
   
|-
 
|-
−
| 8-12
+
| 2
−
| [[#SEQ|SEQ]]'s current sequence's size
+
| Lockdown has been enabled before
 
|-
 
|-
−
| 13-16
+
| 4
−
| [[#SEQ|SEQ]]'s current instruction's address
+
| Enable SCP lockdown mode (locks [[#SCP|SCP]]'s MMIO register space)
 
|-
 
|-
−
| 17
+
| 6
−
| [[#SEQ|SEQ]]'s current instruction is valid
+
| SCP lockdown has been enabled before
−
|-
  −
| 18
  −
| [[#SEQ|SEQ]] is running in HS mode
  −
|-
  −
| 19-22
  −
| [[#LOAD|LOAD]]'s queue's size
  −
|-
  −
| 23
  −
| [[#LOAD|LOAD]]'s current operation is valid
  −
|-
  −
| 24
  −
| [[#LOAD|LOAD]] is running in HS mode
  −
|-
  −
| 25-26
  −
| [[#STORE|STORE]]'s queue's size
  −
|-
  −
| 30
  −
| [[#STORE|STORE]]'s current operation is valid
  −
|-
  −
| 31
  −
| [[#STORE|STORE]] is running in HS mode
   
|}
 
|}
   −
Used for debugging the [[#LOAD|LOAD]], [[#STORE|STORE]] and [[#SEQ|SEQ]] blocks.
+
Unofficial name.
 +
 
 +
Controls lockdown mode. Can only be cleared in HS mode.
   −
=== TSEC_SCP_DBG1 ===
+
=== TSEC_SCP_CFG ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-31
+
| 0
−
| Data
+
| Endianness for ADD
−
  If target is SEQ:
+
0: Little
−
  Bits 0-3: current instruction's first operand
+
1: Big
−
  Bits 4-9: current instruction's second operand
+
|-
−
  Bits 10-14: current instruction's opcode
+
| 1
 +
| Endianness for GFMUL
 +
0: Little
 +
  1: Big
 +
|-
 +
| 2
 +
| Endianness for [[#LOAD|LOAD]]
 +
0: Little
 +
1: Big
 +
|-
 +
| 3
 +
| Endianness for [[#STORE|STORE]]
 +
0: Little
 +
1: Big
 +
|-
 +
| 4
 +
| Endianness for [[#AES|AES]]
 +
0: Little
 +
1: Big
 +
|-
 +
| 8
 +
| Flush [[#CMD|CMD]]
 +
|-
 +
| 12-13
 +
| Carry chain's size
 +
0: 32 bits
 +
1: 64 bits
 +
2: 96 bits
 +
3: 128 bits
 +
|-
 +
| 16-31
 +
| [[#SCP|SCP]]'s internal pipeline stall timeout value
 
|}
 
|}
   −
Used for retrieving debug data. Contains information on the last crypto sequence created when debugging the [[#SEQ|SEQ]] block.
+
Unofficial name.
   −
=== TSEC_SCP_DBG2 ===
+
=== TSEC_SCP_CTL_SCP ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-1
+
| 0
−
| [[#SEQ|SEQ]]'s state
+
| Swap [[#SCP|SCP]]'s master
−
  0: Idle
+
|-
−
  1: Recording (cs0begin/cs1begin)
+
| 1
−
  2: Executing (cs0exec/cs1exec)
+
| Current [[#SCP|SCP]]'s master
 +
  0: Falcon
 +
  1: External
 +
|}
 +
 
 +
Unofficial name.
 +
 
 +
=== TSEC_SCP_CTL_PKEY ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
! Description
 +
|-
 +
| 0
 +
| TSEC_SCP_CTL_PKEY_REQUEST_RELOAD
 +
|-
 +
| 1
 +
| TSEC_SCP_CTL_PKEY_LOADED
 +
|}
 +
 
 +
=== TSEC_SCP_CTL_DBG ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| 4-7
+
| 4
−
| Number of cycles left for [[#SEQ|SEQ]]'s current sequence
+
| Disable lockdown mode
 
|-
 
|-
−
| 12-15
+
| 8
−
| Active crypto key register (ckeyreg)
+
| Disable SCP lockdown mode
 
|}
 
|}
   −
Used for retrieving additional debug data associated with the [[#SEQ|SEQ]] block.
+
Unofficial name.
 +
 
 +
Overrides lockdown mode. Can only be set in debug mode.
   −
=== TSEC_SCP_CMD ===
+
=== TSEC_SCP_DBG0 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 3,814: Line 3,850:  
|-
 
|-
 
| 0-3
 
| 0-3
−
| Destination register
+
| Index
 
|-
 
|-
−
| 8-13
+
| 4
−
| Source register or immediate value
+
| Auto-increment
 
|-
 
|-
−
| 20-24
+
| 5-6
−
| Command opcode
+
| Target
−
  0x0: nop (fuc5 opcode 0x00)
+
  0: None
−
  0x1: cmov (fuc5 opcode 0x84)
+
  1: STORE
−
  0x2: cxsin (fuc5 opcode 0x88) or xdst (with cxset)
+
  2: LOAD
−
  0x3: cxsout (fuc5 opcode 0x8C) or xdld (with cxset)
+
  3: SEQ
−
0x4:  crnd (fuc5 opcode 0x90)
+
|-
−
0x5:  cs0begin (fuc5 opcode 0x94)
+
| 8-12
−
0x6:  cs0exec (fuc5 opcode 0x98)
+
| [[#SEQ|SEQ]]'s current sequence's size
−
0x7:  cs1begin (fuc5 opcode 0x9C)
  −
0x8:  cs1exec (fuc5 opcode 0xA0)
  −
0x9:  invalid (fuc5 opcode 0xA4)
  −
0xA:  cchmod (fuc5 opcode 0xA8)
  −
0xB:  cxor (fuc5 opcode 0xAC)
  −
0xC:  cadd (fuc5 opcode 0xB0)
  −
0xD:  cand (fuc5 opcode 0xB4)
  −
0xE:  crev (fuc5 opcode 0xB8)
  −
0xF:  cgfmul (fuc5 opcode 0xBC)
  −
0x10: csecret (fuc5 opcode 0xC0)
  −
0x11: ckeyreg (fuc5 opcode 0xC4)
  −
0x12: ckexp (fuc5 opcode 0xC8)
  −
0x13: ckrexp (fuc5 opcode 0xCC)
  −
0x14: cenc (fuc5 opcode 0xD0)
  −
0x15: cdec (fuc5 opcode 0xD4)
  −
0x16: csigcmp (fuc5 opcode 0xD8)
  −
0x17: csigenc (fuc5 opcode 0xDC)
  −
0x18: csigclr (fuc5 opcode 0xE0)
   
|-
 
|-
−
| 28
+
| 13-16
−
| [[#CMD|CMD]]'s current instruction is valid
+
| [[#SEQ|SEQ]]'s current instruction's address
 
|-
 
|-
−
| 31
+
| 17
−
| [[#CMD|CMD]] is running in HS mode
+
| [[#SEQ|SEQ]]'s current instruction is valid
−
|}
  −
 
  −
Contains information on the last crypto command executed.
  −
 
  −
=== TSEC_SCP_STAT0 ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0
+
| 18
−
| [[#SCP|SCP]] is active
+
| [[#SEQ|SEQ]] is running in HS mode
 
|-
 
|-
−
| 2
+
| 19-22
−
| [[#CMD|CMD]] is active
+
| [[#LOAD|LOAD]]'s queue's size
 
|-
 
|-
−
| 4
+
| 23
−
| [[#STORE|STORE]] is active
+
| [[#LOAD|LOAD]]'s current operation is valid
 
|-
 
|-
−
| 6
+
| 24
−
| [[#SEQ|SEQ]] is active
+
| [[#LOAD|LOAD]] is running in HS mode
 
|-
 
|-
−
| 8
+
| 25-26
−
| [[#CTL|CTL]] is active
+
| [[#STORE|STORE]]'s queue's size
 
|-
 
|-
−
| 10
+
| 30
−
| [[#LOAD|LOAD]] is active
+
| [[#STORE|STORE]]'s current operation is valid
 
|-
 
|-
−
| 14
+
| 31
−
| [[#AES|AES]] is active
+
| [[#STORE|STORE]] is running in HS mode
−
|-
  −
| 16
  −
| [[#RNG|RNG]] is active
   
|}
 
|}
   −
Contains the statuses of hardware blocks.
+
Unofficial name.
 +
 
 +
Used for debugging the [[#LOAD|LOAD]], [[#STORE|STORE]] and [[#SEQ|SEQ]] blocks.
   −
=== TSEC_SCP_STAT1 ===
+
=== TSEC_SCP_DBG1 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-1
+
| 0-31
−
| Signature comparison result
+
| Data
−
  0: None
+
  If target is SEQ:
−
1: Running
+
  Bits 0-3: current instruction's first operand
−
  2: Failed
+
  Bits 4-9: current instruction's second operand
−
  3: Succeeded
+
  Bits 10-14: current instruction's opcode
 +
|}
 +
 
 +
Unofficial name.
 +
 
 +
Used for retrieving debug data. Contains information on the last crypto sequence created when debugging the [[#SEQ|SEQ]] block.
 +
 
 +
=== TSEC_SCP_DBG2 ===
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 
|-
 
|-
−
| 4
+
| 0-1
−
| [[#LOAD|Falcon<->LOAD]] interface is running in HS mode
+
| [[#SEQ|SEQ]]'s state
 +
0: Idle
 +
1: Recording (cs0begin/cs1begin)
 +
2: Executing (cs0exec/cs1exec)
 
|-
 
|-
−
| 6
+
| 4-7
−
| [[#LOAD|Falcon<->LOAD]] interface is ready
+
| Number of cycles left for [[#SEQ|SEQ]]'s current sequence
 
|-
 
|-
−
| 8
+
| 12-15
−
| [[#STORE|Falcon<->STORE]] interface is running in HS mode
+
| Active crypto key register (ckeyreg)
−
|-
  −
| 10
  −
| [[#STORE|Falcon<->STORE]] interface received a valid operation
  −
|-
  −
| 12
  −
| [[#CMD|Falcon<->CMD]] interface is running in HS mode
  −
|-
  −
| 14
  −
| [[#CMD|Falcon<->CMD]] interface received a valid instruction
   
|}
 
|}
   −
Contains the statuses of hardware interfaces and the result of the last authentication attempt.
+
Unofficial name.
 +
 
 +
Used for retrieving additional debug data associated with the [[#SEQ|SEQ]] block.
   −
=== TSEC_SCP_STAT2 ===
+
=== TSEC_SCP_CMD ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-4
+
| 0-3
−
| Current opcode in [[#SEQ|SEQ]]
+
| Destination register
 
|-
 
|-
−
| 5-9
+
| 8-13
−
| Current opcode in [[#CMD|Falcon<->CMD]] interface
+
| Source register or immediate value
 
|-
 
|-
−
| 10-14
+
| 20-24
−
| Pending opcode in [[#CMD|CMD]]
+
| Command opcode
 +
0x0:  nop (fuc5 opcode 0x00)
 +
0x1:  cmov (fuc5 opcode 0x84)
 +
0x2:  cxsin (fuc5 opcode 0x88) or xdst (with cxset)
 +
0x3:  cxsout (fuc5 opcode 0x8C) or xdld (with cxset)
 +
0x4:  crnd (fuc5 opcode 0x90)
 +
0x5:  cs0begin (fuc5 opcode 0x94)
 +
0x6:  cs0exec (fuc5 opcode 0x98)
 +
0x7:  cs1begin (fuc5 opcode 0x9C)
 +
0x8:  cs1exec (fuc5 opcode 0xA0)
 +
0x9:  invalid (fuc5 opcode 0xA4)
 +
0xA:  cchmod (fuc5 opcode 0xA8)
 +
0xB:  cxor (fuc5 opcode 0xAC)
 +
0xC:  cadd (fuc5 opcode 0xB0)
 +
0xD:  cand (fuc5 opcode 0xB4)
 +
0xE:  crev (fuc5 opcode 0xB8)
 +
0xF:  cgfmul (fuc5 opcode 0xBC)
 +
0x10: csecret (fuc5 opcode 0xC0)
 +
0x11: ckeyreg (fuc5 opcode 0xC4)
 +
0x12: ckexp (fuc5 opcode 0xC8)
 +
0x13: ckrexp (fuc5 opcode 0xCC)
 +
0x14: cenc (fuc5 opcode 0xD0)
 +
0x15: cdec (fuc5 opcode 0xD4)
 +
0x16: csigcmp (fuc5 opcode 0xD8)
 +
0x17: csigenc (fuc5 opcode 0xDC)
 +
0x18: csigclr (fuc5 opcode 0xE0)
 
|-
 
|-
−
| 15-16
+
| 28
−
| Current opcode in [[#AES|AES]]
+
| [[#CMD|CMD]]'s current instruction is valid
−
0: Encryption
  −
1: Decryption
  −
2: Key expansion
  −
3: Key reverse expansion
   
|-
 
|-
−
| 24
+
| 31
−
| [[#SCP|SCP]]'s internal pipeline is stalled on hazard
+
| [[#CMD|CMD]] is running in HS mode
−
|-
  −
| 25
  −
| [[#STORE|STORE]] is stalled
  −
|-
  −
| 26
  −
| [[#LOAD|LOAD]] is stalled
  −
|-
  −
| 27
  −
| [[#RNG|RNG]] is stalled
  −
|-
  −
| 28
  −
| [[#SCP|SCP]]'s internal pipeline is stalled on writeback
  −
|-
  −
| 29
  −
| [[#AES|AES]] is stalled
   
|}
 
|}
   −
Contains the status of crypto operations.
+
Unofficial name.
 +
 
 +
Contains information on the last crypto command executed.
   −
=== TSEC_SCP_RNG_STAT0 ===
+
=== TSEC_SCP_STAT0 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 3,969: Line 3,992:  
|-
 
|-
 
| 0
 
| 0
−
| [[#RND|RND]] is ready
+
| [[#SCP|SCP]] is active
 +
|-
 +
| 2
 +
| [[#CMD|CMD]] is active
 +
|-
 +
| 4
 +
| [[#STORE|STORE]] is active
 
|-
 
|-
−
| 4-7
+
| 6
−
| Unknown
+
| [[#SEQ|SEQ]] is active
 
|-
 
|-
−
| 8-11
+
| 8
−
| Unknown
+
| [[#CTL|CTL]] is active
 
|-
 
|-
−
| 16
+
| 10
−
| Unknown
+
| [[#LOAD|LOAD]] is active
 
|-
 
|-
−
| 20
+
| 14
−
| Unknown
+
| [[#AES|AES]] is active
−
|}
+
|-
 +
| 16
 +
| [[#RNG|RNG]] is active
 +
|}
 +
 
 +
Unofficial name.
 +
 
 +
Contains the statuses of hardware blocks.
   −
=== TSEC_SCP_RNG_STAT1 ===
+
=== TSEC_SCP_STAT1 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-15
+
| 0-1
−
| Unknown
+
| Signature comparison result
 +
0: None
 +
1: Running
 +
2: Failed
 +
3: Succeeded
 
|-
 
|-
−
| 16-31
+
| 4
−
| Unknown
+
| [[#LOAD|Falcon<->LOAD]] interface is running in HS mode
−
|}
  −
 
  −
=== TSEC_SCP_IRQSTAT ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0
+
| 6
−
| [[#RND|RND]] ready
+
| [[#LOAD|Falcon<->LOAD]] interface is ready
 
|-
 
|-
 
| 8
 
| 8
−
| ACL error
+
| [[#STORE|Falcon<->STORE]] interface is running in HS mode
 +
|-
 +
| 10
 +
| [[#STORE|Falcon<->STORE]] interface received a valid operation
 
|-
 
|-
 
| 12
 
| 12
−
| SEC error
+
| [[#CMD|Falcon<->CMD]] interface is running in HS mode
 
|-
 
|-
−
| 16
+
| 14
−
| [[#CMD|CMD]] error
+
| [[#CMD|Falcon<->CMD]] interface received a valid instruction
 +
|}
 +
 
 +
Unofficial name.
 +
 
 +
Contains the statuses of hardware interfaces and the result of the last authentication attempt.
 +
 
 +
=== TSEC_SCP_STAT2 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-4
 +
| Current opcode in [[#SEQ|SEQ]]
 
|-
 
|-
−
| 20
+
| 5-9
−
| Single step
+
| Current opcode in [[#CMD|Falcon<->CMD]] interface
 +
|-
 +
| 10-14
 +
| Pending opcode in [[#CMD|CMD]]
 +
|-
 +
| 15-16
 +
| Current opcode in [[#AES|AES]]
 +
0: Encryption
 +
1: Decryption
 +
2: Key expansion
 +
3: Key reverse expansion
 
|-
 
|-
 
| 24
 
| 24
−
| [[#RND|RND]] clock trigger
+
| [[#SCP|SCP]]'s internal pipeline is stalled on hazard
 +
|-
 +
| 25
 +
| [[#STORE|STORE]] is stalled
 +
|-
 +
| 26
 +
| [[#LOAD|LOAD]] is stalled
 +
|-
 +
| 27
 +
| [[#RNG|RNG]] is stalled
 
|-
 
|-
 
| 28
 
| 28
−
| Stall timeout
+
| [[#SCP|SCP]]'s internal pipeline is stalled on writeback
 +
|-
 +
| 29
 +
| [[#AES|AES]] is stalled
 
|}
 
|}
   −
=== TSEC_SCP_IRQMASK ===
+
Unofficial name.
 +
 
 +
Contains the status of crypto operations.
 +
 
 +
=== TSEC_SCP_RNG_STAT0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| [[#RND|RND]] is ready
 +
|-
 +
| 4-7
 +
| Unknown
 +
|-
 +
| 8-11
 +
| Unknown
 +
|-
 +
| 16
 +
| Unknown
 +
|-
 +
| 20
 +
| Unknown
 +
|}
 +
 
 +
Unofficial name.
 +
 
 +
=== TSEC_SCP_RNG_STAT1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-15
 +
| Unknown
 +
|-
 +
| 16-31
 +
| Unknown
 +
|}
 +
 
 +
Unofficial name.
 +
 
 +
=== TSEC_SCP_IRQSTAT ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 4,050: Line 4,163:  
|}
 
|}
   −
=== TSEC_SCP_ACL_ERR ===
+
Unofficial name.
 +
 
 +
=== TSEC_SCP_IRQMASK ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 4,056: Line 4,171:  
|-
 
|-
 
| 0
 
| 0
−
| Writing to a crypto register without the correct ACL
+
| [[#RND|RND]] ready
−
|-
  −
| 4
  −
| Reading from a crypto register without the correct ACL
   
|-
 
|-
 
| 8
 
| 8
−
| Invalid ACL change (cchmod)
+
| ACL error
 
|-
 
|-
−
| 31
+
| 12
 +
| SEC error
 +
|-
 +
| 16
 +
| [[#CMD|CMD]] error
 +
|-
 +
| 20
 +
| Single step
 +
|-
 +
| 24
 +
| [[#RND|RND]] clock trigger
 +
|-
 +
| 28
 +
| Stall timeout
 +
|}
 +
 
 +
Unofficial name.
 +
 
 +
=== TSEC_SCP_ACL_ERR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Writing to a crypto register without the correct ACL
 +
|-
 +
| 4
 +
| Reading from a crypto register without the correct ACL
 +
|-
 +
| 8
 +
| Invalid ACL change (cchmod)
 +
|-
 +
| 31
 
| ACL error occurred
 
| ACL error occurred
 
|}
 
|}
 +
 +
Unofficial name.
    
Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|ACL error]] IRQ.
 
Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|ACL error]] IRQ.
Line 4,118: Line 4,264:  
| SEC error occurred
 
| SEC error occurred
 
|}
 
|}
 +
 +
Unofficial name.
    
Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|SEC error]] IRQ.
 
Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|SEC error]] IRQ.
Line 4,147: Line 4,295:  
| Forbidden ACL change (cchmod in NS mode)
 
| Forbidden ACL change (cchmod in NS mode)
 
|}
 
|}
 +
 +
Unofficial name.
    
Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|CMD error]] IRQ.
 
Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|CMD error]] IRQ.
Line 4,158: Line 4,308:  
| [[#RND|RND]] clock trigger's lower limit
 
| [[#RND|RND]] clock trigger's lower limit
 
|}
 
|}
 +
 +
Unofficial name.
    
=== TSEC_SCP_RND_CTL1 ===
 
=== TSEC_SCP_RND_CTL1 ===
Line 4,170: Line 4,322:  
| [[#RND|RND]] clock trigger's mask
 
| [[#RND|RND]] clock trigger's mask
 
|}
 
|}
 +
 +
Unofficial name.
    
=== TSEC_SCP_RND_CTL2 ===
 
=== TSEC_SCP_RND_CTL2 ===
Line 4,179: Line 4,333:  
| Unknown
 
| Unknown
 
|}
 
|}
 +
 +
Unofficial name.
    
=== TSEC_SCP_RND_CTL3 ===
 
=== TSEC_SCP_RND_CTL3 ===
Line 4,191: Line 4,347:  
| Trigger second LFSR
 
| Trigger second LFSR
 
|}
 
|}
 +
 +
Unofficial name.
    
=== TSEC_SCP_RND_CTL4 ===
 
=== TSEC_SCP_RND_CTL4 ===
Line 4,200: Line 4,358:  
| First LFSR's polynomial for [[#RNG|RNG]]'s test mode
 
| First LFSR's polynomial for [[#RNG|RNG]]'s test mode
 
|}
 
|}
 +
 +
Unofficial name.
    
=== TSEC_SCP_RND_CTL5 ===
 
=== TSEC_SCP_RND_CTL5 ===
Line 4,209: Line 4,369:  
| First LFSR's initial state for [[#RNG|RNG]]'s test mode
 
| First LFSR's initial state for [[#RNG|RNG]]'s test mode
 
|}
 
|}
 +
 +
Unofficial name.
    
=== TSEC_SCP_RND_CTL6 ===
 
=== TSEC_SCP_RND_CTL6 ===
Line 4,218: Line 4,380:  
| Second LFSR's polynomial for [[#RNG|RNG]]'s test mode
 
| Second LFSR's polynomial for [[#RNG|RNG]]'s test mode
 
|}
 
|}
 +
 +
Unofficial name.
    
=== TSEC_SCP_RND_CTL7 ===
 
=== TSEC_SCP_RND_CTL7 ===
Line 4,227: Line 4,391:  
| Second LFSR's initial state for [[#RNG|RNG]]'s test mode
 
| Second LFSR's initial state for [[#RNG|RNG]]'s test mode
 
|}
 
|}
 +
 +
Unofficial name.
    
=== TSEC_SCP_RND_CTL8 ===
 
=== TSEC_SCP_RND_CTL8 ===
Line 4,239: Line 4,405:  
| Unknown
 
| Unknown
 
|}
 
|}
 +
 +
Unofficial name.
    
=== TSEC_SCP_RND_CTL9 ===
 
=== TSEC_SCP_RND_CTL9 ===
Line 4,251: Line 4,419:  
| Unknown
 
| Unknown
 
|}
 
|}
 +
 +
Unofficial name.
    
=== TSEC_SCP_RND_CTL10 ===
 
=== TSEC_SCP_RND_CTL10 ===
Line 4,263: Line 4,433:  
| Unknown
 
| Unknown
 
|}
 
|}
 +
 +
Unofficial name.
    
=== TSEC_SCP_RND_CTL11 ===
 
=== TSEC_SCP_RND_CTL11 ===
Line 4,313: Line 4,485:  
| Unknown
 
| Unknown
 
|}
 
|}
 +
 +
Unofficial name.
    
=== TSEC_TFBIF_CTL ===
 
=== TSEC_TFBIF_CTL ===
Line 4,546: Line 4,720:  
| 16-31
 
| 16-31
 
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SWR2MC_REORDER_DEPTH_LIMIT
 
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SWR2MC_REORDER_DEPTH_LIMIT
−
|}
  −
  −
=== TSEC_TFBIF_WRR_RDP ===
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
  −
|-
  −
| 0-15
  −
| TSEC_TFBIF_WRR_RDP_EXT_WEIGHT
  −
|-
  −
| 16-31
  −
| TSEC_TFBIF_WRR_RDP_INT_WEIGHT
   
|}
 
|}
   Line 4,565: Line 4,727:  
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 0-2
 
| Read access level
 
| Read access level
 
|-
 
|-
−
| 4-7
+
| 3
 +
| Set on memory read access violation
 +
|-
 +
| 4-6
 
| Write access level
 
| Write access level
 +
|-
 +
| 7
 +
| Set on memory write access violation
 
|}
 
|}
 +
 +
Unofficial name.
    
Controls accesses to external memory regions. Accessible in HS mode only.
 
Controls accesses to external memory regions. Accessible in HS mode only.
Line 4,666: Line 4,836:  
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
 
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
   −
=== TSEC_TFBIF_ACTMON_ACTIVE_MASK ===
+
=== TSEC_CG ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-5
−
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_STARVED_MC
+
| TSEC_CG_IDLE_CG_DLY_CNT
 
|-
 
|-
−
| 1
+
| 6
−
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_STALLED_MC
+
| TSEC_CG_IDLE_CG_EN
 
|-
 
|-
−
| 2
+
| 16-18
−
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED_MC
+
| TSEC_CG_WAKEUP_DLY_CNT
 
|-
 
|-
−
| 3
+
| 19
−
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_ACTIVE
+
| TSEC_CG_WAKEUP_DLY_EN
 
|}
 
|}
   −
Takes the memory access mask for the Activity Monitor. Disconnected on the TSEC.
+
=== TSEC_BAR0_CTL ===
−
 
  −
=== TSEC_TFBIF_ACTMON_ACTIVE_BORPS ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 4,692: Line 4,860:  
|-
 
|-
 
| 0
 
| 0
−
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STARVED_MC_POLARITY
+
| TSEC_BAR0_CTL_READ
 
|-
 
|-
 
| 1
 
| 1
−
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STARVED_MC_OPERATION
+
| TSEC_BAR0_CTL_WRITE
 
|-
 
|-
−
| 2
+
| 4-7
−
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STALLED_MC_POLARITY
+
| TSEC_BAR0_CTL_BYTE_MASK
 
|-
 
|-
−
| 3
+
| 12-13
−
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STALLED_MC_OPERATION
+
| TSEC_BAR0_CTL_STATUS
 +
0: Idle
 +
1: Busy
 +
2: Error
 +
3: Disabled
 
|-
 
|-
−
| 4
+
| 16-17
−
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_DELAYED_MC_POLARITY
+
| TSEC_BAR0_CTL_SEC_MODE
 +
0: Non-secure
 +
1: Invalid
 +
2: Light Secure
 +
3: Heavy Secure
 
|-
 
|-
−
| 5
+
| 31
−
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_DELAYED_MC_OPERATION
+
| TSEC_BAR0_CTL_INIT
 +
|}
 +
 
 +
Unofficial name.
 +
 
 +
Controls DMA transfers between TSEC and HOST1X (master and clients).
 +
 
 +
Starting a transfer over BAR0 automatically sets TSEC_BAR0_CTL_SEC_MODE to the current Falcon security mode. Once set, any attempts to start a transfer from a lower security level will fail.
 +
 
 +
=== TSEC_BAR0_ADDR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| 6
+
| 0-31
−
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE_POLARITY
+
| TSEC_BAR0_ADDR_VAL
−
|-
  −
| 7
  −
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE_OPERATION
   
|}
 
|}
   −
Takes the billions of records per second count for the Activity Monitor. Disconnected on the TSEC.
+
Unofficial name.
 +
 
 +
Takes the address for DMA transfers between TSEC and HOST1X (master and clients).
   −
=== TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT ===
+
=== TSEC_BAR0_DATA ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 4,724: Line 4,911:  
|-
 
|-
 
| 0-31
 
| 0-31
−
| TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT_VAL
+
| TSEC_BAR0_DATA_VAL
 
|}
 
|}
   −
Controls the Activity Monitor. Disconnected on the TSEC.
+
Unofficial name.
 +
 
 +
Takes the data for DMA transfers between TSEC and HOST1X (master and clients).
   −
=== TSEC_TFBIF_ACTMON_MCB_MASK ===
+
=== TSEC_BAR0_TIMEOUT ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-31
−
| TSEC_TFBIF_ACTMON_MCB_MASK_STARVED_MC
+
| TSEC_BAR0_TIMEOUT_VAL
−
|-
  −
| 1
  −
| TSEC_TFBIF_ACTMON_MCB_MASK_STALLED_MC
  −
|-
  −
| 2
  −
| TSEC_TFBIF_ACTMON_MCB_MASK_DELAYED_MC
  −
|-
  −
| 3
  −
| TSEC_TFBIF_ACTMON_MCB_MASK_ACTIVE
   
|}
 
|}
   −
Disconnected on the TSEC.
+
Unofficial name.
   −
=== TSEC_TFBIF_ACTMON_MCB_BORPS ===
+
Takes the timeout value for DMA transfers between TSEC and HOST1X (master and clients).
 +
 
 +
=== TSEC_VERSION ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-31
−
| TSEC_TFBIF_ACTMON_MCB_BORPS_STARVED_MC_POLARITY
+
| Version
 +
|}
 +
 
 +
Unofficial name.
 +
 
 +
=== TSEC_SCRATCH0 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| 1
+
| 0-31
−
| TSEC_TFBIF_ACTMON_MCB_BORPS_STARVED_MC_OPERATION
+
| Value
 +
|}
 +
 
 +
Unofficial name.
 +
 
 +
=== TSEC_SCRATCH1 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| 2
+
| 0-31
−
| TSEC_TFBIF_ACTMON_MCB_BORPS_STALLED_MC_POLARITY
+
| Value
−
|-
  −
| 3
  −
| TSEC_TFBIF_ACTMON_MCB_BORPS_STALLED_MC_OPERATION
  −
|-
  −
| 4
  −
| TSEC_TFBIF_ACTMON_MCB_BORPS_DELAYED_MC_POLARITY
  −
|-
  −
| 5
  −
| TSEC_TFBIF_ACTMON_MCB_BORPS_DELAYED_MC_OPERATION
  −
|-
  −
| 6
  −
| TSEC_TFBIF_ACTMON_MCB_BORPS_ACTIVE_POLARITY
  −
|-
  −
| 7
  −
| TSEC_TFBIF_ACTMON_MCB_BORPS_ACTIVE_OPERATION
   
|}
 
|}
   −
Disconnected on the TSEC.
+
Unofficial name.
   −
=== TSEC_TFBIF_ACTMON_MCB_WEIGHT ===
+
=== TSEC_SCRATCH2 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 4,787: Line 4,970:  
|-
 
|-
 
| 0-31
 
| 0-31
−
| TSEC_TFBIF_ACTMON_MCB_WEIGHT_VAL
+
| Value
 
|}
 
|}
   −
Disconnected on the TSEC.
+
Unofficial name.
   −
=== TSEC_TFBIF_THI_TRANSPROP ===
+
=== TSEC_SCRATCH3 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-6
+
| 0-31
−
| TSEC_TFBIF_THI_TRANSPROP_STREAMID0
+
| Value
−
|-
  −
| 8-14
  −
| TSEC_TFBIF_THI_TRANSPROP_STREAMID1
  −
|-
  −
| 16
  −
| TSEC_TFBIF_THI_TRANSPROP_TZ_AUTH
   
|}
 
|}
   −
=== TSEC_CG ===
+
Unofficial name.
 +
 
 +
=== TSEC_SCRATCH4 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-5
+
| 0-31
−
| TSEC_CG_IDLE_CG_DLY_CNT
+
| Value
−
|-
  −
| 6
  −
| TSEC_CG_IDLE_CG_EN
  −
|-
  −
| 16-18
  −
| TSEC_CG_WAKEUP_DLY_CNT
  −
|-
  −
| 19
  −
| TSEC_CG_WAKEUP_DLY_EN
   
|}
 
|}
   −
=== TSEC_BAR0_CTL ===
+
Unofficial name.
 +
 
 +
=== TSEC_SCRATCH5 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-31
−
| TSEC_BAR0_CTL_READ
+
| Value
 +
|}
 +
 
 +
Unofficial name.
 +
 
 +
=== TSEC_SCRATCH6 ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| 1
+
| 0-31
−
| TSEC_BAR0_CTL_WRITE
+
| Value
−
|-
  −
| 4-7
  −
| TSEC_BAR0_CTL_BYTE_MASK
  −
|-
  −
| 12-13
  −
| TSEC_BAR0_CTL_STATUS
  −
0: Idle
  −
1: Busy
  −
2: Error
  −
3: Disabled
  −
|-
  −
| 16-17
  −
| TSEC_BAR0_CTL_SEC_MODE
  −
0: Non-secure
  −
1: Invalid
  −
2: Light Secure
  −
3: Heavy Secure
  −
|-
  −
| 31
  −
| TSEC_BAR0_CTL_INIT
   
|}
 
|}
   −
Controls DMA transfers between TSEC and HOST1X (master and clients).
+
Unofficial name.
   −
Starting a transfer over BAR0 automatically sets TSEC_BAR0_CTL_SEC_MODE to the current Falcon security mode. Once set, any attempts to start a transfer from a lower security level will fail.
+
=== TSEC_SCRATCH7 ===
−
 
  −
=== TSEC_BAR0_ADDR ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 4,867: Line 5,025:  
|-
 
|-
 
| 0-31
 
| 0-31
−
| TSEC_BAR0_ADDR_VAL
+
| Value
 
|}
 
|}
   −
Takes the address for DMA transfers between TSEC and HOST1X (master and clients).
+
Unofficial name.
 +
 
 +
=== TSEC_GPTMRINT ===
 +
Unofficial name.
 +
 
 +
Same as [[#TSEC_FALCON_GPTMRINT|TSEC_FALCON_GPTMRINT]], but for an unknown hardware block.
 +
 
 +
=== TSEC_GPTMRVAL ===
 +
Unofficial name.
 +
 
 +
Same as [[#TSEC_FALCON_GPTMRVAL|TSEC_FALCON_GPTMRVAL]], but for an unknown hardware block.
 +
 
 +
=== TSEC_GPTMRCTL ===
 +
Unofficial name.
 +
 
 +
Same as [[#TSEC_FALCON_GPTMRCTL|TSEC_FALCON_GPTMRCTL]], but for an unknown hardware block.
   −
=== TSEC_BAR0_DATA ===
+
=== TSEC_ITFEN ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-31
+
| 0
−
| TSEC_BAR0_DATA_VAL
+
| Enable [[#TSEC_GPTMRINT|TSEC_GPTMRINT]]
 +
|-
 +
| 1
 +
| Unknown
 +
|-
 +
| 2
 +
| Unknown
 +
|-
 +
| 3
 +
| Unknown
 
|}
 
|}
   −
Takes the data for DMA transfers between TSEC and HOST1X (master and clients).
+
Unofficial name.
   −
=== TSEC_BAR0_TIMEOUT ===
+
=== TSEC_ITFSTAT ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-31
+
| 0
−
| TSEC_BAR0_TIMEOUT_VAL
+
| [[#TSEC_GPTMRINT|TSEC_GPTMRINT]] is enabled
 +
|-
 +
| 1
 +
| Unknown
 +
|-
 +
| 2
 +
| Unknown
 +
|-
 +
| 3
 +
| Unknown
 
|}
 
|}
   −
Takes the timeout value for DMA transfers between TSEC and HOST1X (master and clients).
+
Unofficial name.
    
=== TSEC_TEGRA_CTL ===
 
=== TSEC_TEGRA_CTL ===
Line 5,201: Line 5,392:  
| 2 || xsin || $cX || N/A || <code><nowiki>$cX = read_from_stream();</nowiki></code> || N/A || <code><nowiki>ACL($cX) = is_mode_hs ? 0x3 : 0x1F;</nowiki></code>
 
| 2 || xsin || $cX || N/A || <code><nowiki>$cX = read_from_stream();</nowiki></code> || N/A || <code><nowiki>ACL($cX) = is_mode_hs ? 0x3 : 0x1F;</nowiki></code>
 
|-
 
|-
−
| 3 || xsout || $cX || N/A || <code><nowiki>write_to_stream($cX);</nowiki></code> || <code><nowiki>(is_mode_hs && (ACL($cX) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0xA))</nowiki></code> || N/A
+
| 3 || xsout || $cX || N/A || <code><nowiki>write_to_stream($cX);</nowiki></code> || <code><nowiki>((is_mode_hs && (ACL($cX) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0xA)))</nowiki></code> || N/A
 
|-
 
|-
 
| 4 || [[#rnd|rnd]] || $cX || N/A || <code><nowiki>$cX = read_from_rnd();</nowiki></code> || N/A || <code><nowiki>ACL($cX) = is_mode_hs ? 0x3 : 0x1F;</nowiki></code>
 
| 4 || [[#rnd|rnd]] || $cX || N/A || <code><nowiki>$cX = read_from_rnd();</nowiki></code> || N/A || <code><nowiki>ACL($cX) = is_mode_hs ? 0x3 : 0x1F;</nowiki></code>
Line 5,217: Line 5,408:  
| 0xA || [[#chmod|chmod]] || $cX || immY || <code><nowiki>ACL($cX) = immY;</nowiki></code> || See [[#ACLs|ACLs]] || N/A
 
| 0xA || [[#chmod|chmod]] || $cX || immY || <code><nowiki>ACL($cX) = immY;</nowiki></code> || See [[#ACLs|ACLs]] || N/A
 
|-
 
|-
−
| 0xB || xor || $cX || $cY || <code><nowiki>$cX ^= $cY;</nowiki></code> || <code><nowiki>(is_mode_hs && (ACL($cX) & 0x2) && (ACL($cY) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0x1A) && (ACL($cY) & 0xA))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
+
| 0xB || xor || $cX || $cY || <code><nowiki>$cX ^= $cY;</nowiki></code> || <code><nowiki>((is_mode_hs && (ACL($cX) & 0x2) && (ACL($cY) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0x1A) && (ACL($cY) & 0xA)))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
 
|-
 
|-
−
| 0xC || add || $cX || immY || <code><nowiki>$cX += immY;</nowiki></code> || <code><nowiki>(is_mode_hs && (ACL($cX) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0x1A))</nowiki></code> || N/A
+
| 0xC || add || $cX || immY || <code><nowiki>$cX += immY;</nowiki></code> || <code><nowiki>((is_mode_hs && (ACL($cX) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0x1A)))</nowiki></code> || N/A
 
|-
 
|-
−
| 0xD || and || $cX || $cY || <code><nowiki>$cX &= $cY;</nowiki></code> || <code><nowiki>(is_mode_hs && (ACL($cX) & 0x2) && (ACL($cY) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0x1A) && (ACL($cY) & 0xA))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
+
| 0xD || and || $cX || $cY || <code><nowiki>$cX &= $cY;</nowiki></code> || <code><nowiki>((is_mode_hs && (ACL($cX) & 0x2) && (ACL($cY) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0x1A) && (ACL($cY) & 0xA)))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
 
|-
 
|-
−
| 0xE || rev || $cX || $cY || <code><nowiki>$cX = endian_swap128($cY);</nowiki></code> || <code><nowiki>(!is_mode_hs && (ACL($cX) & 0x10))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
+
| 0xE || rev || $cX || $cY || <code><nowiki>$cX = endian_swap128($cY);</nowiki></code> || <code><nowiki>(is_mode_hs || (!is_mode_hs && (ACL($cX) & 0x10)))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
 
|-
 
|-
−
| 0xF || gfmul || $cX || $cY || <code><nowiki>$cX = gfmul($cY);</nowiki></code>|| <code><nowiki>(is_mode_hs && (ACL($cX) & 0x2) && (ACL($cY) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0x1A) && (ACL($cY) & 0xA))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
+
| 0xF || gfmul || $cX || $cY || <code><nowiki>$cX = gfmul($cY);</nowiki></code>|| <code><nowiki>((is_mode_hs && (ACL($cX) & 0x2) && (ACL($cY) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0x1A) && (ACL($cY) & 0xA)))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
 
|-
 
|-
 
| 0x10 || secret || $cX || immY || <code><nowiki>$cX = load_secret(immY);</nowiki></code> || N/A || <code><nowiki>ACL($cX) = load_secret_acl(immY);</nowiki></code>
 
| 0x10 || secret || $cX || immY || <code><nowiki>$cX = load_secret(immY);</nowiki></code> || N/A || <code><nowiki>ACL($cX) = load_secret_acl(immY);</nowiki></code>
Line 5,231: Line 5,422:  
| 0x11 || keyreg || $cX || N/A || <code><nowiki>active_key = $cX;</nowiki></code> || N/A || N/A
 
| 0x11 || keyreg || $cX || N/A || <code><nowiki>active_key = $cX;</nowiki></code> || N/A || N/A
 
|-
 
|-
−
| 0x12 || kexp || $cX || $cY || <code><nowiki>$cX = aes_key_expand($cY);</nowiki></code> || <code><nowiki>(!is_mode_hs && (ACL($cX) & 0x10))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
+
| 0x12 || kexp || $cX || $cY || <code><nowiki>$cX = aes_key_expand($cY);</nowiki></code> || <code><nowiki>(is_mode_hs || (!is_mode_hs && (ACL($cX) & 0x10)))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
 
|-
 
|-
−
| 0x13 || krexp || $cX || $cY || <code><nowiki>$cX = aes_key_reverse_expand($cY);</nowiki></code> || <code><nowiki>(!is_mode_hs && (ACL($cX) & 0x10))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
+
| 0x13 || krexp || $cX || $cY || <code><nowiki>$cX = aes_key_reverse_expand($cY);</nowiki></code> || <code><nowiki>(is_mode_hs || (!is_mode_hs && (ACL($cX) & 0x10)))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
 
|-
 
|-
 
| 0x14 || enc || $cX || $cY || <code><nowiki>$cX = aes_enc(active_key, $cY);</nowiki></code> || N/A || <code><nowiki>ACL($cX) = (ACL(active_key) & ACL($cY));</nowiki></code>
 
| 0x14 || enc || $cX || $cY || <code><nowiki>$cX = aes_enc(active_key, $cY);</nowiki></code> || N/A || <code><nowiki>ACL($cX) = (ACL(active_key) & ACL($cY));</nowiki></code>
Line 5,239: Line 5,430:  
| 0x15 || dec || $cX || $cY || <code><nowiki>$cX = aes_dec(active_key, $cY);</nowiki></code> || N/A || <code><nowiki>ACL($cX) = (ACL(active_key) & ACL($cY));</nowiki></code>
 
| 0x15 || dec || $cX || $cY || <code><nowiki>$cX = aes_dec(active_key, $cY);</nowiki></code> || N/A || <code><nowiki>ACL($cX) = (ACL(active_key) & ACL($cY));</nowiki></code>
 
|-
 
|-
−
| 0x16 || [[#sigcmp|sigcmp]] || $cX || $cY || <code><nowiki>current_sig = memcmp($cX, $cY) ? NULL : $cX;</nowiki></code> || <code><nowiki>is_secure_bootrom</nowiki></code> || <code><nowiki>has_sig = true; is_mode_hs = true;</nowiki></code>
+
| 0x16 || [[#sigcmp|sigcmp]] || $cX || $cY || <code><nowiki>current_sig = memcmp($cX, $cY) ? NULL : $cX;</nowiki></code> || <code><nowiki>(is_mode_secure_bootrom && (ACL($cY) & 0x2))</nowiki></code> || <code><nowiki>is_mode_hs = has_sig = (current_sig != NULL);</nowiki></code>
 
|-
 
|-
−
| 0x17 || sigenc || $cX || $cY || <code><nowiki>$cX = aes_enc($cY, current_sig);</nowiki></code> || <code><nowiki>has_sig</nowiki></code> || <code><nowiki>ACL($cX) = 0x3;</nowiki></code>
+
| 0x17 || sigenc || $cX || $cY || <code><nowiki>$cX = aes_enc($cY, current_sig);</nowiki></code> || <code><nowiki>(is_mode_hs && has_sig)</nowiki></code> || <code><nowiki>ACL($cX) = 0x3;</nowiki></code>
 
|-
 
|-
−
| 0x18 || [[#sigclr|sigclr]] || N/A || N/A || <code><nowiki>current_sig = NULL;</nowiki></code> || <code><nowiki>has_sig</nowiki></code> || <code><nowiki>has_sig = false;</nowiki></code>
+
| 0x18 || [[#sigclr|sigclr]] || N/A || N/A || <code><nowiki>current_sig = NULL;</nowiki></code> || <code><nowiki>(is_mode_hs && has_sig)</nowiki></code> || <code><nowiki>has_sig = false;</nowiki></code>
 
|}
 
|}
  
Retrieved from "https://switchbrew.org/wiki/Special:MobileDiff/10923...11886"