TSEC: Difference between revisions
No edit summary |
No edit summary |
||
| (One intermediate revision by the same user not shown) | |||
| Line 11: | Line 11: | ||
* 0x54501500 to 0x54501600: TRNG (True Random Number Generator). | * 0x54501500 to 0x54501600: TRNG (True Random Number Generator). | ||
* 0x54501600 to 0x54501700: TFBIF (Tegra Framebuffer Interface) and CG (Clock Gate). | * 0x54501600 to 0x54501700: TFBIF (Tegra Framebuffer Interface) and CG (Clock Gate). | ||
* 0x54501700 to 0x54501800: | * 0x54501700 to 0x54501800: BAR0. | ||
* 0x54501800 to 0x54501900: TEGRA (miscellaneous interfaces). | * 0x54501800 to 0x54501900: TEGRA (miscellaneous interfaces). | ||
| Line 367: | Line 367: | ||
| 0x04 | | 0x04 | ||
|- | |- | ||
| | | FALCON_CMEMBASE | ||
| 0x54501160 | | 0x54501160 | ||
| 0x04 | | 0x04 | ||
|- | |- | ||
| | | FALCON_DMEMAPERT | ||
| 0x54501164 | | 0x54501164 | ||
| 0x04 | | 0x04 | ||
| Line 739: | Line 739: | ||
| 0x04 | | 0x04 | ||
|- | |- | ||
| [[# | | [[#TSEC_BAR0_CTL|TSEC_BAR0_CTL]] | ||
| 0x54501700 | | 0x54501700 | ||
| 0x04 | | 0x04 | ||
|- | |- | ||
| [[# | | [[#TSEC_BAR0_ADDR|TSEC_BAR0_ADDR]] | ||
| 0x54501704 | | 0x54501704 | ||
| 0x04 | | 0x04 | ||
|- | |- | ||
| [[# | | [[#TSEC_BAR0_DATA|TSEC_BAR0_DATA]] | ||
| 0x54501708 | | 0x54501708 | ||
| 0x04 | | 0x04 | ||
|- | |- | ||
| [[# | | [[#TSEC_BAR0_TIMEOUT|TSEC_BAR0_TIMEOUT]] | ||
| 0x5450170C | | 0x5450170C | ||
| 0x04 | | 0x04 | ||
| Line 1,109: | Line 1,109: | ||
|- | |- | ||
| 0 | | 0 | ||
| | | FALCON_IRQMODE_LVL_GPTMR | ||
|- | |- | ||
| 1 | | 1 | ||
| | | FALCON_IRQMODE_LVL_WDTMR | ||
|- | |- | ||
| 2 | | 2 | ||
| | | FALCON_IRQMODE_LVL_MTHD | ||
|- | |- | ||
| 3 | | 3 | ||
| | | FALCON_IRQMODE_LVL_CTXSW | ||
|- | |- | ||
| 4 | | 4 | ||
| | | FALCON_IRQMODE_LVL_HALT | ||
|- | |- | ||
| 5 | | 5 | ||
| | | FALCON_IRQMODE_LVL_EXTERR | ||
|- | |- | ||
| 6 | | 6 | ||
| | | FALCON_IRQMODE_LVL_SWGEN0 | ||
|- | |- | ||
| 7 | | 7 | ||
| | | FALCON_IRQMODE_LVL_SWGEN1 | ||
|- | |- | ||
| 8-15 | | 8-15 | ||
| | | FALCON_IRQMODE_LVL_EXT | ||
|} | |} | ||
| Line 2,701: | Line 2,701: | ||
|} | |} | ||
=== | === TSEC_BAR0_CTL === | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! Bits | ! Bits | ||
| Line 2,707: | Line 2,707: | ||
|- | |- | ||
| 0 | | 0 | ||
| | | TSEC_BAR0_CTL_READ | ||
|- | |- | ||
| 1 | | 1 | ||
| | | TSEC_BAR0_CTL_WRITE | ||
|- | |- | ||
| 4-7 | | 4-7 | ||
| | | TSEC_BAR0_CTL_BYTE_MASK | ||
|- | |- | ||
| 12-13 | | 12-13 | ||
| | | TSEC_BAR0_CTL_STATUS | ||
0: Idle | 0: Idle | ||
1: Busy | 1: Busy | ||
| Line 2,723: | Line 2,723: | ||
|- | |- | ||
| 31 | | 31 | ||
| | | TSEC_BAR0_CTL_INIT | ||
|} | |} | ||
A DMA read/write operation requires bits | A BAR0 DMA read/write operation requires bits TSEC_BAR0_CTL_INIT and TSEC_BAR0_CTL_READ/TSEC_BAR0_CTL_WRITE to be set in TSEC_BAR0_CTL. | ||
During the transfer, | During the transfer, TSEC_BAR0_CTL_STATUS is set to "Busy". | ||
Accessing an invalid address sets | Accessing an invalid address sets TSEC_BAR0_CTL_STATUS to "Error". | ||
=== | === TSEC_BAR0_ADDR === | ||
Takes the address for DMA transfers between TSEC and HOST1X (master and clients). | Takes the address for DMA transfers between TSEC and HOST1X (master and clients). | ||
=== | === TSEC_BAR0_DATA === | ||
Takes the data for DMA transfers between TSEC and HOST1X (master and clients). | Takes the data for DMA transfers between TSEC and HOST1X (master and clients). | ||
=== | === TSEC_BAR0_TIMEOUT === | ||
Takes the timeout value for DMA transfers between TSEC and HOST1X (master and clients). | |||
=== TSEC_TEGRA_CTL === | === TSEC_TEGRA_CTL === | ||