Changes

2,609 bytes added ,  18:04, 10 October 2019
Line 1,060: Line 1,060:  
| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
 
| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
 
|-
 
|-
| 0xC0184706 || Inout || 24 || NVGPU_GPU_IOCTL_GET_TPC_MASKS
+
| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]]
 
|-
 
|-
 
| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]]
 
| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]]
 
|-
 
|-
| 0x4008470D || In || 8 || NVGPU_GPU_IOCTL_INVAL_ICACHE
+
| 0x4008470D || In || 8 || [[#NVGPU_GPU_IOCTL_INVAL_ICACHE]]
 
|-
 
|-
| 0x4008470E || In || 8 || NVGPU_GPU_IOCTL_SET_MMUDEBUG_MODE
+
| 0x4008470E || In || 8 || [[#NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE]]
 
|-
 
|-
| 0x4010470F || In || 16 || NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE
+
| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]
 
|-
 
|-
 
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE
 
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE
Line 1,191: Line 1,191:  
     __in    u64 gpu_characteristics_buf_addr;  // ignored, but must not be NULL
 
     __in    u64 gpu_characteristics_buf_addr;  // ignored, but must not be NULL
 
     __out struct gpu_characteristics gc;
 
     __out struct gpu_characteristics gc;
 +
  };
 +
 +
=== NVGPU_GPU_IOCTL_GET_TPC_MASKS ===
 +
Returns the TPC mask value for each GPC. Modified to return inline data instead of using a pointer.
 +
 +
  struct {
 +
    __in u32 mask_buf_size;      // ignored, but must not be NULL
 +
    __in u32 reserved[3];
 +
    __out u64 mask_buf;          // receives one 32-bit TPC mask per GPC (GPC 0 and GPC 1)
 
   };
 
   };
   Line 1,198: Line 1,207:  
   struct {
 
   struct {
 
     __in u32 flush;          // l2_flush | l2_invalidate << 1 | fb_flush << 2
 
     __in u32 flush;          // l2_flush | l2_invalidate << 1 | fb_flush << 2
     u32     reserved;
+
     __in u32 reserved;
 +
  };
 +
 
 +
=== NVGPU_GPU_IOCTL_INVAL_ICACHE ===
 +
Invalidates the GPU instruction cache. Identical to Linux driver.
 +
 
 +
  struct {
 +
    __in s32 channel_fd;
 +
    __in u32 reserved;
 +
  };
 +
 
 +
=== NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE ===
 +
Sets the GPU MMU debug mode. Identical to Linux driver.
 +
 
 +
  struct {
 +
    __in u32 state;
 +
    __in u32 reserved;
 +
  };
 +
 
 +
=== NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE ===
 +
Sets the GPU SM debug mode. Identical to Linux driver.
 +
 
 +
  struct {
 +
    __in s32 channel_fd;
 +
    __in u32 enable;
 +
    __in u64 sms;
 
   };
 
   };
   Line 1,260: Line 1,294:  
| 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
 
| 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
 
|-
 
|-
| 0x40044803 || 4 || NVGPU_IOCTL_CHANNEL_SET_TIMEOUT
+
| 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
 
|-
 
|-
 
| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
 
| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
 
|-
 
|-
| 0x40184806 || || NVGPU_IOCTL_CHANNEL_WAIT
+
| 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
 
|-
 
|-
| 0xC0044807 || 4 || NVGPU_IOCTL_CHANNEL_CYCLE_STATS
+
| 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
 
|-
 
|-
 
| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
 
| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
Line 1,272: Line 1,306:  
| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
 
| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
 
|-
 
|-
| 0x4008480A || || NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX
+
| 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
 
|-
 
|-
 
| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
 
| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
Line 1,290: Line 1,324:  
| 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
 
| 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
 
|-
 
|-
| 0xC0104813 || 16 || NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT
+
| 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
 
|-
 
|-
| 0x80804816 || 128 || NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO
+
| 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
 
|-
 
|-
 
| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
 
| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
Line 1,308: Line 1,342:  
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
 
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
 
|- style="border-top: double"
 
|- style="border-top: double"
| 0x40084714 || 8 || NVGPU_IOCTL_CHANNEL_SET_USER_DATA
+
| 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
 
|-
 
|-
| 0x80084715 || 8 || NVGPU_IOCTL_CHANNEL_GET_USER_DATA
+
| 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
 
|}
 
|}
   Line 1,406: Line 1,440:  
   struct {
 
   struct {
 
     __in u32 nvmap_fd;
 
     __in u32 nvmap_fd;
 +
  };
 +
 +
=== NVGPU_IOCTL_CHANNEL_SET_TIMEOUT ===
 +
Sets the timeout value for the GPU channel. Identical to Linux driver.
 +
 +
  struct {
 +
    __in u32 timeout;
 
   };
 
   };
   Line 1,414: Line 1,455:  
     __in u32 num_entries;
 
     __in u32 num_entries;
 
     __in u32 flags;
 
     __in u32 flags;
 +
  };
 +
 +
=== NVGPU_IOCTL_CHANNEL_WAIT ===
 +
Waits on channel. Identical to Linux driver.
 +
 +
  struct {
 +
    __in u32 type;            // wait type (0=notifier, 1=semaphore)
 +
    __in u32 timeout;        // wait timeout value
 +
    __in u32 dmabuf_fd;      // nvmap handle
 +
    __in u32 offset;          // nvmap memory offset
 +
    __in u32 payload;        // payload data (semaphore only)
 +
    __in u32 padding;        // ignored
 +
  };
 +
 +
=== NVGPU_IOCTL_CHANNEL_CYCLE_STATS ===
 +
Maps memory for the cycle stats buffer. Identical to Linux driver.
 +
 +
  struct {
 +
    __in u32 dmabuf_fd;  // nvmap handle
 
   };
 
   };
   Line 1,445: Line 1,505:  
     __in  u32 flags;        // bit0: LOCKBOOST_ZERO
 
     __in  u32 flags;        // bit0: LOCKBOOST_ZERO
 
     __out u64 obj_id;      // (ignored) used for FREE_OBJ_CTX ioctl, which is not supported
 
     __out u64 obj_id;      // (ignored) used for FREE_OBJ_CTX ioctl, which is not supported
 +
  };
 +
 +
=== NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX ===
 +
Frees a graphics context object. Not supported.
 +
 +
  struct {
 +
    __in u64 obj_id;      // ignored
 
   };
 
   };
   Line 1,491: Line 1,558:  
     __in u32 cmd;    // 0=disable, 1=enable, 2=clear
 
     __in u32 cmd;    // 0=disable, 1=enable, 2=clear
 
     __in u32 id;    // same id's as for [[#QueryEvent]]
 
     __in u32 id;    // same id's as for [[#QueryEvent]]
 +
  };
 +
 +
=== NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT ===
 +
Controls the cycle stats snapshot buffer. Identical to Linux driver.
 +
 +
  struct {
 +
    __in    u32 cmd;        // command to handle (0=flush, 1=attach, 2=detach)
 +
    __in    u32 dmabuf_fd;  // nvmap handle
 +
    __inout u32 extra;      // extra payload data/result
 +
    __in    u32 padding;    // ignored
 +
  };
 +
 +
=== NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO ===
 +
Returns information on the current error notification caught by the error notifier. Exclusive to the Switch.
 +
 +
  struct {
 +
    __out u32 error_info[32];    // first word is an error code (0=no_error, 1=gr_error, 2=gr_error, 3=invalid, 4=invalid)
 
   };
 
   };
    
=== NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION ===
 
=== NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION ===
 
Returns the current error notification caught by the error notifier. Exclusive to the Switch.
 
Returns the current error notification caught by the error notifier. Exclusive to the Switch.
  −
Despite being marked as inout this is all output.
      
   struct {
 
   struct {
Line 1,538: Line 1,620:  
   struct {
 
   struct {
 
     __in u32 timeslice;
 
     __in u32 timeslice;
 +
  };
 +
 +
=== NVGPU_IOCTL_CHANNEL_SET_USER_DATA ===
 +
Sets user specific data.
 +
 +
  struct {
 +
    __in u64 data;
 +
  };
 +
 +
=== NVGPU_IOCTL_CHANNEL_GET_USER_DATA ===
 +
Gets user specific data.
 +
 +
  struct {
 +
    __out u64 data;
 
   };
 
   };