Changes

346 bytes added ,  22:15, 10 September 2019
Line 62: Line 62:  
* CPU Suspend SMC code now explicitly initializes the state of I2C5 before communicating with the PMIC, instead of assuming that it is in a valid state.
 
* CPU Suspend SMC code now explicitly initializes the state of I2C5 before communicating with the PMIC, instead of assuming that it is in a valid state.
 
* Code for initializing MMIO inside package2ldr now writes random values to a number of PMC secure scratch registers, and validates that the written values are read back successfully before locking the scratch.
 
* Code for initializing MMIO inside package2ldr now writes random values to a number of PMC secure scratch registers, and validates that the written values are read back successfully before locking the scratch.
** TODO: Check back later for information on what these scratch do.
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** This writes to secscratch 4-7 (used to store SRK), then locks them.
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*** The SE will overwrite these values during context save despite the lock.
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** This then writes to secscratch 112-115 and 24-25, used by TZ during context save to store a MAC and a key source, respectively.
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*** These too will be overwritten during context save, as the scratch are not locked.
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** secscratch 4-7 are then locked a second time.
    
====KernelLdr====
 
====KernelLdr====