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307 bytes added ,  19:35, 16 February 2020
Line 208: Line 208:  
| 2 || [[#DramId]]
 
| 2 || [[#DramId]]
 
|-
 
|-
| 3 || [[#SecurityEngineIrqNumber]]
+
| 3 || [[#SecurityEngineInterruptNumber]]
 
|-
 
|-
| 4 || [[#Version]]
+
| 4 || [[#FuseVersion]]
 
|-
 
|-
 
| 5 || [[#HardwareType]]
 
| 5 || [[#HardwareType]]
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| 13 || [[#IsChargerHiZModeEnabled]]
 
| 13 || [[#IsChargerHiZModeEnabled]]
 
|-
 
|-
| 14 || [4.0.0+] [[#IsKiosk]]
+
| 14 || [4.0.0+] [[#IsQuest]]
 
|-
 
|-
 
| 15 || [5.0.0+] [[#RegulatorType]]
 
| 15 || [5.0.0+] [[#RegulatorType]]
 
|-
 
|-
| 16 || [5.0.0+] [[#KeyGeneration]]
+
| 16 || [5.0.0+] [[#DeviceUniqueKeyGeneration]]
 
|-
 
|-
 
| 17 || [5.0.0+] [[#Package2Hash]]
 
| 17 || [5.0.0+] [[#Package2Hash]]
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'''Erista''' memory is LPDDR4, while '''Mariko''' memory is LPDDR4X.
 
'''Erista''' memory is LPDDR4, while '''Mariko''' memory is LPDDR4X.
   −
===== SecurityEngineIrqNumber =====
+
===== SecurityEngineInterruptNumber =====
 
SPL uses this for setting up the security engine IRQ.
 
SPL uses this for setting up the security engine IRQ.
   −
===== Version =====
+
===== FuseVersion =====
 
The current [[Package2#Versions|Package1 Maxver Constant]] - 1.
 
The current [[Package2#Versions|Package1 Maxver Constant]] - 1.
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[3.0.0+] [[Loader services|RO]] checks this and if set then skipping NRR rsa signatures is allowed.
 
[3.0.0+] [[Loader services|RO]] checks this and if set then skipping NRR rsa signatures is allowed.
   −
The value of this field is loaded from [[BootConfig]] unsigned-config+0x10 u8 bit1.
+
===== KernelConfiguration =====
 +
{| class="wikitable" border="1"
 +
|-
 +
! Bits
 +
! Description
 +
|-
 +
| 0
 +
| EnableNonZeroFillMemory
 +
|-
 +
| 1
 +
| EnableUserExceptionHandler
 +
|-
 +
| 2
 +
| PerformanceMonitoringUnit
 +
|-
 +
| 3
 +
| [8.0.0+] EnableApplicationExtraThread
 +
|-
 +
| 8
 +
| CallShowErrorOnPanic
 +
|-
 +
| 16-17
 +
| MemorySize
 +
|}
   −
===== KernelConfiguration =====
+
Kernel reads this when setting up memory-related code.
Kernel reads this when setting up memory-related code.  
     −
Bit 0 is a boolean determining whether kernel should it will memset various allocated memory-regions with 0x58, 0x59, 0x5A ('X', 'Y', 'Z') instead of zero. This allows Nintendo devs to find uninitialized memory bugs.
+
EnableNonZeroFillMemory is a boolean determining whether kernel should it will memset various allocated memory-regions with 0x58, 0x59, 0x5A ('X', 'Y', 'Z') instead of zero. This allows Nintendo devs to find uninitialized memory bugs.
   −
Bit 1 is a boolean determining whether kernel should forcefully enable usermode exception handlers (when false, only certain aborts (((1LL << (esr >> 26)) & 0x1115804400224001) == 0, typically data/prefetch aborts) that occur when the faulting address is in a readable region with MemoryType_CodeStatic will trigger usermode exception handlers).
+
EnableUserExceptionHandler is a boolean determining whether kernel should forcefully enable usermode exception handlers (when false, only certain aborts (((1LL << (esr >> 26)) & 0x1115804400224001) == 0, typically data/prefetch aborts) that occur when the faulting address is in a readable region with MemoryType_CodeStatic will trigger usermode exception handlers).
   −
Bit 2 is a boolean determining whether kernel should enable usermode access to the Performance Monitors (whether PMUSERENR_EL0 should be 1 or 0).
+
PerformanceMonitoringUnit is a boolean determining whether kernel should enable usermode access to the Performance Monitors (whether PMUSERENR_EL0 should be 1 or 0).
   −
[8.0.0+] Bit 3 is a boolean determining whether the kernel should increase the KThread slabheap capacity by 160. This also increases object capacities that are calculated based on number of threads.
+
EnableApplicationExtraThread is a boolean determining whether the kernel should increase the KThread slabheap capacity by 160. This also increases object capacities that are calculated based on number of threads.
   −
Bits 8-15 are a boolean determining whether kernel should call smcPanic on error instead of infinite-looping.
+
CallShowErrorOnPanic is a boolean determining whether kernel should call smcPanic on error instead of infinite-looping.
   −
Bits 16-17 determine how much memory is available. 00/03 = 4 GB, 01 = 6 GB, 02 = 8 GB.
+
MemorySize determines how much memory is available. 00/03 = 4 GB, 01 = 6 GB, 02 = 8 GB.
    
===== IsChargerHiZModeEnabled =====
 
===== IsChargerHiZModeEnabled =====
 
This tells if the TI Charger (bq24192) is active.
 
This tells if the TI Charger (bq24192) is active.
   −
===== IsKiosk =====
+
===== IsQuest =====
 
This item is bit 10 from [[Fuse_registers#FUSE_RESERVED_ODM4|FUSE_RESERVED_ODM4]].
 
This item is bit 10 from [[Fuse_registers#FUSE_RESERVED_ODM4|FUSE_RESERVED_ODM4]].
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[5.0.0+] [[PCV_services|PCV]] uses this value in combination with [[#HardwareType|HardwareType]] to configure power blocks and memory tables for different hardware.
 
[5.0.0+] [[PCV_services|PCV]] uses this value in combination with [[#HardwareType|HardwareType]] to configure power blocks and memory tables for different hardware.
   −
===== KeyGeneration =====
+
===== DeviceUniqueKeyGeneration =====
 
This item is obtained from [[Fuse_registers#FUSE_RESERVED_ODM2|FUSE_RESERVED_ODM2]] if bit 11 from [[Fuse_registers#FUSE_RESERVED_ODM4|FUSE_RESERVED_ODM4]] is set, [[Fuse_registers#FUSE_RESERVED_ODM0|FUSE_RESERVED_ODM0]] matches 0x8E61ECAE and [[Fuse_registers#FUSE_RESERVED_ODM1|FUSE_RESERVED_ODM1]] matches 0xF2BA3BB2.
 
This item is obtained from [[Fuse_registers#FUSE_RESERVED_ODM2|FUSE_RESERVED_ODM2]] if bit 11 from [[Fuse_registers#FUSE_RESERVED_ODM4|FUSE_RESERVED_ODM4]] is set, [[Fuse_registers#FUSE_RESERVED_ODM0|FUSE_RESERVED_ODM0]] matches 0x8E61ECAE and [[Fuse_registers#FUSE_RESERVED_ODM1|FUSE_RESERVED_ODM1]] matches 0xF2BA3BB2.
  

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