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525 bytes added ,  16:54, 25 August 2019
Add 32-bit ABI for svc*ProcessMemory
Line 281: Line 281:  
| 0x72 || svcConnectToPort || W1=clientport_handle || W0=result, W1=session_handle
 
| 0x72 || svcConnectToPort || W1=clientport_handle || W0=result, W1=session_handle
 
|-
 
|-
| 0x73 || [[#svcSetProcessMemoryPermission]] || W0=process_handle, X1=addr, X2=size, W3=perm || W0=result
+
| 0x73 || [[#svcSetProcessMemoryPermission]] || W0=process_handle, X1=addr, X2=size, W3=perm
 +
R0=process_handle, R1=size_lower32, R2=addr_lower32, R3=addr_upper32, R4=size_upper32, R5=perm
 +
|| W0=result
 
|-
 
|-
| 0x74 || [[#svcMapProcessMemory]] || X0=dstaddr, W1=process_handle, X2=srcaddr, X3=size || W0=result
+
| 0x74 || [[#svcMapProcessMemory]] || X0=dstaddr, W1=process_handle, X2=srcaddr, X3=size
 +
R0=dstaddr, R1=process_handle, R2=srcaddr_lower32, R3=srcaddr_upper32, R4=size
 +
|| W0=result
 
|-
 
|-
| 0x75 || [[#svcUnmapProcessMemory]] || X0=dstaddr, W1=process_handle, X2=srcaddr, X3=size || W0=result
+
| 0x75 || [[#svcUnmapProcessMemory]] || X0=dstaddr, W1=process_handle, X2=srcaddr, X3=size
 +
R0=dstaddr, R1=process_handle, R2=srcaddr_lower32, R3=srcaddr_upper32, R4=size
 +
|| W0=result
 
|-
 
|-
| 0x76 || [[#svcQueryProcessMemory]] || X0=meminfo_ptr, W2=process_handle, X3=addr || W0=result, W1=pageinfo
+
| 0x76 || [[#svcQueryProcessMemory]] || X0=meminfo_ptr, W2=process_handle, X3=addr
 +
R0=meminfo_ptr, R1=addr_lower32, R2=process_handle, R3=addr_upper32
 +
|| W0=result, W1=pageinfo
 
|-
 
|-
 
| 0x77 || [[#svcMapProcessCodeMemory]] || W0=process_handle, X1=dstaddr, X2=srcaddr, X3=size || W0=result
 
| 0x77 || [[#svcMapProcessCodeMemory]] || W0=process_handle, X1=dstaddr, X2=srcaddr, X3=size || W0=result
Line 1,427: Line 1,435:  
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
|-
 
|-
! Argument || Type || Name
+
! Argument64 || Argument32 || Type || Name
 
|-
 
|-
| (In) W0 || Handle<Process> || ProcessHandle
+
| (In) W0 || R0 || Handle<Process> || ProcessHandle
 
|-
 
|-
| (In) X1 || u64 || Addr
+
| (In) X1 || R2, R3 || u64 || Addr
 
|-
 
|-
| (In) X2 || u64 || Size
+
| (In) X2 || R1, R4 || u64 || Size
 
|-
 
|-
| (In) W3 || void* || Perm
+
| (In) W3 || R5 || void* || Perm
 
|-
 
|-
| (Out) W0 || [[#Result]] || Ret
+
| (Out) W0 || R0 || [[#Result]] || Ret
 
|}
 
|}
 
</div>
 
</div>
Line 1,450: Line 1,458:  
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
|-
 
|-
! Argument || Type || Name
+
! Argument64 || Argument32 || Type || Name
 
|-
 
|-
| (In) X0 || u64 || DstAddr
+
| (In) X0 || R0 || u64 || DstAddr
 
|-
 
|-
| (In) W1 || Handle<Process> || ProcessHandle
+
| (In) W1 || R1 || Handle<Process> || ProcessHandle
 
|-
 
|-
| (In) X2 || void* || SrcAddr
+
| (In) X2 || R2, R3 || void* || SrcAddr
 
|-
 
|-
| (In) X3 || u64 || Size
+
| (In) X3 || R4 || u64 || Size
 
|-
 
|-
| (Out) W0 || [[#Result]] || Ret
+
| (Out) W0 || R0 || [[#Result]] || Ret
 
|}
 
|}
 
</div>
 
</div>
Line 1,473: Line 1,481:  
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
|-
 
|-
! Argument || Type || Name
+
! Argument64 || Argument32 || Type || Name
 
|-
 
|-
| (In) X0 || void* || DstAddr
+
| (In) X0 || R0 || void* || DstAddr
 
|-
 
|-
| (In) W1 || Handle<Process> || ProcessHandle
+
| (In) W1 || R1 || Handle<Process> || ProcessHandle
 
|-
 
|-
| (In) X2 || u64 || SrcAddr
+
| (In) X2 || R2, R3 || u64 || SrcAddr
 
|-
 
|-
| (In) X3 || u64 || Size
+
| (In) X3 || R4 || u64 || Size
 
|-
 
|-
| (Out) W0 || [[#Result]] || Ret
+
| (Out) W0 || R0 || [[#Result]] || Ret
 
|}
 
|}
 
</div>
 
</div>
Line 1,494: Line 1,502:  
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
|-
 
|-
! Argument || Type || Name
+
! Argument64 || Argument32 || Type || Name
 
|-
 
|-
| (In) X0 || [[#MemoryInfo]]* || MemInfoPtr
+
| (In) X0 || R0 || [[#MemoryInfo]]* || MemInfoPtr
 
|-
 
|-
| (In) W2 || Handle<Process> || ProcessHandle
+
| (In) W2 || R2 || Handle<Process> || ProcessHandle
 
|-
 
|-
| (In) X3 || u64 || Addr
+
| (In) X3 || R1, R3 || u64 || Addr
 
|-
 
|-
| (Out) W0 || [[#Result]] || Ret
+
| (Out) W0 || R0 || [[#Result]] || Ret
 
|-
 
|-
| (Out) W1 || PageInfo || PageInfo
+
| (Out) W1 || R1 || PageInfo || PageInfo
 
|}
 
|}
 
</div>
 
</div>
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