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NV services: Difference between revisions

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Each service is used by:
Each service is used by:
* "nvdrv": regular applications
* "nvdrv": Applications.
* "nvdrv:a": applets
** [[#Permissions|Permission]] mask is [3.0.0+] 0xA82B ([1.0.0-2.3.0] 0x2B).
* "nvdrv:s": sysmodules
* "nvdrv:a": Applets.
* "nvdrv:t": factory titles
** [[#Permissions|Permission]] mask is [3.0.0+] 0x10A9 ([1.0.0-2.3.0] 0xA9).
* "nvdrv:s": Sysmodules.
** [[#Permissions|Permission]] mask is [3.0.0+] 0x439E ([1.0.0-2.3.0] 0x39E).
* "nvdrv:t": Factory.
** [[#Permissions|Permission]] mask is 0xFFFFFFFF.


{| class="wikitable" border="1"
{| class="wikitable" border="1"
Line 30: Line 34:
| 6 || [[#GetStatus]]
| 6 || [[#GetStatus]]
|-
|-
| 7 || [[#SetAruid]]
| 7 || [[#SetAruidForTest]]
|-
|-
| 8 || [[#SetAruidByPID]]
| 8 || [[#SetAruid]]
|-
|-
| 9 || [[#DumpGraphicsMemoryInfo]]
| 9 || [[#DumpGraphicsMemoryInfo]]
Line 42: Line 46:
| 12 || [3.0.0+] [[#Ioctl3]]
| 12 || [3.0.0+] [[#Ioctl3]]
|-
|-
| 13 || [3.0.0+] [[#FinishInitialize]]
| 13 || [3.0.0+] [[#SetGraphicsFirmwareMemoryMarginEnabled]]
|}
|}


Line 84: Line 88:
Takes no input. Returns 0x10-bytes and an output u32 ('''error_code''').
Takes no input. Returns 0x10-bytes and an output u32 ('''error_code''').


== SetAruid ==
== SetAruidForTest ==
Takes an input u64 which must [[IPC_Marshalling|match]] the user-process PID ([[Applet_Manager_services#AppletResourceUserId|AppletResourceUserId]]). Returns an output u32 ('''error_code''').
Takes an input u64 which must [[IPC_Marshalling|match]] the user-process PID ([[Applet_Manager_services#AppletResourceUserId|AppletResourceUserId]]). Returns an output u32 ('''error_code''').


== SetAruidByPID ==
== SetAruid ==
Takes a PID-descriptor and an u64 which must [[IPC_Marshalling|match]] the user-process PID ([[Applet_Manager_services#AppletResourceUserId|AppletResourceUserId]]). Returns an output u32 ('''error_code''').
Takes a PID-descriptor and an u64 which must [[IPC_Marshalling|match]] the user-process PID ([[Applet_Manager_services#AppletResourceUserId|AppletResourceUserId]]). Returns an output u32 ('''error_code''').


== DumpGraphicsMemoryInfo ==
== DumpGraphicsMemoryInfo ==
No input or output. Does nothing.
No input or output.


== InitializeDevtools ==
== InitializeDevtools ==
Takes a copy-handle and an input u32. Returns an output u32 ('''error_code''').
Takes a copy-handle ('''transfer_memory''') and an input u32 ('''transfer_memory_size'''). Returns an output u32 ('''error_code''').


== Ioctl2 ==
== Ioctl2 ==
Line 103: Line 107:
Cmdhdr_word1 is 0x100B instead of 0xC0B.
Cmdhdr_word1 is 0x100B instead of 0xC0B.


== FinishInitialize ==
== SetGraphicsFirmwareMemoryMarginEnabled ==
Takes an input u64. No output.
Takes an input u64. No output.


Line 109: Line 113:


Official user-processes starting with 3.0.0 now use this at the end of nvdrv service init with value 0x1.
Official user-processes starting with 3.0.0 now use this at the end of nvdrv service init with value 0x1.
= Permissions =
Each nvdrv service is initialized with a bitfield that controls access to nodes and other operations.
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0
| Can access [[#Channels|/dev/nvhost-gpu]], [[#/dev/nvhost-ctrl-gpu|/dev/nvhost-ctrl-gpu]] and [[#/dev/nvhost-as-gpu|/dev/nvhost-as-gpu]].
|-
| 1
| Can access [[#/dev/nvhost-dbg-gpu|/dev/nvhost-dbg-gpu]] and [[#/dev/nvhost-prof-gpu|/dev/nvhost-prof-gpu]].
|-
| 2
| Can access [[#/dev/nvsched-ctrl|/dev/nvsched-ctrl]].
|-
| 3
| Can access [[#Channels|/dev/nvhost-vic]].
|-
| 4
| Can access [[#Channels|/dev/nvhost-msenc]].
|-
| 5
| Can access [[#Channels|/dev/nvhost-nvdec]].
|-
| 6
|
|-
| 7
| Can access [[#Channels|/dev/nvhost-nvjpg]].
|-
| 8
| Can access [[#Channels|/dev/nvhost-display]], [[#/dev/nvcec-ctrl|/dev/nvcec-ctrl]], [[#/dev/nvhdcp_up-ctrl|/dev/nvhdcp_up-ctrl]], [[#/dev/nvdisp-ctrl|/dev/nvdisp-ctrl]], [[#/dev/nvdisp-disp0, /dev/nvdisp-disp1|/dev/nvdisp-disp0]], [[#/dev/nvdisp-disp0, /dev/nvdisp-disp1|/dev/nvdisp-disp1]], [[#/dev/nvdcutil-disp0, /dev/nvdcutil-disp1|/dev/nvdcutil-disp0]] and [[#/dev/nvdcutil-disp0, /dev/nvdcutil-disp1|/dev/nvdcutil-disp1]].
|-
| 9
| Can duplicate [[#/dev/nvmap|nvmap]] handles from other processes with [[#NVMAP_IOC_FROM_ID|NVMAP_IOC_FROM_ID]].
|-
| 10
| Can use [[#SetAruidForTest|SetAruidForTest]].
|-
| 11
| Can use [[#SetGraphicsFirmwareMemoryMarginEnabled|SetGraphicsFirmwareMemoryMarginEnabled]].
|-
| 12
| Can duplicate exported [[#/dev/nvmap|nvmap]] handles from other processes with [[#NVMAP_IOC_FROM_ID|NVMAP_IOC_FROM_ID]].
|-
| 13
|
|-
| 14
| Can use [[#NVMAP_IOC_EXPORT_FOR_ARUID|NVMAP_IOC_EXPORT_FOR_ARUID]] and [[#NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID|NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID]].
|-
| 15
|
|-
| 16-31
| Unused.
|}
Nodes [[#/dev/nvmap|/dev/nvmap]], [[#/dev/nvhost-ctrl|/dev/nvhost-ctrl]] and [[#/dev/nverpt-ctrl|/dev/nverpt-ctrl]] are always accessible.


= Ioctls =
= Ioctls =
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     __in  u32 handle;
     __in  u32 handle;
     u32      pad;
     u32      pad;
     __out u64 refcount;
     __out u64 address;
     __out u32 size;
     __out u32 size;
     __out u32 flags;    // 1=NOT_FREED_YET
     __out u32 flags;    // 1=NOT_FREED_YET
Line 718: Line 783:
   struct {
   struct {
     __in u32 fence_id;
     __in u32 fence_id;
     __in u32 fence_value;
     __in u32 fence_thresh;
     __in u32 swap_interval;
     __in u32 swap_interval;
   };
   };
Line 858: Line 923:
Maps a memory region in the device address space. Identical to Linux driver pretty much.
Maps a memory region in the device address space. Identical to Linux driver pretty much.


On success, the mapped memory region is locked by having [[SVC#MemoryState]] bit34 set.
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.


   struct {
   struct {
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Unaligned size will cause a [[#Panic]].
Unaligned size will cause a [[#Panic]].


On success, the mapped memory region is locked by having [[SVC#MemoryState]] bit34 set.
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.


   struct {
   struct {
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     __in u32 flags;          // passes 0
     __in u32 flags;          // passes 0
     __in u32 reserved;        // ignored; passes 0
     __in u32 reserved;        // ignored; passes 0
     __in u64 unk0;
     __in u64 va_range_start;
     __in u64 unk1;
     __in u64 va_range_end;
     __in u64 unk2;
     __in u64 va_range_split;
   };
   };


Line 955: Line 1,020:


   struct remap_entry {
   struct remap_entry {
     __in u16 flags;       // 0 or 4
     __in u16 flags;           // 0 or 4
     __in u16 kind;           
     __in u16 kind;           
     __in u32 nvmap_handle;
     __in u32 nvmap_handle;
     __in u32 reserved;
     __in u32 map_offset;
     __in u32 offset;      // (alloc_space_offset >> 0x10)
     __in u32 gpu_offset;      // (alloc_space_offset >> 0x10)
     __in u32 pages;       // alloc_space_pages
     __in u32 pages;           // alloc_space_pages
   };
   };
   
   
Line 1,070: Line 1,135:
| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]
| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]
|-
|-
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || [[#NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE]]
|-
|-
| 0x80084711 || Out || 8 || NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS
| 0x80084711 || Out || 8 || [[#NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS]]
|-
|-
| 0x80084712 || Out || 8 || NVGPU_GPU_IOCTL_NUM_VSMS
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]]
|-
|-
| 0xC0044713 || Inout || 4 || NVGPU_GPU_IOCTL_VSMS_MAPPING
| 0xC0044713 || Inout || 4 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]
|-
|-
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
|-
|-
| 0x80044715 || Out || 4 || NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD
| 0x80044715 || Out || 4 || [[#NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD]]
|-
|-
| 0x40084716 || In || 8 || NVGPU_GPU_IOCTL_SET_CG_CONTROLS
| 0x40084716 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_CG_CONTROLS]]
|-
|-
| 0xC0084717 || Inout || 8 || NVGPU_GPU_IOCTL_GET_CG_CONTROLS
| 0xC0084717 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_CG_CONTROLS]]
|-
|-
| 0x40084718 || In || 8 || NVGPU_GPU_IOCTL_SET_PG_CONTROLS
| 0x40084718 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_PG_CONTROLS]]
|-
|-
| 0xC0084719 || Inout || 8 || NVGPU_GPU_IOCTL_GET_PG_CONTROLS
| 0xC0084719 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_PG_CONTROLS]]
|-
|-
| 0x8018471A || Out || 24 || NVGPU_GPU_IOCTL_PMU_DUMP_ELPG_STATS
| 0x8018471A || Out || 24 || [[#NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING]]
|-
|-
| 0xC008471B || Inout || 8 || NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA
| 0xC008471B || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA]]
|-
|-
| 0xC010471C || Inout || 16 || NVGPU_GPU_IOCTL_GET_GPU_TIME
| 0xC010471C || Inout || 16 || [[#NVGPU_GPU_IOCTL_GET_GPU_TIME]]
|-
|-
| 0xC108471D || Inout || 264 || NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
|}
|}


Line 1,239: Line 1,304:
   };
   };


=== NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK ===
=== NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE ===
Returns the mask value for a ZBC slot.
Waits until all valid warps on the GPU SM are paused and returns their current state.
 
  struct {
    __in u64 pwarpstate;
  };
 
[6.1.0+] This command was modified to return inline data instead of using a pointer.
 
  struct {
    __out u64 sm0_valid_warps;
    __out u64 sm0_trapped_warps;
    __out u64 sm0_paused_warps;
    __out u64 sm1_valid_warps;
    __out u64 sm1_trapped_warps;
    __out u64 sm1_paused_warps;
  };
 
=== NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS ===
Returns a mask value describing all active TPC exceptions. Identical to Linux driver.
 
  struct {
    __out u64 tpc_exception_en_sm_mask;
  };
 
=== NVGPU_GPU_IOCTL_NUM_VSMS ===
Returns the number of GPU SM units present. Identical to Linux driver.
 
  struct {
    __out u32 num_vsms;
    __out u32 reserved;
  };
 
=== NVGPU_GPU_IOCTL_VSMS_MAPPING ===
Returns mapping information on each GPU SM unit. Modified to return inline data instead of using a pointer.
 
  struct {
    __out u8 sm0_gpc_index;
    __out u8 sm0_tpc_index;
    __out u8 sm1_gpc_index;
    __out u8 sm1_tpc_index;
  };
 
=== NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK ===
Returns the mask value for a ZBC slot.


   struct {
   struct {
Line 1,247: Line 1,355:
   };
   };


== Channels ==
=== NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD ===
Channels are a concept for  NVIDIA hardware blocks that share a common interface.
Returns the GPU load value from the PMU.


{| class="wikitable" border="1"
  struct {
! Path || Name
    __out u32 pmu_gpu_load;
|-
  };
| /dev/nvhost-gpu || GPU
 
|-
=== NVGPU_GPU_IOCTL_SET_CG_CONTROLS ===
| /dev/nvhost-msenc || Video Encoder
Sets the clock gate control value.
|-
 
| /dev/nvhost-nvdec || Video Decoder
  struct {
|-
    __in u32 cg_mask;
| /dev/nvhost-nvjpg || JPEG Decoder
    __in u32 cg_value;
|-
  };
| /dev/nvhost-vic || Video Image Compositor
 
|-
=== NVGPU_GPU_IOCTL_GET_CG_CONTROLS ===
| /dev/nvhost-display || Display
Returns the clock gate control value.
|}


== Channel Ioctls ==
  struct {
{| class="wikitable" border="1"
    __in u32 cg_mask;
! Value || Size || Description
    __out u32 cg_value;
|-
  };
| 0xC0??0001 || Variable || NVHOST_IOCTL_CHANNEL_SUBMIT
 
|-
=== NVGPU_GPU_IOCTL_SET_PG_CONTROLS ===
| 0xC0080002 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
Sets the power gate control value.
 
  struct {
    __in u32 pg_mask;
    __in u32 pg_value;
  };
 
=== NVGPU_GPU_IOCTL_GET_PG_CONTROLS ===
Returns the power gate control value.
 
  struct {
    __in u32 pg_mask;
    __out u32 pg_value;
  };
 
=== NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING ===
Returns the GPU PMU ELPG residency gating values.
 
  struct {
    __out u64 pg_ingating_time_us;
    __out u64 pg_ungating_time_us;
    __out u64 pg_gating_cnt;
  };
 
=== NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA ===
Returns user specific data from the error channel, if one exists.
 
  struct {
    __out u64 data;
  };
 
=== NVGPU_GPU_IOCTL_GET_GPU_TIME ===
Returns the timestamp from the GPU's nanosecond timer (PTIMER). Identical to Linux driver.
 
  struct {
    __out u64 gpu_timestamp;      // raw GPU counter (PTIMER) value
    __out u64 reserved;
  };
 
=== NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO ===
Returns CPU/GPU timestamp pairs for correlation analysis. Identical to Linux driver.
 
struct time_correlation_sample {
  u64 cpu_timestamp;                                  // from CPU's CNTPCT_EL0 register
  u64 gpu_timestamp;                                  // from GPU's PTIMER registers
};
struct {
  __out struct time_correlation_sample samples[16];  // timestamp pairs
  __in u32    count;                                // number of pairs to read
  __in u32    source_id;                            // cpu clock source id (must be 1)
};
 
== Channels ==
Channels are a concept for  NVIDIA hardware blocks that share a common interface.
 
{| class="wikitable" border="1"
! Path || Name
|-
| /dev/nvhost-gpu || GPU
|-
| /dev/nvhost-msenc || Video Encoder
|-
| /dev/nvhost-nvdec || Video Decoder
|-
| /dev/nvhost-nvjpg || JPEG Decoder
|-
| /dev/nvhost-vic || Video Image Compositor
|-
| /dev/nvhost-display || Display
|}
 
== Channel Ioctls ==
{| class="wikitable" border="1"
! Value || Size || Description
|-
| 0xC0??0001 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT]]
|-
| 0xC0080002 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
|-
| 0xC0080003 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
|-
| 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
|-
| 0x40040007 || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
|-
| 0x40080008 || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
|-
| 0xC0??0009 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
|-
| 0xC0??000A || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
|-
| 0x00000013 || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
|-
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
|-
| 0xC0??0024 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]
|-
| 0xC0??0025 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
|-
| 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
|- style="border-top: double"
| 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
|-
| 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
|-
| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
|-
| 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
|-
| 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
|-
| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
|-
| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
|-
| 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
|-
| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
|-
| 0xC018480C || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
|-
| 0x4004480D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
|-
|-
| 0xC0080003 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
| 0x0000480E || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
|-
|-
| 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
| 0x0000480F || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
|-
|-
| 0x40040007 || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
| 0x00004810 || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
|-
|-
| 0x40080008 || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
| 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
|-
|-
| 0xC0??0009 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
| 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
|-
|-
| 0xC0??000A || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
| 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
|-
|-
| 0x00000013 || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
| 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
|-
|-
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
|-
|-
| 0xC0??0024 || Variable || NVHOST_IOCTL_CHANNEL_SUBMIT_EX
| 0x40204818 || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
|-
|-
| 0xC0??0025 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
| 0xC0??4819 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
|-
|-
| 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
| 0xC020481A || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
|- style="border-top: double"
| 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
|-
|-
| 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
| 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_EX]]
|-
|-
| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
| 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY_EX]]
|-
|-
| 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
|- style="border-top: double"
| 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
|-
|-
| 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
| 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
|-
|}
| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
 
|-
=== NVHOST_IOCTL_CHANNEL_SUBMIT ===
| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
Submits data to the channel.
|-
 
| 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
  struct cmdbuf {
|-
    u32 mem;
| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
    u32 offset;
|-
    u32 words;
| 0xC018480C || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
  };
|-
 
| 0x4004480D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
  struct reloc {
|-
    u32 cmdbuf_mem;
| 0x0000480E || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
    u32 cmdbuf_offset;
|-
    u32 target;
| 0x0000480F || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
    u32 target_offset;
|-
  };
| 0x00004810 || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
 
|-
  struct reloc_shift {
| 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
    u32 shift;
|-
  };
| 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
 
|-
  struct syncpt_incr {
| 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
    u32 syncpt_id;
|-
    u32 syncpt_incrs;
| 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
  };
|-
 
| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
  struct fence {
|-
    u32 id;
| 0x40204818 || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
    u32 thresh;
|-
  };
| 0xC0??4819 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
 
|-
  struct {
| 0xC020481A || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
    __in    u32 num_cmdbufs;
|-
    __in    u32 num_relocs;
| 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_EX]]
    __in    u32 num_syncpt_incrs;
|-
    __in    u32 num_fences;
| 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY_EX]]
    __in    struct cmdbuf cmdbufs[];              // depends on num_cmdbufs
|-
    __in    struct reloc relocs[];                // depends on num_relocs
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
    __in    struct reloc_shift reloc_shifts[];    // depends on num_relocs
|- style="border-top: double"
    __in    struct syncpt_incr syncpt_incrs[];    // depends on num_syncpt_incrs
| 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
    __out  struct fence fences[];                // depends on num_fences
|-
  };
| 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
 
|}
=== NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT ===
Returns the current syncpoint value for a given module. Identical to Linux driver.
 
  struct {
    __in    u32 module_id;
    __out  u32 syncpt_value;
  };


=== NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT ===
=== NVHOST_IOCTL_CHANNEL_GET_WAITBASE ===
Returns the current syncpoint value for a given module. Identical to Linux driver.
Returns the current waitbase value for a given module. Always returns 0.


   struct {
   struct {
     __in    u32 module_id;
     __in    u32 module_id;
    __out  u32 syncpt_value;
     __out  u32 waitbase_value;
  };
 
=== NVHOST_IOCTL_CHANNEL_GET_WAITBASE ===
Returns the current waitbase value for a given module. Always returns 0.
 
  struct {
    __in    u32 module_id;
     __out  u32 waitbase_value;
   };
   };


Line 1,376: Line 1,603:
     __in    u32 timeout;
     __in    u32 timeout;
   };
   };
 
 
=== NVHOST_IOCTL_CHANNEL_SET_CLK_RATE ===
=== NVHOST_IOCTL_CHANNEL_SET_CLK_RATE ===
Sets the clock rate value for a given module. Identical to Linux driver.
Sets the clock rate value for a given module. Identical to Linux driver.
 
 
   struct {
   struct {
     __in    u32 clk_rate;
     __in    u32 clk_rate;
    __in    u32 module_id;
  };
 
=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER ===
Uses '''nvmap_pin''' internally to pin a given number of nvmap handles to an appropriate device physical address.
 
  struct handle {
    u32 handle_id_in;                // nvmap handle to map
    u32 phys_addr_out;                // returned device physical address mapped to the handle
  };
  struct {
    __in    u32 num_handles;          // number of nvmap handles to map
    __in    u32 reserved;            // ignored
    __in    u8  is_compr;            // memory to map is compressed
    __in    u8  padding[3];          // ignored
    __inout struct handle handles[];  // depends on num_handles
  };
 
=== NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER ===
Uses '''nvmap_unpin''' internally to unpin a given number of nvmap handles from their device physical address.
 
  struct handle {
    u32 handle_id_in;                // nvmap handle to unmap
    u32 reserved;                    // ignored
  };
  struct {
    __in    u32 num_handles;          // number of nvmap handles to unmap
    __in    u32 reserved;            // ignored
    __in    u8  is_compr;            // memory to unmap is compressed
    __in    u8  padding[3];          // ignored
    __inout struct handle handles[];  // depends on num_handles
  };
 
=== NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX ===
Sets the global timeout value for the channel. Identical to Linux driver.
 
  struct {
    __in    u32 timeout;
    __in    u32 flags;
  };
 
=== NVHOST_IOCTL_CHANNEL_GET_CLK_RATE ===
Returns the clock rate value for a given module. Identical to Linux driver.
 
  struct {
    __out  u32 clk_rate;
     __in    u32 module_id;
     __in    u32 module_id;
   };
   };


=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER ===
=== NVHOST_IOCTL_CHANNEL_SUBMIT_EX ===
Uses '''nvmap_pin''' internally to pin a given number of nvmap handles to an appropriate device physical address.
Same as [[#NVHOST_IOCTL_CHANNEL_SUBMIT|NVHOST_IOCTL_CHANNEL_SUBMIT]].
 
  struct handle {
    u32 handle_id_in;                // nvmap handle to map
    u32 phys_addr_out;                // returned device physical address mapped to the handle
  };
  struct {
    __in    u32 num_handles;          // number of nvmap handles to map
    __in    u32 reserved;            // ignored
    __in    u8  is_compr;            // memory to map is compressed
    __in    u8  padding[3];          // ignored
    __inout struct handle handles[];  // depends on num_handles
  };
 
=== NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER ===
Uses '''nvmap_unpin''' internally to unpin a given number of nvmap handles from their device physical address.
 
  struct handle {
    u32 handle_id_in;                // nvmap handle to unmap
    u32 reserved;                    // ignored
  };
  struct {
    __in    u32 num_handles;          // number of nvmap handles to unmap
    __in    u32 reserved;            // ignored
    __in    u8  is_compr;            // memory to unmap is compressed
    __in    u8  padding[3];          // ignored
    __inout struct handle handles[];  // depends on num_handles
  };
 
=== NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX ===
Sets the global timeout value for the channel. Identical to Linux driver.
 
  struct {
    __in    u32 timeout;
    __in    u32 flags;
  };
 
=== NVHOST_IOCTL_CHANNEL_GET_CLK_RATE ===
Returns the clock rate value for a given module. Identical to Linux driver.
 
  struct {
    __out  u32 clk_rate;
    __in    u32 module_id;
  };


=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX ===
=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX ===
Line 1,484: Line 1,714:


   struct fence {
   struct fence {
     u32 syncpt_id;
     u32 id;
     u32 syncpt_value;
     u32 thresh;
   };
   };
    
    
Line 1,595: Line 1,825:


  struct fence {
  struct fence {
  u32 syncpt_id;
    u32 id;
  u32 syncpt_value;
    u32 thresh;
  };
  };
   
   
Retrieved from "https://switchbrew.org/wiki/NV_services"