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NV services: Difference between revisions

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Each service is used by:
Each service is used by:
* "nvdrv": regular applications
* "nvdrv": Applications.
* "nvdrv:a": applets
** [[#Permissions|Permission]] mask is [3.0.0+] 0xA82B ([1.0.0-2.3.0] 0x2B).
* "nvdrv:s": sysmodules
* "nvdrv:a": Applets.
* "nvdrv:t": factory titles
** [[#Permissions|Permission]] mask is [3.0.0+] 0x10A9 ([1.0.0-2.3.0] 0xA9).
* "nvdrv:s": Sysmodules.
** [[#Permissions|Permission]] mask is [3.0.0+] 0x439E ([1.0.0-2.3.0] 0x39E).
* "nvdrv:t": Factory.
** [[#Permissions|Permission]] mask is 0xFFFFFFFF.


{| class="wikitable" border="1"
{| class="wikitable" border="1"
Line 30: Line 34:
| 6 || [[#GetStatus]]
| 6 || [[#GetStatus]]
|-
|-
| 7 || [[#SetAruid]]
| 7 || [[#SetAruidForTest]]
|-
|-
| 8 || [[#SetAruidByPID]]
| 8 || [[#SetAruid]]
|-
|-
| 9 || [[#DumpGraphicsMemoryInfo]]
| 9 || [[#DumpGraphicsMemoryInfo]]
Line 42: Line 46:
| 12 || [3.0.0+] [[#Ioctl3]]
| 12 || [3.0.0+] [[#Ioctl3]]
|-
|-
| 13 || [3.0.0+] [[#FinishInitialize]]
| 13 || [3.0.0+] [[#SetGraphicsFirmwareMemoryMarginEnabled]]
|}
|}


Line 84: Line 88:
Takes no input. Returns 0x10-bytes and an output u32 ('''error_code''').
Takes no input. Returns 0x10-bytes and an output u32 ('''error_code''').


== SetAruid ==
== SetAruidForTest ==
Takes an input u64 which must [[IPC_Marshalling|match]] the user-process PID ([[Applet_Manager_services#AppletResourceUserId|AppletResourceUserId]]). Returns an output u32 ('''error_code''').
Takes an input u64 which must [[IPC_Marshalling|match]] the user-process PID ([[Applet_Manager_services#AppletResourceUserId|AppletResourceUserId]]). Returns an output u32 ('''error_code''').


== SetAruidByPID ==
== SetAruid ==
Takes a PID-descriptor and an u64 which must [[IPC_Marshalling|match]] the user-process PID ([[Applet_Manager_services#AppletResourceUserId|AppletResourceUserId]]). Returns an output u32 ('''error_code''').
Takes a PID-descriptor and an u64 which must [[IPC_Marshalling|match]] the user-process PID ([[Applet_Manager_services#AppletResourceUserId|AppletResourceUserId]]). Returns an output u32 ('''error_code''').


== DumpGraphicsMemoryInfo ==
== DumpGraphicsMemoryInfo ==
No input or output. Does nothing.
No input or output.


== InitializeDevtools ==
== InitializeDevtools ==
Takes a copy-handle and an input u32. Returns an output u32 ('''error_code''').
Takes a copy-handle ('''transfer_memory''') and an input u32 ('''transfer_memory_size'''). Returns an output u32 ('''error_code''').


== Ioctl2 ==
== Ioctl2 ==
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Cmdhdr_word1 is 0x100B instead of 0xC0B.
Cmdhdr_word1 is 0x100B instead of 0xC0B.


== FinishInitialize ==
== SetGraphicsFirmwareMemoryMarginEnabled ==
Takes an input u64. No output.
Takes an input u64. No output.


Line 109: Line 113:


Official user-processes starting with 3.0.0 now use this at the end of nvdrv service init with value 0x1.
Official user-processes starting with 3.0.0 now use this at the end of nvdrv service init with value 0x1.
= Permissions =
Each nvdrv service is initialized with a bitfield that controls access to nodes and other operations.
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0
| Can access [[#Channels|/dev/nvhost-gpu]], [[#/dev/nvhost-ctrl-gpu|/dev/nvhost-ctrl-gpu]] and [[#/dev/nvhost-as-gpu|/dev/nvhost-as-gpu]].
|-
| 1
| Can access [[#/dev/nvhost-dbg-gpu|/dev/nvhost-dbg-gpu]] and [[#/dev/nvhost-prof-gpu|/dev/nvhost-prof-gpu]].
|-
| 2
| Can access [[#/dev/nvsched-ctrl|/dev/nvsched-ctrl]].
|-
| 3
| Can access [[#Channels|/dev/nvhost-vic]].
|-
| 4
| Can access [[#Channels|/dev/nvhost-msenc]].
|-
| 5
| Can access [[#Channels|/dev/nvhost-nvdec]].
|-
| 6
|
|-
| 7
| Can access [[#Channels|/dev/nvhost-nvjpg]].
|-
| 8
| Can access [[#Channels|/dev/nvhost-display]], [[#/dev/nvcec-ctrl|/dev/nvcec-ctrl]], [[#/dev/nvhdcp_up-ctrl|/dev/nvhdcp_up-ctrl]], [[#/dev/nvdisp-ctrl|/dev/nvdisp-ctrl]], [[#/dev/nvdisp-disp0, /dev/nvdisp-disp1|/dev/nvdisp-disp0]], [[#/dev/nvdisp-disp0, /dev/nvdisp-disp1|/dev/nvdisp-disp1]], [[#/dev/nvdcutil-disp0, /dev/nvdcutil-disp1|/dev/nvdcutil-disp0]] and [[#/dev/nvdcutil-disp0, /dev/nvdcutil-disp1|/dev/nvdcutil-disp1]].
|-
| 9
| Can duplicate [[#/dev/nvmap|nvmap]] handles from other processes with [[#NVMAP_IOC_FROM_ID|NVMAP_IOC_FROM_ID]].
|-
| 10
| Can use [[#SetAruidForTest|SetAruidForTest]].
|-
| 11
| Can use [[#SetGraphicsFirmwareMemoryMarginEnabled|SetGraphicsFirmwareMemoryMarginEnabled]].
|-
| 12
| Can duplicate exported [[#/dev/nvmap|nvmap]] handles from other processes with [[#NVMAP_IOC_FROM_ID|NVMAP_IOC_FROM_ID]].
|-
| 13
|
|-
| 14
| Can use [[#NVMAP_IOC_EXPORT_FOR_ARUID|NVMAP_IOC_EXPORT_FOR_ARUID]] and [[#NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID|NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID]].
|-
| 15
|
|-
| 16-31
| Unused.
|}
Nodes [[#/dev/nvmap|/dev/nvmap]], [[#/dev/nvhost-ctrl|/dev/nvhost-ctrl]] and [[#/dev/nverpt-ctrl|/dev/nverpt-ctrl]] are always accessible.


= Ioctls =
= Ioctls =
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=== NVHOST_IOCTL_CTRL_GET_CONFIG ===
=== NVHOST_IOCTL_CTRL_GET_CONFIG ===
Gets configured settings. Not available in production mode.
Returns configured settings. Not available in production mode.


   struct {
   struct {
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     __in  u32 handle;
     __in  u32 handle;
     u32      pad;
     u32      pad;
     __out u64 refcount;
     __out u64 address;
     __out u32 size;
     __out u32 size;
     __out u32 flags;    // 1=NOT_FREED_YET
     __out u32 flags;    // 1=NOT_FREED_YET
Line 718: Line 783:
   struct {
   struct {
     __in u32 fence_id;
     __in u32 fence_id;
     __in u32 fence_value;
     __in u32 fence_thresh;
     __in u32 swap_interval;
     __in u32 swap_interval;
   };
   };
Line 858: Line 923:
Maps a memory region in the device address space. Identical to Linux driver pretty much.
Maps a memory region in the device address space. Identical to Linux driver pretty much.


On success, the mapped memory region is locked by having [[SVC#MemoryState]] bit34 set.
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.


   struct {
   struct {
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Unaligned size will cause a [[#Panic]].
Unaligned size will cause a [[#Panic]].


On success, the mapped memory region is locked by having [[SVC#MemoryState]] bit34 set.
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.


   struct {
   struct {
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     __in u32 flags;          // passes 0
     __in u32 flags;          // passes 0
     __in u32 reserved;        // ignored; passes 0
     __in u32 reserved;        // ignored; passes 0
     __in u64 unk0;
     __in u64 va_range_start;
     __in u64 unk1;
     __in u64 va_range_end;
     __in u64 unk2;
     __in u64 va_range_split;
   };
   };


Line 955: Line 1,020:


   struct remap_entry {
   struct remap_entry {
     __in u16 flags;       // 0 or 4
     __in u16 flags;           // 0 or 4
     __in u16 kind;           
     __in u16 kind;           
     __in u32 nvmap_handle;
     __in u32 nvmap_handle;
     __in u32 reserved;
     __in u32 map_offset;
     __in u32 offset;      // (alloc_space_offset >> 0x10)
     __in u32 gpu_offset;      // (alloc_space_offset >> 0x10)
     __in u32 pages;       // alloc_space_pages
     __in u32 pages;           // alloc_space_pages
   };
   };
   
   
Line 1,060: Line 1,125:
| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
|-
|-
| 0xC0184706 || Inout || 24 || NVGPU_GPU_IOCTL_GET_TPC_MASKS
| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]]
|-
|-
| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]]
| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]]
|-
|-
| 0x4008470D || In || 8 || NVGPU_GPU_IOCTL_INVAL_ICACHE
| 0x4008470D || In || 8 || [[#NVGPU_GPU_IOCTL_INVAL_ICACHE]]
|-
|-
| 0x4008470E || In || 8 || NVGPU_GPU_IOCTL_SET_MMUDEBUG_MODE
| 0x4008470E || In || 8 || [[#NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE]]
|-
|-
| 0x4010470F || In || 16 || NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE
| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]
|-
|-
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || [[#NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE]]
|-
|-
| 0x80084711 || Out || 8 || NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS
| 0x80084711 || Out || 8 || [[#NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS]]
|-
|-
| 0x80084712 || Out || 8 || NVGPU_GPU_IOCTL_NUM_VSMS
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]]
|-
|-
| 0xC0044713 || Inout || 4 || NVGPU_GPU_IOCTL_VSMS_MAPPING
| 0xC0044713 || Inout || 4 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]
|-
|-
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
|-
|-
| 0x80044715 || Out || 4 || NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD
| 0x80044715 || Out || 4 || [[#NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD]]
|-
|-
| 0x40084716 || In || 8 || NVGPU_GPU_IOCTL_SET_CG_CONTROLS
| 0x40084716 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_CG_CONTROLS]]
|-
|-
| 0xC0084717 || Inout || 8 || NVGPU_GPU_IOCTL_GET_CG_CONTROLS
| 0xC0084717 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_CG_CONTROLS]]
|-
|-
| 0x40084718 || In || 8 || NVGPU_GPU_IOCTL_SET_PG_CONTROLS
| 0x40084718 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_PG_CONTROLS]]
|-
|-
| 0xC0084719 || Inout || 8 || NVGPU_GPU_IOCTL_GET_PG_CONTROLS
| 0xC0084719 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_PG_CONTROLS]]
|-
|-
| 0x8018471A || Out || 24 || NVGPU_GPU_IOCTL_PMU_DUMP_ELPG_STATS
| 0x8018471A || Out || 24 || [[#NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING]]
|-
|-
| 0xC008471B || Inout || 8 || NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA
| 0xC008471B || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA]]
|-
|-
| 0xC010471C || Inout || 16 || NVGPU_GPU_IOCTL_GET_GPU_TIME
| 0xC010471C || Inout || 16 || [[#NVGPU_GPU_IOCTL_GET_GPU_TIME]]
|-
|-
| 0xC108471D || Inout || 264 || NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
|}
|}


Line 1,148: Line 1,213:
=== NVGPU_GPU_IOCTL_GET_CHARACTERISTICS ===
=== NVGPU_GPU_IOCTL_GET_CHARACTERISTICS ===
Returns the GPU characteristics. Modified to return inline data instead of using a pointer.
Returns the GPU characteristics. Modified to return inline data instead of using a pointer.
[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].


   struct gpu_characteristics {
   struct gpu_characteristics {
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     __in    u64 gpu_characteristics_buf_addr;  // ignored, but must not be NULL
     __in    u64 gpu_characteristics_buf_addr;  // ignored, but must not be NULL
     __out struct gpu_characteristics gc;
     __out struct gpu_characteristics gc;
  };
=== NVGPU_GPU_IOCTL_GET_TPC_MASKS ===
Returns the TPC mask value for each GPC. Modified to return inline data instead of using a pointer.
[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].
  struct {
    __in u32 mask_buf_size;      // ignored, but must not be NULL
    __in u32 reserved[3];
    __out u64 mask_buf;          // receives one 32-bit TPC mask per GPC (GPC 0 and GPC 1)
   };
   };


Line 1,198: Line 1,276:
   struct {
   struct {
     __in u32 flush;          // l2_flush | l2_invalidate << 1 | fb_flush << 2
     __in u32 flush;          // l2_flush | l2_invalidate << 1 | fb_flush << 2
     u32     reserved;
     __in u32 reserved;
  };
 
=== NVGPU_GPU_IOCTL_INVAL_ICACHE ===
Invalidates the GPU instruction cache. Identical to Linux driver.
 
  struct {
    __in s32 channel_fd;
    __in u32 reserved;
   };
   };


=== NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK ===
=== NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE ===
Returns the mask value for a ZBC slot.
Sets the GPU MMU debug mode. Identical to Linux driver.


   struct {
   struct {
     __out u32 slot;       // always 0x07
     __in u32 state;
     __out u32 mask;
     __in u32 reserved;
   };
   };


== Channels ==
=== NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE ===
Channels are a concept for  NVIDIA hardware blocks that share a common interface.
Sets the GPU SM debug mode. Identical to Linux driver.
 
  struct {
    __in s32 channel_fd;
    __in u32 enable;
    __in u64 sms;
  };


{| class="wikitable" border="1"
=== NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE ===
! Path || Name
Waits until all valid warps on the GPU SM are paused and returns their current state.
|-
 
| /dev/nvhost-gpu || GPU
  struct {
|-
    __in u64 pwarpstate;
| /dev/nvhost-msenc || Video Encoder
  };
|-
 
| /dev/nvhost-nvdec || Video Decoder
[6.1.0+] This command was modified to return inline data instead of using a pointer.
|-
 
| /dev/nvhost-nvjpg || JPEG Decoder
  struct {
|-
    __out u64 sm0_valid_warps;
| /dev/nvhost-vic || Video Image Compositor
    __out u64 sm0_trapped_warps;
|-
    __out u64 sm0_paused_warps;
| /dev/nvhost-display || Display
    __out u64 sm1_valid_warps;
|}
    __out u64 sm1_trapped_warps;
    __out u64 sm1_paused_warps;
  };
 
=== NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS ===
Returns a mask value describing all active TPC exceptions. Identical to Linux driver.


== Channel Ioctls ==
  struct {
{| class="wikitable" border="1"
    __out u64 tpc_exception_en_sm_mask;
! Value || Size || Description
  };
|-
 
| 0xC0??0001 || Variable || NVHOST_IOCTL_CHANNEL_SUBMIT
=== NVGPU_GPU_IOCTL_NUM_VSMS ===
|-
Returns the number of GPU SM units present. Identical to Linux driver.
| 0xC0080002 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
 
|-
  struct {
| 0xC0080003 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
    __out u32 num_vsms;
|-
    __out u32 reserved;
| 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
  };
|-
 
| 0x40040007 || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
=== NVGPU_GPU_IOCTL_VSMS_MAPPING ===
|-
Returns mapping information on each GPU SM unit. Modified to return inline data instead of using a pointer.
| 0x40080008 || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
 
|-
  struct {
| 0xC0??0009 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
    __out u8 sm0_gpc_index;
|-
    __out u8 sm0_tpc_index;
| 0xC0??000A || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
    __out u8 sm1_gpc_index;
|-
    __out u8 sm1_tpc_index;
| 0x00000013 || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
  };
|-
 
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
=== NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK ===
|-
Returns the mask value for a ZBC slot.
| 0xC0??0024 || Variable || NVHOST_IOCTL_CHANNEL_SUBMIT_EX
 
|-
  struct {
| 0xC0??0025 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
    __out u32 slot;      // always 0x07
|-
    __out u32 mask;
| 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
  };
|- style="border-top: double"
 
| 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
=== NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD ===
|-
Returns the GPU load value from the PMU.
| 0x40044803 || 4 || NVGPU_IOCTL_CHANNEL_SET_TIMEOUT
 
|-
  struct {
| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
    __out u32 pmu_gpu_load;
|-
  };
| 0x40184806 || || NVGPU_IOCTL_CHANNEL_WAIT
 
|-
=== NVGPU_GPU_IOCTL_SET_CG_CONTROLS ===
| 0xC0044807 || 4 || NVGPU_IOCTL_CHANNEL_CYCLE_STATS
Sets the clock gate control value.
|-
 
| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
  struct {
|-
    __in u32 cg_mask;
| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
    __in u32 cg_value;
|-
  };
| 0x4008480A || || NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX
 
|-
=== NVGPU_GPU_IOCTL_GET_CG_CONTROLS ===
| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
Returns the clock gate control value.
|-
 
| 0xC018480C || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
  struct {
|-
    __in u32 cg_mask;
| 0x4004480D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
    __out u32 cg_value;
|-
  };
| 0x0000480E || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
 
|-
=== NVGPU_GPU_IOCTL_SET_PG_CONTROLS ===
| 0x0000480F || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
Sets the power gate control value.
 
  struct {
    __in u32 pg_mask;
    __in u32 pg_value;
  };
 
=== NVGPU_GPU_IOCTL_GET_PG_CONTROLS ===
Returns the power gate control value.
 
  struct {
    __in u32 pg_mask;
    __out u32 pg_value;
  };
 
=== NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING ===
Returns the GPU PMU ELPG residency gating values.
 
  struct {
    __out u64 pg_ingating_time_us;
    __out u64 pg_ungating_time_us;
    __out u64 pg_gating_cnt;
  };
 
=== NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA ===
Returns user specific data from the error channel, if one exists.
 
  struct {
    __out u64 data;
  };
 
=== NVGPU_GPU_IOCTL_GET_GPU_TIME ===
Returns the timestamp from the GPU's nanosecond timer (PTIMER). Identical to Linux driver.
 
  struct {
    __out u64 gpu_timestamp;      // raw GPU counter (PTIMER) value
    __out u64 reserved;
  };
 
=== NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO ===
Returns CPU/GPU timestamp pairs for correlation analysis. Identical to Linux driver.
 
struct time_correlation_sample {
  u64 cpu_timestamp;                                  // from CPU's CNTPCT_EL0 register
  u64 gpu_timestamp;                                  // from GPU's PTIMER registers
};
struct {
  __out struct time_correlation_sample samples[16];  // timestamp pairs
  __in u32    count;                                // number of pairs to read
  __in u32    source_id;                            // cpu clock source id (must be 1)
};
 
== Channels ==
Channels are a concept for  NVIDIA hardware blocks that share a common interface.
 
{| class="wikitable" border="1"
! Path || Name
|-
|-
| 0x00004810 || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
| /dev/nvhost-gpu || GPU
|-
|-
| 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
| /dev/nvhost-msenc || Video Encoder
|-
|-
| 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
| /dev/nvhost-nvdec || Video Decoder
|-
|-
| 0xC0104813 || 16 || NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT
| /dev/nvhost-nvjpg || JPEG Decoder
|-
|-
| 0x80804816 || 128 || NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO
| /dev/nvhost-vic || Video Image Compositor
|-
|-
| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
| /dev/nvhost-display || Display
|}
 
== Channel Ioctls ==
{| class="wikitable" border="1"
! Value || Size || Description
|-
| 0xC0??0001 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT]]
|-
| 0xC0080002 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
|-
|-
| 0x40204818 || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
| 0xC0080003 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
|-
|-
| 0xC0??4819 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
| 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
|-
|-
| 0xC020481A || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
| 0x40040007 || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
|-
|-
| 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_EX]]
| 0x40080008 || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
|-
|-
| 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY_EX]]
| 0xC0??0009 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
|-
|-
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
| 0xC0??000A || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
|- style="border-top: double"
| 0x40084714 || 8 || NVGPU_IOCTL_CHANNEL_SET_USER_DATA
|-
|-
| 0x80084715 || 8 || NVGPU_IOCTL_CHANNEL_GET_USER_DATA
| 0x00000013 || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
|}
|-
 
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
=== NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT ===
|-
Returns the current syncpoint value for a given module. Identical to Linux driver.
| 0xC0??0024 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]
 
|-
  struct {
| 0xC0??0025 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
    __in    u32 module_id;
|-
    __out  u32 syncpt_value;
| 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
  };
|- style="border-top: double"
 
| 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
=== NVHOST_IOCTL_CHANNEL_GET_WAITBASE ===
|-
Returns the current waitbase value for a given module. Always returns 0.
| 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
 
|-
  struct {
| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
    __in    u32 module_id;
|-
    __out  u32 waitbase_value;
| 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
  };
|-
 
| 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
=== NVHOST_IOCTL_CHANNEL_GET_MODMUTEX ===
|-
Stubbed. Does a debug print and returns 0.
| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
 
|-
=== NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT ===
| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
Sets the submit timeout value for the channel. Identical to Linux driver.
|-
 
| 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
  struct {
|-
    __in    u32 timeout;
| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
  };
|-
 
| 0xC018480C || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
=== NVHOST_IOCTL_CHANNEL_SET_CLK_RATE ===
|-
Sets the clock rate value for a given module. Identical to Linux driver.
| 0x4004480D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
|-
| 0x0000480E || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
|-
| 0x0000480F || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
|-
| 0x00004810 || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
|-
| 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
|-
| 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
|-
| 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
|-
| 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
|-
| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
|-
| 0x40204818 || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
|-
| 0xC0??4819 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
|-
| 0xC020481A || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
|-
| 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_EX]]
|-
| 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY_EX]]
|-
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
|- style="border-top: double"
| 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
|-
| 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
|}


=== NVHOST_IOCTL_CHANNEL_SUBMIT ===
Submits data to the channel.
  struct cmdbuf {
    u32 mem;
    u32 offset;
    u32 words;
  };
 
  struct reloc {
    u32 cmdbuf_mem;
    u32 cmdbuf_offset;
    u32 target;
    u32 target_offset;
  };
 
  struct reloc_shift {
    u32 shift;
  };
 
  struct syncpt_incr {
    u32 syncpt_id;
    u32 syncpt_incrs;
  };
 
  struct fence {
    u32 id;
    u32 thresh;
  };
 
   struct {
   struct {
     __in    u32 clk_rate;
     __in    u32 num_cmdbufs;
     __in    u32 module_id;
     __in    u32 num_relocs;
    __in    u32 num_syncpt_incrs;
    __in    u32 num_fences;
    __in    struct cmdbuf cmdbufs[];              // depends on num_cmdbufs
    __in    struct reloc relocs[];                // depends on num_relocs
    __in    struct reloc_shift reloc_shifts[];    // depends on num_relocs
    __in    struct syncpt_incr syncpt_incrs[];    // depends on num_syncpt_incrs
    __out  struct fence fences[];                // depends on num_fences
   };
   };


=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER ===
=== NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT ===
Uses '''nvmap_pin''' internally to pin a given number of nvmap handles to an appropriate device physical address.
Returns the current syncpoint value for a given module. Identical to Linux driver.


   struct handle {
   struct {
     u32 handle_id_in;                 // nvmap handle to map
     __in    u32 module_id;
     u32 phys_addr_out;               // returned device physical address mapped to the handle
     __out  u32 syncpt_value;
   };
   };
 
=== NVHOST_IOCTL_CHANNEL_GET_WAITBASE ===
Returns the current waitbase value for a given module. Always returns 0.
 
   struct {
   struct {
     __in    u32 num_handles;         // number of nvmap handles to map
     __in    u32 module_id;
     __in    u32 reserved;             // ignored
     __out  u32 waitbase_value;
    __in    u8  is_compr;            // memory to map is compressed
    __in    u8  padding[3];          // ignored
    __inout struct handle handles[];  // depends on num_handles
   };
   };


=== NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER ===
=== NVHOST_IOCTL_CHANNEL_GET_MODMUTEX ===
Uses '''nvmap_unpin''' internally to unpin a given number of nvmap handles from their device physical address.
Stubbed. Does a debug print and returns 0.
 
=== NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT ===
Sets the submit timeout value for the channel. Identical to Linux driver.


   struct handle {
   struct {
     u32 handle_id_in;                 // nvmap handle to unmap
     __in    u32 timeout;
    u32 reserved;                    // ignored
   };
   };
 
=== NVHOST_IOCTL_CHANNEL_SET_CLK_RATE ===
Sets the clock rate value for a given module. Identical to Linux driver.
 
   struct {
   struct {
     __in    u32 num_handles;          // number of nvmap handles to unmap
    __in    u32 clk_rate;
    __in    u32 module_id;
  };
 
=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER ===
Uses '''nvmap_pin''' internally to pin a given number of nvmap handles to an appropriate device physical address.
 
  struct handle {
    u32 handle_id_in;                // nvmap handle to map
    u32 phys_addr_out;                // returned device physical address mapped to the handle
  };
  struct {
     __in    u32 num_handles;          // number of nvmap handles to map
     __in    u32 reserved;            // ignored
     __in    u32 reserved;            // ignored
     __in    u8  is_compr;            // memory to unmap is compressed
     __in    u8  is_compr;            // memory to map is compressed
     __in    u8  padding[3];          // ignored
     __in    u8  padding[3];          // ignored
     __inout struct handle handles[];  // depends on num_handles
     __inout struct handle handles[];  // depends on num_handles
   };
   };


=== NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX ===
=== NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER ===
Sets the global timeout value for the channel. Identical to Linux driver.
Uses '''nvmap_unpin''' internally to unpin a given number of nvmap handles from their device physical address.


  struct handle {
    u32 handle_id_in;                // nvmap handle to unmap
    u32 reserved;                    // ignored
  };
   struct {
   struct {
     __in    u32 timeout;
    __in    u32 num_handles;          // number of nvmap handles to unmap
    __in    u32 reserved;            // ignored
    __in    u8  is_compr;            // memory to unmap is compressed
    __in    u8  padding[3];          // ignored
    __inout struct handle handles[];  // depends on num_handles
  };
 
=== NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX ===
Sets the global timeout value for the channel. Identical to Linux driver.
 
  struct {
     __in    u32 timeout;
     __in    u32 flags;
     __in    u32 flags;
   };
   };
Line 1,394: Line 1,659:
     __in    u32 module_id;
     __in    u32 module_id;
   };
   };
=== NVHOST_IOCTL_CHANNEL_SUBMIT_EX ===
Same as [[#NVHOST_IOCTL_CHANNEL_SUBMIT|NVHOST_IOCTL_CHANNEL_SUBMIT]].


=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX ===
=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX ===
Line 1,406: Line 1,674:
   struct {
   struct {
     __in u32 nvmap_fd;
     __in u32 nvmap_fd;
  };
=== NVGPU_IOCTL_CHANNEL_SET_TIMEOUT ===
Sets the timeout value for the GPU channel. Identical to Linux driver.
  struct {
    __in u32 timeout;
   };
   };


Line 1,414: Line 1,689:
     __in u32 num_entries;
     __in u32 num_entries;
     __in u32 flags;
     __in u32 flags;
  };
=== NVGPU_IOCTL_CHANNEL_WAIT ===
Waits on channel. Identical to Linux driver.
  struct {
    __in u32 type;            // wait type (0=notifier, 1=semaphore)
    __in u32 timeout;        // wait timeout value
    __in u32 dmabuf_fd;      // nvmap handle
    __in u32 offset;          // nvmap memory offset
    __in u32 payload;        // payload data (semaphore only)
    __in u32 padding;        // ignored
  };
=== NVGPU_IOCTL_CHANNEL_CYCLE_STATS ===
Maps memory for the cycle stats buffer. Identical to Linux driver.
  struct {
    __in u32 dmabuf_fd;  // nvmap handle
   };
   };


Line 1,420: Line 1,714:


   struct fence {
   struct fence {
     u32 syncpt_id;
     u32 id;
     u32 syncpt_value;
     u32 thresh;
   };
   };
    
    
Line 1,445: Line 1,739:
     __in  u32 flags;        // bit0: LOCKBOOST_ZERO
     __in  u32 flags;        // bit0: LOCKBOOST_ZERO
     __out u64 obj_id;      // (ignored) used for FREE_OBJ_CTX ioctl, which is not supported
     __out u64 obj_id;      // (ignored) used for FREE_OBJ_CTX ioctl, which is not supported
  };
=== NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX ===
Frees a graphics context object. Not supported.
  struct {
    __in u64 obj_id;      // ignored
   };
   };


Line 1,491: Line 1,792:
     __in u32 cmd;    // 0=disable, 1=enable, 2=clear
     __in u32 cmd;    // 0=disable, 1=enable, 2=clear
     __in u32 id;    // same id's as for [[#QueryEvent]]
     __in u32 id;    // same id's as for [[#QueryEvent]]
  };
=== NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT ===
Controls the cycle stats snapshot buffer. Identical to Linux driver.
  struct {
    __in    u32 cmd;        // command to handle (0=flush, 1=attach, 2=detach)
    __in    u32 dmabuf_fd;  // nvmap handle
    __inout u32 extra;      // extra payload data/result
    __in    u32 padding;    // ignored
  };
=== NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO ===
Returns information on the current error notification caught by the error notifier. Exclusive to the Switch.
  struct {
    __out u32 error_info[32];    // first word is an error code (0=no_error, 1=gr_error, 2=gr_error, 3=invalid, 4=invalid)
   };
   };


=== NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION ===
=== NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION ===
Returns the current error notification caught by the error notifier. Exclusive to the Switch.
Returns the current error notification caught by the error notifier. Exclusive to the Switch.
Despite being marked as inout this is all output.


   struct {
   struct {
Line 1,509: Line 1,825:


  struct fence {
  struct fence {
  u32 syncpt_id;
    u32 id;
  u32 syncpt_value;
    u32 thresh;
  };
  };
   
   
Line 1,538: Line 1,854:
   struct {
   struct {
     __in u32 timeslice;
     __in u32 timeslice;
  };
=== NVGPU_IOCTL_CHANNEL_SET_USER_DATA ===
Sets user specific data.
  struct {
    __in u64 data;
  };
=== NVGPU_IOCTL_CHANNEL_GET_USER_DATA ===
Returns user specific data.
  struct {
    __out u64 data;
   };
   };


= nvmemp =
= nvmemp =
NVIDIA memory profiler (this service is not available on retail units).  
NVIDIA memory profiler (this service is not available on retail units).  
/dev/nvhost-ctrl sends the ioctl NVHOST_IOCTL_CTRL_GET_CONFIG to check the config "nv!NV_MEMORY_PROFILER". If config_str returns "1", the applications attempts to talk to use nvmemp.
/dev/nvhost-ctrl sends the ioctl NVHOST_IOCTL_CTRL_GET_CONFIG to check the config "nv!NV_MEMORY_PROFILER". If config_str returns "1", the application attempts to use nvmemp.


{| class="wikitable" border="1"
{| class="wikitable" border="1"
Line 1,550: Line 1,880:
| 0 || Open
| 0 || Open
|-
|-
| 1 || GetPid
| 1 || GetAruid
|}
|}


Line 1,578: Line 1,908:


== GetDebugFSKeys ==
== GetDebugFSKeys ==
Takes a u32 '''fd''' and reads debug contents into a type-6 buffer.
Takes a u32 '''fd''' and reads debug contents into a type-6 buffer.
 
 
= nvgem:c =
= nvgem:c =
This is "nv::gemcontrol::INvGemControl".
This is "nv::gemcontrol::INvGemControl".
 
{| class="wikitable" border="1"
|-
! Cmd || Name
|-
| 0 || Initialize
|-
| 1 || GetGemEvent
|-
| 2 ||
|-
| 3 || RegisterUnregisterAppIdLocked
|-
| 4 ||
|-
| [1.0.0-4.1.0] 5 || GetAruid
|-
| 6 || HandleDeferredErrors
|-
| 7 || [3.0.0+]
|}
 
= nvgem:cd =
This is "nv::gemcoredump::INvGemCoreDump".


{| class="wikitable" border="1"
{| class="wikitable" border="1"
Line 1,589: Line 1,943:
| 0 || Initialize
| 0 || Initialize
|-
|-
| 1 || GetGemEvent
| 1 || GetAruid
|-
| 2 ||
|-
| 3 || RegisterUnregisterAppIdLocked
|-
| 4 ||
|-
| [1.0.0-4.1.0] 5 || GetAruid
|-
| 6 || HandleDeferredErrors
|-
| 7 || [3.0.0+]
|}
 
= nvgem:cd =
This is "nv::gemcoredump::INvGemCoreDump".
 
{| class="wikitable" border="1"
|-
! Cmd || Name
|-
| 0 ||
|-
| 1 ||
|-
|-
| [1.0.0-8.1.0] 2 ||
| [1.0.0-8.1.0] 2 || ReadNextCdBlock
|-
|-
| 3 || [8.0.0+]
| 3 || [8.0.0+]
Retrieved from "https://switchbrew.org/wiki/NV_services"