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=== NVHOST_IOCTL_CTRL_GET_CONFIG ===
=== NVHOST_IOCTL_CTRL_GET_CONFIG ===
Gets configured settings. Not available in production mode.
Returns configured settings. Not available in production mode.


   struct {
   struct {
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     __in  u32 handle;
     __in  u32 handle;
     u32      pad;
     u32      pad;
     __out u64 refcount;
     __out u64 address;
     __out u32 size;
     __out u32 size;
     __out u32 flags;    // 1=NOT_FREED_YET
     __out u32 flags;    // 1=NOT_FREED_YET
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Maps a memory region in the device address space. Identical to Linux driver pretty much.
Maps a memory region in the device address space. Identical to Linux driver pretty much.


On success, the mapped memory region is locked by having [[SVC#MemoryState]] bit34 set.
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.


   struct {
   struct {
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Unaligned size will cause a [[#Panic]].
Unaligned size will cause a [[#Panic]].


On success, the mapped memory region is locked by having [[SVC#MemoryState]] bit34 set.
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.


   struct {
   struct {
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     __in u32 flags;          // passes 0
     __in u32 flags;          // passes 0
     __in u32 reserved;        // ignored; passes 0
     __in u32 reserved;        // ignored; passes 0
     __in u64 unk0;
     __in u64 va_range_start;
     __in u64 unk1;
     __in u64 va_range_end;
     __in u64 unk2;
     __in u64 va_range_split;
   };
   };


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   struct remap_entry {
   struct remap_entry {
     __in u16 flags;       // 0 or 4
     __in u16 flags;           // 0 or 4
     __in u16 kind;           
     __in u16 kind;           
     __in u32 nvmap_handle;
     __in u32 nvmap_handle;
     __in u32 reserved;
     __in u32 map_offset;
     __in u32 offset;      // (alloc_space_offset >> 0x10)
     __in u32 gpu_offset;      // (alloc_space_offset >> 0x10)
     __in u32 pages;       // alloc_space_pages
     __in u32 pages;           // alloc_space_pages
   };
   };
   
   
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| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]
| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]
|-
|-
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || [[#NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE]]
|-
|-
| 0x80084711 || Out || 8 || NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS
| 0x80084711 || Out || 8 || [[#NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS]]
|-
|-
| 0x80084712 || Out || 8 || NVGPU_GPU_IOCTL_NUM_VSMS
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]]
|-
|-
| 0xC0044713 || Inout || 4 || NVGPU_GPU_IOCTL_VSMS_MAPPING
| 0xC0044713 || Inout || 4 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]
|-
|-
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
|-
|-
| 0x80044715 || Out || 4 || NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD
| 0x80044715 || Out || 4 || [[#NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD]]
|-
|-
| 0x40084716 || In || 8 || NVGPU_GPU_IOCTL_SET_CG_CONTROLS
| 0x40084716 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_CG_CONTROLS]]
|-
|-
| 0xC0084717 || Inout || 8 || NVGPU_GPU_IOCTL_GET_CG_CONTROLS
| 0xC0084717 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_CG_CONTROLS]]
|-
|-
| 0x40084718 || In || 8 || NVGPU_GPU_IOCTL_SET_PG_CONTROLS
| 0x40084718 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_PG_CONTROLS]]
|-
|-
| 0xC0084719 || Inout || 8 || NVGPU_GPU_IOCTL_GET_PG_CONTROLS
| 0xC0084719 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_PG_CONTROLS]]
|-
|-
| 0x8018471A || Out || 24 || NVGPU_GPU_IOCTL_PMU_DUMP_ELPG_STATS
| 0x8018471A || Out || 24 || [[#NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING]]
|-
|-
| 0xC008471B || Inout || 8 || NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA
| 0xC008471B || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA]]
|-
|-
| 0xC010471C || Inout || 16 || NVGPU_GPU_IOCTL_GET_GPU_TIME
| 0xC010471C || Inout || 16 || [[#NVGPU_GPU_IOCTL_GET_GPU_TIME]]
|-
|-
| 0xC108471D || Inout || 264 || NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
|}
|}


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     __in u32 enable;
     __in u32 enable;
     __in u64 sms;
     __in u64 sms;
  };
=== NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE ===
Waits until all valid warps on the GPU SM are paused and returns their current state.
  struct {
    __in u64 pwarpstate;
  };
[6.1.0+] This command was modified to return inline data instead of using a pointer.
  struct {
    __out u64 sm0_valid_warps;
    __out u64 sm0_trapped_warps;
    __out u64 sm0_paused_warps;
    __out u64 sm1_valid_warps;
    __out u64 sm1_trapped_warps;
    __out u64 sm1_paused_warps;
  };
=== NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS ===
Returns a mask value describing all active TPC exceptions. Identical to Linux driver.
  struct {
    __out u64 tpc_exception_en_sm_mask;
  };
=== NVGPU_GPU_IOCTL_NUM_VSMS ===
Returns the number of GPU SM units present. Identical to Linux driver.
  struct {
    __out u32 num_vsms;
    __out u32 reserved;
  };
=== NVGPU_GPU_IOCTL_VSMS_MAPPING ===
Returns mapping information on each GPU SM unit. Modified to return inline data instead of using a pointer.
  struct {
    __out u8 sm0_gpc_index;
    __out u8 sm0_tpc_index;
    __out u8 sm1_gpc_index;
    __out u8 sm1_tpc_index;
   };
   };


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     __out u32 mask;
     __out u32 mask;
   };
   };
=== NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD ===
Returns the GPU load value from the PMU.
  struct {
    __out u32 pmu_gpu_load;
  };
=== NVGPU_GPU_IOCTL_SET_CG_CONTROLS ===
Sets the clock gate control value.
  struct {
    __in u32 cg_mask;
    __in u32 cg_value;
  };
=== NVGPU_GPU_IOCTL_GET_CG_CONTROLS ===
Returns the clock gate control value.
  struct {
    __in u32 cg_mask;
    __out u32 cg_value;
  };
=== NVGPU_GPU_IOCTL_SET_PG_CONTROLS ===
Sets the power gate control value.
  struct {
    __in u32 pg_mask;
    __in u32 pg_value;
  };
=== NVGPU_GPU_IOCTL_GET_PG_CONTROLS ===
Returns the power gate control value.
  struct {
    __in u32 pg_mask;
    __out u32 pg_value;
  };
=== NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING ===
Returns the GPU PMU ELPG residency gating values.
  struct {
    __out u64 pg_ingating_time_us;
    __out u64 pg_ungating_time_us;
    __out u64 pg_gating_cnt;
  };
=== NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA ===
Returns user specific data from the error channel, if one exists.
  struct {
    __out u64 data;
  };
=== NVGPU_GPU_IOCTL_GET_GPU_TIME ===
Returns the timestamp from the GPU's nanosecond timer (PTIMER). Identical to Linux driver.
  struct {
    __out u64 gpu_timestamp;      // raw GPU counter (PTIMER) value
    __out u64 reserved;
  };
=== NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO ===
Returns CPU/GPU timestamp pairs for correlation analysis. Identical to Linux driver.
struct time_correlation_sample {
  u64 cpu_timestamp;                                  // from CPU's CNTPCT_EL0 register
  u64 gpu_timestamp;                                  // from GPU's PTIMER registers
};
struct {
  __out struct time_correlation_sample samples[16];  // timestamp pairs
  __in u32    count;                                // number of pairs to read
  __in u32    source_id;                            // cpu clock source id (must be 1)
};


== Channels ==
== Channels ==
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=== NVGPU_IOCTL_CHANNEL_GET_USER_DATA ===
=== NVGPU_IOCTL_CHANNEL_GET_USER_DATA ===
Gets user specific data.
Returns user specific data.


   struct {
   struct {
Retrieved from "https://switchbrew.org/wiki/NV_services"