Line 149: |
Line 149: |
| |- | | |- |
| | 0x40080021 || In || 8 || [[#NVHOST_IOCTL_CTRL_EVENT_KILL]] | | | 0x40080021 || In || 8 || [[#NVHOST_IOCTL_CTRL_EVENT_KILL]] |
| + | |- |
| + | | 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_GET_MAX_EVENT_FIFO_CHANNEL]] |
| |} | | |} |
| | | |
Line 214: |
Line 216: |
| | | |
| === NVHOST_IOCTL_CTRL_GET_CONFIG === | | === NVHOST_IOCTL_CTRL_GET_CONFIG === |
− | Gets configured settings. Not available in production mode.
| + | Returns configured settings. Not available in production mode. |
| | | |
| struct { | | struct { |
Line 272: |
Line 274: |
| struct { | | struct { |
| __in u64 user_events; // 64-bit bitfield where each bit represents one event | | __in u64 user_events; // 64-bit bitfield where each bit represents one event |
| + | }; |
| + | |
| + | === NVHOST_IOCTL_CTRL_GET_MAX_EVENT_FIFO_CHANNEL === |
| + | If event FIFO is enabled, returns the maximum channel number. Exclusive to the Switch. |
| + | |
| + | struct { |
| + | __out u32 max_channel; // 0x00 (FIFO disabled) or 0x60 (FIFO enabled) |
| }; | | }; |
| | | |
Line 357: |
Line 366: |
| __in u32 handle; | | __in u32 handle; |
| u32 pad; | | u32 pad; |
− | __out u64 refcount; | + | __out u64 address; |
| __out u32 size; | | __out u32 size; |
| __out u32 flags; // 1=NOT_FREED_YET | | __out u32 flags; // 1=NOT_FREED_YET |
Line 446: |
Line 455: |
| | 0xC1100214 || Inout || 272 || NVDISP_CTRL_GET_OUTPUT_EDID | | | 0xC1100214 || Inout || 272 || NVDISP_CTRL_GET_OUTPUT_EDID |
| |- | | |- |
− | | 0xC0040216 || Inout || 4 || NVDISP_CTRL_GET_EXT_HPD_IN_EVENT | + | | 0xC0080216</br>([1.0.0-3.0.0] 0xC0040216) || Inout || 8</br>([1.0.0-3.0.0] 4) || NVDISP_CTRL_GET_EXT_HPD_IN_OUT_EVENTS</br>([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_IN_EVENT) |
| |- | | |- |
− | | 0xC0040217 || Inout || 4 || NVDISP_CTRL_GET_EXT_HPD_OUT_EVENT | + | | ([1.0.0-3.0.0] 0xC0040217) || ([1.0.0-3.0.0] Inout) || ([1.0.0-3.0.0] 4) || ([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_OUT_EVENT) |
| |- | | |- |
| | 0xC0100218 || Inout || 16 || NVDISP_CTRL_GET_VBLANK_HEAD0_EVENT | | | 0xC0100218 || Inout || 16 || NVDISP_CTRL_GET_VBLANK_HEAD0_EVENT |
Line 597: |
Line 606: |
| | 0x8001060C || Out || 1 || [[#NVSCHED_CTRL_HAS_OVERRUN_EVENT]] | | | 0x8001060C || Out || 1 || [[#NVSCHED_CTRL_HAS_OVERRUN_EVENT]] |
| |- | | |- |
− | | 0x8010060D || Out || 16 || [[#NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT]] | + | | 0x8020060D</br>([1.0.0-3.0.0] 0x8010060D) || Out || 32</br>([1.0.0-3.0.0] 16) || [[#NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT]] |
| |- | | |- |
| | 0x400C060E || In || 12 || [[#NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE]] | | | 0x400C060E || In || 12 || [[#NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE]] |
Line 700: |
Line 709: |
| __out u64 runlist_id; | | __out u64 runlist_id; |
| __out u64 debt; | | __out u64 debt; |
| + | __out u64 unk0; // 3.0.0+ only |
| + | __out u64 unk1; // 3.0.0+ only |
| }; | | }; |
| | | |
Line 724: |
Line 735: |
| ! Value || Direction || Size || Description | | ! Value || Direction || Size || Description |
| |- | | |- |
− | | 0xC1280701 || Inout || 296 || NVERPT_TELEMETRY_SUBMIT_DATA | + | | 0xC1280701 || Inout || 296 || [[#NVERPT_TELEMETRY_SUBMIT_DATA]] |
| |- | | |- |
− | | 0xCF580702 || Inout || 3928 || NVERPT_TELEMETRY_SUBMIT_DATA_EX | + | | 0xCF580702 || Inout || 3928 || [[#NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA]] |
| |} | | |} |
| + | |
| + | === NVERPT_TELEMETRY_SUBMIT_DATA === |
| + | Sends test data for creating a new [[Error_Report_services|Error Report]]. |
| + | |
| + | struct { |
| + | __in u64 TestU64; |
| + | __in u32 TestU32; |
| + | __in u8 padding0[4]; |
| + | __in s64 TestI64; |
| + | __in s32 TestI32; |
| + | __in u8 TestString[32]; |
| + | __in u8 TestU8Array[8]; |
| + | __in u32 TestU8Array_size; |
| + | __in u32 TestU32Array[8]; |
| + | __in u32 TestU32Array_size; |
| + | __in u64 TestU64Array[8]; |
| + | __in u32 TestU64Array_size; |
| + | __in s32 TestI32Array[8]; |
| + | __in u32 TestI32Array_size; |
| + | __in s64 TestI64Array[8]; |
| + | __in u32 TestI64Array_size; |
| + | __in u16 TestU16; |
| + | __in u8 TestU8; |
| + | __in s16 TestI16; |
| + | __in s8 TestI8; |
| + | __in u8 padding1[5]; |
| + | }; |
| + | |
| + | === NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA === |
| + | Sends display data for creating a new [[Error_Report_services|Error Report]]. |
| + | |
| + | struct { |
| + | __in u32 CodecType; |
| + | __in u32 DecodeBuffers; |
| + | __in u32 FrameWidth; |
| + | __in u32 FrameHeight; |
| + | __in u8 ColorPrimaries; |
| + | __in u8 TransferCharacteristics; |
| + | __in u8 MatrixCoefficients; |
| + | __in u8 padding; |
| + | __in u32 DisplayWidth; |
| + | __in u32 DisplayHeight; |
| + | __in u32 DARWidth; |
| + | __in u32 DARHeight; |
| + | __in u32 ColorFormat; |
| + | __in u32 ColorSpace[8]; |
| + | __in u32 ColorSpace_size; |
| + | __in u32 SurfaceLayout[8]; |
| + | __in u32 SurfaceLayout_size; |
| + | __in u8 ErrorString[64]; // must be "Error detected = 0x1000000" |
| + | __in u32 VideoDecState; |
| + | __in u8 VideoLog[3712]; |
| + | __in u32 VideoLog_size; |
| + | }; |
| | | |
| == /dev/nvhost-as-gpu == | | == /dev/nvhost-as-gpu == |
Line 755: |
Line 820: |
| | 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_INITIALIZE_EX]] | | | 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_INITIALIZE_EX]] |
| |- | | |- |
− | | 0xC038410A || Inout || 56 || NVGPU_AS_IOCTL_MAP_BUFFER_EX | + | | 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX]] |
| |- | | |- |
| | 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]] | | | 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]] |
Line 768: |
Line 833: |
| | | |
| === NVGPU_AS_IOCTL_ALLOC_SPACE === | | === NVGPU_AS_IOCTL_ALLOC_SPACE === |
− | This one reserves pages in the device address space.
| + | Reserves pages in the device address space. |
| | | |
| struct { | | struct { |
Line 782: |
Line 847: |
| | | |
| === NVGPU_AS_IOCTL_FREE_SPACE === | | === NVGPU_AS_IOCTL_FREE_SPACE === |
− | This one frees pages from the device address space.
| + | Frees pages from the device address space. |
| | | |
| struct { | | struct { |
Line 791: |
Line 856: |
| | | |
| === NVGPU_AS_IOCTL_MAP_BUFFER === | | === NVGPU_AS_IOCTL_MAP_BUFFER === |
− | Map a memory region in the device address space. Identical to Linux driver pretty much.
| + | Maps a memory region in the device address space. Identical to Linux driver pretty much. |
| | | |
− | On success, the mapped memory region is locked by having [[SVC#MemoryState]] bit34 set. | + | On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute. |
| | | |
| struct { | | struct { |
Line 807: |
Line 872: |
| | | |
| === NVGPU_AS_IOCTL_MODIFY === | | === NVGPU_AS_IOCTL_MODIFY === |
− | Modify a memory region in the device address space.
| + | Modifies a memory region in the device address space. |
| | | |
| Unaligned size will cause a [[#Panic]]. | | Unaligned size will cause a [[#Panic]]. |
| | | |
− | On success, the mapped memory region is locked by having [[SVC#MemoryState]] bit34 set. | + | On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute. |
| | | |
| struct { | | struct { |
− | __in u32 flags; // bit0: fixed_offset, bit2: cacheable | + | __in u32 flags; // bit0: fixed_offset, bit2: cacheable |
− | __in u32 kind; // -1 is default | + | __in u32 kind; // -1 is default |
− | __in u32 nvmap_handle; | + | __in u32 nvmap_handle; |
− | __inout u32 page_size; // 0 means don't care | + | __inout u32 page_size; // 0 means don't care |
− | __in u64 buffer_offset; | + | __in u64 buffer_offset; |
− | __in u64 mapping_size; | + | __in u64 mapping_size; |
| __inout u64 offset; | | __inout u64 offset; |
| }; | | }; |
| | | |
| === NVGPU_AS_IOCTL_UNMAP_BUFFER === | | === NVGPU_AS_IOCTL_UNMAP_BUFFER === |
− | Unmap a memory region from the device address space.
| + | Unmaps a memory region from the device address space. |
| | | |
| struct { | | struct { |
Line 841: |
Line 906: |
| | | |
| === NVGPU_AS_IOCTL_GET_VA_REGIONS === | | === NVGPU_AS_IOCTL_GET_VA_REGIONS === |
− | Nintendo modified to get rid of pointer in struct. | + | Nintendo's custom implementation to get rid of pointer in struct. |
| | | |
| struct va_region { | | struct va_region { |
Line 851: |
Line 916: |
| | | |
| struct { | | struct { |
− | u64 not_used; // (contained output user ptr on linux, ignored) | + | u64 not_used; // (contained output user ptr on linux, ignored) |
− | __inout u32 bufsize; // forced to 2*sizeof(struct va_region) | + | __inout u32 bufsize; // forced to 2*sizeof(struct va_region) |
− | u32 pad; | + | u32 pad; |
− | __out struct va_region regions[2]; | + | __out struct va_region regions[2]; |
| }; | | }; |
| | | |
Line 865: |
Line 930: |
| __in u32 flags; // passes 0 | | __in u32 flags; // passes 0 |
| __in u32 reserved; // ignored; passes 0 | | __in u32 reserved; // ignored; passes 0 |
− | __in u64 unk0; | + | __in u64 va_range_start; |
− | __in u64 unk1; | + | __in u64 va_range_end; |
− | __in u64 unk2; | + | __in u64 va_range_split; |
| + | }; |
| + | |
| + | === NVGPU_AS_IOCTL_MAP_BUFFER_EX === |
| + | Maps a memory region in the device address space with extra params. |
| + | |
| + | struct { |
| + | __in u32 flags; // bit0: fixed_offset, bit2: cacheable |
| + | __in u32 kind; // -1 is default |
| + | __in u32 nvmap_handle; |
| + | __inout u32 page_size; // 0 means don't care |
| + | __in u64 buffer_offset; |
| + | __in u64 mapping_size; |
| + | __inout u64 offset; |
| + | __in u64 unk0; |
| + | __in u32 unk1; |
| + | u32 pad; |
| }; | | }; |
| | | |
Line 874: |
Line 955: |
| | | |
| struct remap_entry { | | struct remap_entry { |
− | __in u16 flags; // 0 or 4 | + | __in u16 flags; // 0 or 4 |
| __in u16 kind; | | __in u16 kind; |
| __in u32 nvmap_handle; | | __in u32 nvmap_handle; |
− | __in u32 padding; | + | __in u32 map_offset; |
− | __in u32 offset; // (alloc_space_offset >> 0x10) | + | __in u32 gpu_offset; // (alloc_space_offset >> 0x10) |
− | __in u32 pages; // alloc_space_pages | + | __in u32 pages; // alloc_space_pages |
| }; | | }; |
| | | |
Line 979: |
Line 1,060: |
| | 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]] | | | 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]] |
| |- | | |- |
− | | 0xC0184706 || Inout || 24 || NVGPU_GPU_IOCTL_GET_TPC_MASKS | + | | 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]] |
| |- | | |- |
| | 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]] | | | 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]] |
| |- | | |- |
− | | 0x4008470D || In || 8 || NVGPU_GPU_IOCTL_INVAL_ICACHE | + | | 0x4008470D || In || 8 || [[#NVGPU_GPU_IOCTL_INVAL_ICACHE]] |
| |- | | |- |
− | | 0x4008470E || In || 8 || NVGPU_GPU_IOCTL_SET_MMUDEBUG_MODE | + | | 0x4008470E || In || 8 || [[#NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE]] |
| |- | | |- |
− | | 0x4010470F || In || 16 || NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE | + | | 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]] |
| |- | | |- |
− | | 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48 || NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE | + | | 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || [[#NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE]] |
| |- | | |- |
− | | 0x80084711 || Out || 8 || NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS | + | | 0x80084711 || Out || 8 || [[#NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS]] |
| |- | | |- |
− | | 0x80084712 || Out || 8 || NVGPU_GPU_IOCTL_NUM_VSMS | + | | 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]] |
| |- | | |- |
− | | 0xC0044713 || Inout || 4 || NVGPU_GPU_IOCTL_VSMS_MAPPING | + | | 0xC0044713 || Inout || 4 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]] |
| |- | | |- |
| | 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]] | | | 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]] |
| |- | | |- |
− | | 0x80044715 || Out || 4 || NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD | + | | 0x80044715 || Out || 4 || [[#NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD]] |
| |- | | |- |
− | | 0x40084716 || In || 8 || NVGPU_GPU_IOCTL_SET_CG_CONTROLS | + | | 0x40084716 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_CG_CONTROLS]] |
| |- | | |- |
− | | 0xC0084717 || Inout || 8 || NVGPU_GPU_IOCTL_GET_CG_CONTROLS | + | | 0xC0084717 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_CG_CONTROLS]] |
| |- | | |- |
− | | 0x40084718 || In || 8 || NVGPU_GPU_IOCTL_SET_PG_CONTROLS | + | | 0x40084718 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_PG_CONTROLS]] |
| |- | | |- |
− | | 0xC0084719 || Inout || 8 || NVGPU_GPU_IOCTL_GET_PG_CONTROLS | + | | 0xC0084719 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_PG_CONTROLS]] |
| |- | | |- |
− | | 0x8018471A || Out || 24 || NVGPU_GPU_IOCTL_PMU_DUMP_ELPG_STATS | + | | 0x8018471A || Out || 24 || [[#NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING]] |
| |- | | |- |
− | | 0xC008471B || Inout || 8 || NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA | + | | 0xC008471B || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA]] |
| |- | | |- |
− | | 0xC010471C || Inout || 16 || NVGPU_GPU_IOCTL_GET_GPU_TIME | + | | 0xC010471C || Inout || 16 || [[#NVGPU_GPU_IOCTL_GET_GPU_TIME]] |
| |- | | |- |
− | | 0xC108471D || Inout || 264 || NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO | + | | 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]] |
| |} | | |} |
| | | |
Line 1,067: |
Line 1,148: |
| === NVGPU_GPU_IOCTL_GET_CHARACTERISTICS === | | === NVGPU_GPU_IOCTL_GET_CHARACTERISTICS === |
| Returns the GPU characteristics. Modified to return inline data instead of using a pointer. | | Returns the GPU characteristics. Modified to return inline data instead of using a pointer. |
| + | |
| + | [3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]]. |
| | | |
| struct gpu_characteristics { | | struct gpu_characteristics { |
− | u32 arch; // 0x120 (NVGPU_GPU_ARCH_GM200) | + | u32 arch; // 0x120 (NVGPU_GPU_ARCH_GM200) |
− | u32 impl; // 0xB (NVGPU_GPU_IMPL_GM20B) | + | u32 impl; // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B) |
− | u32 rev; // 0xA1 (Revision A1) | + | u32 rev; // 0xA1 (Revision A1) |
− | u32 num_gpc; // 0x1 | + | u32 num_gpc; // 0x1 |
− | u64 l2_cache_size; // 0x40000 | + | u64 l2_cache_size; // 0x40000 |
− | u64 on_board_video_memory_size; // 0x0 (not used) | + | u64 on_board_video_memory_size; // 0x0 (not used) |
− | u32 num_tpc_per_gpc; // 0x2 | + | u32 num_tpc_per_gpc; // 0x2 |
− | u32 bus_type; // 0x20 (NVGPU_GPU_BUS_TYPE_AXI) | + | u32 bus_type; // 0x20 (NVGPU_GPU_BUS_TYPE_AXI) |
− | u32 big_page_size; // 0x20000 | + | u32 big_page_size; // 0x20000 |
− | u32 compression_page_size; // 0x20000 | + | u32 compression_page_size; // 0x20000 |
− | u32 pde_coverage_bit_count; // 0x1B | + | u32 pde_coverage_bit_count; // 0x1B |
− | u32 available_big_page_sizes; // 0x30000 | + | u32 available_big_page_sizes; // 0x30000 |
− | u32 gpc_mask; // 0x1 | + | u32 gpc_mask; // 0x1 |
− | u32 sm_arch_sm_version; // 0x503 (Maxwell Generation 5.0.3?) | + | u32 sm_arch_sm_version; // 0x503 (Maxwell Generation 5.0.3) |
− | u32 sm_arch_spa_version; // 0x503 (Maxwell Generation 5.0.3?) | + | u32 sm_arch_spa_version; // 0x503 (Maxwell Generation 5.0.3) |
− | u32 sm_arch_warp_count; // 0x80 | + | u32 sm_arch_warp_count; // 0x80 |
− | u32 gpu_va_bit_count; // 0x28 | + | u32 gpu_va_bit_count; // 0x28 |
− | u32 reserved; // NULL | + | u32 reserved; // NULL |
− | u64 flags; // 0x55 | + | u64 flags; // 0x55 (HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT) |
− | u32 twod_class; // 0x902D (FERMI_TWOD_A) | + | u32 twod_class; // 0x902D (FERMI_TWOD_A) |
− | u32 threed_class; // 0xB197 (MAXWELL_B) | + | u32 threed_class; // 0xB197 (MAXWELL_B) |
− | u32 compute_class; // 0xB1C0 (MAXWELL_COMPUTE_B) | + | u32 compute_class; // 0xB1C0 (MAXWELL_COMPUTE_B) |
− | u32 gpfifo_class; // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A) | + | u32 gpfifo_class; // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A) |
− | u32 inline_to_memory_class; // 0xA140 (KEPLER_INLINE_TO_MEMORY_B) | + | u32 inline_to_memory_class; // 0xA140 (KEPLER_INLINE_TO_MEMORY_B) |
− | u32 dma_copy_class; // 0xB0B5 (MAXWELL_DMA_COPY_A) | + | u32 dma_copy_class; // 0xB0B5 (MAXWELL_DMA_COPY_A) |
− | u32 max_fbps_count; // 0x1 | + | u32 max_fbps_count; // 0x1 |
− | u32 fbp_en_mask; // 0x0 (disabled) | + | u32 fbp_en_mask; // 0x0 (disabled) |
− | u32 max_ltc_per_fbp; // 0x2 | + | u32 max_ltc_per_fbp; // 0x2 |
− | u32 max_lts_per_ltc; // 0x1 | + | u32 max_lts_per_ltc; // 0x1 |
− | u32 max_tex_per_tpc; // 0x0 (not supported) | + | u32 max_tex_per_tpc; // 0x0 (not supported) |
− | u32 max_gpc_count; // 0x1 | + | u32 max_gpc_count; // 0x1 |
− | u32 rop_l2_en_mask_0; // 0x21D70 (fuse_status_opt_rop_l2_fbp_r) | + | u32 rop_l2_en_mask_0; // 0x21D70 (fuse_status_opt_rop_l2_fbp_r) |
− | u32 rop_l2_en_mask_1; // 0x0 | + | u32 rop_l2_en_mask_1; // 0x0 |
− | u64 chipname; // 0x6230326D67 ("gm20b") | + | u64 chipname; // 0x6230326D67 ("gm20b") |
− | u64 gr_compbit_store_base_hw; // 0x0 (not supported) | + | u64 gr_compbit_store_base_hw; // 0x0 (not supported) |
| }; | | }; |
| | | |
Line 1,110: |
Line 1,193: |
| __in u64 gpu_characteristics_buf_addr; // ignored, but must not be NULL | | __in u64 gpu_characteristics_buf_addr; // ignored, but must not be NULL |
| __out struct gpu_characteristics gc; | | __out struct gpu_characteristics gc; |
| + | }; |
| + | |
| + | === NVGPU_GPU_IOCTL_GET_TPC_MASKS === |
| + | Returns the TPC mask value for each GPC. Modified to return inline data instead of using a pointer. |
| + | |
| + | [3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]]. |
| + | |
| + | struct { |
| + | __in u32 mask_buf_size; // ignored, but must not be NULL |
| + | __in u32 reserved[3]; |
| + | __out u64 mask_buf; // receives one 32-bit TPC mask per GPC (GPC 0 and GPC 1) |
| }; | | }; |
| | | |
Line 1,117: |
Line 1,211: |
| struct { | | struct { |
| __in u32 flush; // l2_flush | l2_invalidate << 1 | fb_flush << 2 | | __in u32 flush; // l2_flush | l2_invalidate << 1 | fb_flush << 2 |
− | u32 reserved; | + | __in u32 reserved; |
| + | }; |
| + | |
| + | === NVGPU_GPU_IOCTL_INVAL_ICACHE === |
| + | Invalidates the GPU instruction cache. Identical to Linux driver. |
| + | |
| + | struct { |
| + | __in s32 channel_fd; |
| + | __in u32 reserved; |
| + | }; |
| + | |
| + | === NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE === |
| + | Sets the GPU MMU debug mode. Identical to Linux driver. |
| + | |
| + | struct { |
| + | __in u32 state; |
| + | __in u32 reserved; |
| + | }; |
| + | |
| + | === NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE === |
| + | Sets the GPU SM debug mode. Identical to Linux driver. |
| + | |
| + | struct { |
| + | __in s32 channel_fd; |
| + | __in u32 enable; |
| + | __in u64 sms; |
| + | }; |
| + | |
| + | === NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE === |
| + | Waits until all valid warps on the GPU SM are paused and returns their current state. |
| + | |
| + | struct { |
| + | __in u64 pwarpstate; |
| + | }; |
| + | |
| + | [6.1.0+] This command was modified to return inline data instead of using a pointer. |
| + | |
| + | struct { |
| + | __out u64 sm0_valid_warps; |
| + | __out u64 sm0_trapped_warps; |
| + | __out u64 sm0_paused_warps; |
| + | __out u64 sm1_valid_warps; |
| + | __out u64 sm1_trapped_warps; |
| + | __out u64 sm1_paused_warps; |
| + | }; |
| + | |
| + | === NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS === |
| + | Returns a mask value describing all active TPC exceptions. Identical to Linux driver. |
| + | |
| + | struct { |
| + | __out u64 tpc_exception_en_sm_mask; |
| + | }; |
| + | |
| + | === NVGPU_GPU_IOCTL_NUM_VSMS === |
| + | Returns the number of GPU SM units present. Identical to Linux driver. |
| + | |
| + | struct { |
| + | __out u32 num_vsms; |
| + | __out u32 reserved; |
| + | }; |
| + | |
| + | === NVGPU_GPU_IOCTL_VSMS_MAPPING === |
| + | Returns mapping information on each GPU SM unit. Modified to return inline data instead of using a pointer. |
| + | |
| + | struct { |
| + | __out u8 sm0_gpc_index; |
| + | __out u8 sm0_tpc_index; |
| + | __out u8 sm1_gpc_index; |
| + | __out u8 sm1_tpc_index; |
| }; | | }; |
| | | |
Line 1,127: |
Line 1,289: |
| __out u32 mask; | | __out u32 mask; |
| }; | | }; |
| + | |
| + | === NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD === |
| + | Returns the GPU load value from the PMU. |
| + | |
| + | struct { |
| + | __out u32 pmu_gpu_load; |
| + | }; |
| + | |
| + | === NVGPU_GPU_IOCTL_SET_CG_CONTROLS === |
| + | Sets the clock gate control value. |
| + | |
| + | struct { |
| + | __in u32 cg_mask; |
| + | __in u32 cg_value; |
| + | }; |
| + | |
| + | === NVGPU_GPU_IOCTL_GET_CG_CONTROLS === |
| + | Returns the clock gate control value. |
| + | |
| + | struct { |
| + | __in u32 cg_mask; |
| + | __out u32 cg_value; |
| + | }; |
| + | |
| + | === NVGPU_GPU_IOCTL_SET_PG_CONTROLS === |
| + | Sets the power gate control value. |
| + | |
| + | struct { |
| + | __in u32 pg_mask; |
| + | __in u32 pg_value; |
| + | }; |
| + | |
| + | === NVGPU_GPU_IOCTL_GET_PG_CONTROLS === |
| + | Returns the power gate control value. |
| + | |
| + | struct { |
| + | __in u32 pg_mask; |
| + | __out u32 pg_value; |
| + | }; |
| + | |
| + | === NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING === |
| + | Returns the GPU PMU ELPG residency gating values. |
| + | |
| + | struct { |
| + | __out u64 pg_ingating_time_us; |
| + | __out u64 pg_ungating_time_us; |
| + | __out u64 pg_gating_cnt; |
| + | }; |
| + | |
| + | === NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA === |
| + | Returns user specific data from the error channel, if one exists. |
| + | |
| + | struct { |
| + | __out u64 data; |
| + | }; |
| + | |
| + | === NVGPU_GPU_IOCTL_GET_GPU_TIME === |
| + | Returns the timestamp from the GPU's nanosecond timer (PTIMER). Identical to Linux driver. |
| + | |
| + | struct { |
| + | __out u64 gpu_timestamp; // raw GPU counter (PTIMER) value |
| + | __out u64 reserved; |
| + | }; |
| + | |
| + | === NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO === |
| + | Returns CPU/GPU timestamp pairs for correlation analysis. Identical to Linux driver. |
| + | |
| + | struct time_correlation_sample { |
| + | u64 cpu_timestamp; // from CPU's CNTPCT_EL0 register |
| + | u64 gpu_timestamp; // from GPU's PTIMER registers |
| + | }; |
| + | |
| + | struct { |
| + | __out struct time_correlation_sample samples[16]; // timestamp pairs |
| + | __in u32 count; // number of pairs to read |
| + | __in u32 source_id; // cpu clock source id (must be 1) |
| + | }; |
| | | |
| == Channels == | | == Channels == |
Line 1,136: |
Line 1,375: |
| | /dev/nvhost-gpu || GPU | | | /dev/nvhost-gpu || GPU |
| |- | | |- |
− | | /dev/nvhost-vic || Video Image Compositor | + | | /dev/nvhost-msenc || Video Encoder |
| |- | | |- |
| | /dev/nvhost-nvdec || Video Decoder | | | /dev/nvhost-nvdec || Video Decoder |
| |- | | |- |
| | /dev/nvhost-nvjpg || JPEG Decoder | | | /dev/nvhost-nvjpg || JPEG Decoder |
| + | |- |
| + | | /dev/nvhost-vic || Video Image Compositor |
| + | |- |
| + | | /dev/nvhost-display || Display |
| |} | | |} |
| | | |
Line 1,149: |
Line 1,392: |
| | 0xC0??0001 || Variable || NVHOST_IOCTL_CHANNEL_SUBMIT | | | 0xC0??0001 || Variable || NVHOST_IOCTL_CHANNEL_SUBMIT |
| |- | | |- |
− | | 0xC0080002 || 8 || NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT | + | | 0xC0080002 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]] |
| |- | | |- |
− | | 0xC0080003 || 8 || NVHOST_IOCTL_CHANNEL_GET_WAITBASE | + | | 0xC0080003 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]] |
| |- | | |- |
| | 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]] | | | 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]] |
| |- | | |- |
− | | 0x40040007 || 4 || NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT | + | | 0x40040007 || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]] |
| |- | | |- |
− | | 0x40080008 || 8 || NVHOST_IOCTL_CHANNEL_SET_CLK_RATE | + | | 0x40080008 || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]] |
| |- | | |- |
− | | 0xC0??0009 || Variable || NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER | + | | 0xC0??0009 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]] |
| |- | | |- |
− | | 0xC0??000A || Variable || NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER | + | | 0xC0??000A || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]] |
| |- | | |- |
− | | 0x00000013 || 0 || NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX | + | | 0x00000013 || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]] |
| |- | | |- |
− | | 0xC0080014 || 8 || NVHOST_IOCTL_CHANNEL_GET_CLK_RATE | + | | 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]] |
− | |-
| |
− | | 0xC0080023 || 8 || NVHOST_IOCTL_CHANNEL_GET_CLK_RATE_EX
| |
| |- | | |- |
| | 0xC0??0024 || Variable || NVHOST_IOCTL_CHANNEL_SUBMIT_EX | | | 0xC0??0024 || Variable || NVHOST_IOCTL_CHANNEL_SUBMIT_EX |
| |- | | |- |
− | | 0xC0??0025 || Variable || NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX | + | | 0xC0??0025 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]] |
| |- | | |- |
− | | 0xC0??0026 || Variable || NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX | + | | 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]] |
| |- style="border-top: double" | | |- style="border-top: double" |
| | 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]] | | | 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]] |
| |- | | |- |
− | | 0x40044803 || 4 || NVGPU_IOCTL_CHANNEL_SET_TIMEOUT | + | | 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]] |
| |- | | |- |
| | 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]] | | | 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]] |
| |- | | |- |
− | | 0x40184806 || || NVGPU_IOCTL_CHANNEL_WAIT | + | | 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]] |
| |- | | |- |
− | | 0xC0044807 || 4 || NVGPU_IOCTL_CHANNEL_CYCLE_STATS | + | | 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]] |
| |- | | |- |
| | 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]] | | | 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]] |
Line 1,189: |
Line 1,430: |
| | 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]] | | | 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]] |
| |- | | |- |
− | | 0x4008480A || || NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX | + | | 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]] |
| |- | | |- |
| | 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]] | | | 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]] |
Line 1,207: |
Line 1,448: |
| | 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]] | | | 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]] |
| |- | | |- |
− | | 0xC0104813 || 16 || NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT | + | | 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]] |
| |- | | |- |
− | | 0x80804816 || 128 || NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO | + | | 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]] |
| |- | | |- |
| | 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]] | | | 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]] |
Line 1,221: |
Line 1,462: |
| | 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_EX]] | | | 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_EX]] |
| |- | | |- |
− | | 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_EX2]] | + | | 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY_EX]] |
| |- | | |- |
| | 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]] | | | 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]] |
| |- style="border-top: double" | | |- style="border-top: double" |
− | | 0x40084714 || 8 || NVGPU_IOCTL_CHANNEL_SET_USER_DATA | + | | 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]] |
| |- | | |- |
− | | 0x80084715 || 8 || NVGPU_IOCTL_CHANNEL_GET_USER_DATA | + | | 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]] |
| |} | | |} |
| + | |
| + | === NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT === |
| + | Returns the current syncpoint value for a given module. Identical to Linux driver. |
| + | |
| + | struct { |
| + | __in u32 module_id; |
| + | __out u32 syncpt_value; |
| + | }; |
| + | |
| + | === NVHOST_IOCTL_CHANNEL_GET_WAITBASE === |
| + | Returns the current waitbase value for a given module. Always returns 0. |
| + | |
| + | struct { |
| + | __in u32 module_id; |
| + | __out u32 waitbase_value; |
| + | }; |
| | | |
| === NVHOST_IOCTL_CHANNEL_GET_MODMUTEX === | | === NVHOST_IOCTL_CHANNEL_GET_MODMUTEX === |
| Stubbed. Does a debug print and returns 0. | | Stubbed. Does a debug print and returns 0. |
| + | |
| + | === NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT === |
| + | Sets the submit timeout value for the channel. Identical to Linux driver. |
| + | |
| + | struct { |
| + | __in u32 timeout; |
| + | }; |
| + | |
| + | === NVHOST_IOCTL_CHANNEL_SET_CLK_RATE === |
| + | Sets the clock rate value for a given module. Identical to Linux driver. |
| + | |
| + | struct { |
| + | __in u32 clk_rate; |
| + | __in u32 module_id; |
| + | }; |
| + | |
| + | === NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER === |
| + | Uses '''nvmap_pin''' internally to pin a given number of nvmap handles to an appropriate device physical address. |
| + | |
| + | struct handle { |
| + | u32 handle_id_in; // nvmap handle to map |
| + | u32 phys_addr_out; // returned device physical address mapped to the handle |
| + | }; |
| + | |
| + | struct { |
| + | __in u32 num_handles; // number of nvmap handles to map |
| + | __in u32 reserved; // ignored |
| + | __in u8 is_compr; // memory to map is compressed |
| + | __in u8 padding[3]; // ignored |
| + | __inout struct handle handles[]; // depends on num_handles |
| + | }; |
| + | |
| + | === NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER === |
| + | Uses '''nvmap_unpin''' internally to unpin a given number of nvmap handles from their device physical address. |
| + | |
| + | struct handle { |
| + | u32 handle_id_in; // nvmap handle to unmap |
| + | u32 reserved; // ignored |
| + | }; |
| + | |
| + | struct { |
| + | __in u32 num_handles; // number of nvmap handles to unmap |
| + | __in u32 reserved; // ignored |
| + | __in u8 is_compr; // memory to unmap is compressed |
| + | __in u8 padding[3]; // ignored |
| + | __inout struct handle handles[]; // depends on num_handles |
| + | }; |
| + | |
| + | === NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX === |
| + | Sets the global timeout value for the channel. Identical to Linux driver. |
| + | |
| + | struct { |
| + | __in u32 timeout; |
| + | __in u32 flags; |
| + | }; |
| + | |
| + | === NVHOST_IOCTL_CHANNEL_GET_CLK_RATE === |
| + | Returns the clock rate value for a given module. Identical to Linux driver. |
| + | |
| + | struct { |
| + | __out u32 clk_rate; |
| + | __in u32 module_id; |
| + | }; |
| + | |
| + | === NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX === |
| + | Same as [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]], but calls '''nvmap_unpin''' internally in case of error. |
| + | |
| + | === NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX === |
| + | Same as [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]. |
| | | |
| === NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD === | | === NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD === |
| Binds a nvmap object to this channel. Identical to Linux driver. | | Binds a nvmap object to this channel. Identical to Linux driver. |
| | | |
− | This ioctl is a no-op in the Linux driver, not sure about Switch?
| + | struct { |
| + | __in u32 nvmap_fd; |
| + | }; |
| + | |
| + | === NVGPU_IOCTL_CHANNEL_SET_TIMEOUT === |
| + | Sets the timeout value for the GPU channel. Identical to Linux driver. |
| | | |
| struct { | | struct { |
− | __in u32 nvmap_fd; | + | __in u32 timeout; |
| }; | | }; |
| | | |
Line 1,248: |
Line 1,579: |
| __in u32 num_entries; | | __in u32 num_entries; |
| __in u32 flags; | | __in u32 flags; |
| + | }; |
| + | |
| + | === NVGPU_IOCTL_CHANNEL_WAIT === |
| + | Waits on channel. Identical to Linux driver. |
| + | |
| + | struct { |
| + | __in u32 type; // wait type (0=notifier, 1=semaphore) |
| + | __in u32 timeout; // wait timeout value |
| + | __in u32 dmabuf_fd; // nvmap handle |
| + | __in u32 offset; // nvmap memory offset |
| + | __in u32 payload; // payload data (semaphore only) |
| + | __in u32 padding; // ignored |
| + | }; |
| + | |
| + | === NVGPU_IOCTL_CHANNEL_CYCLE_STATS === |
| + | Maps memory for the cycle stats buffer. Identical to Linux driver. |
| + | |
| + | struct { |
| + | __in u32 dmabuf_fd; // nvmap handle |
| }; | | }; |
| | | |
Line 1,259: |
Line 1,609: |
| | | |
| struct gpfifo_entry { | | struct gpfifo_entry { |
− | u64 entry; // gpu_iova | (unk_2bits << 40) | (size << 42) | (unk_flag << 63) | + | u64 entry; // gpu_iova | (unk_2bits << 40) | (size << 42) | (unk_flag << 63) |
| }; | | }; |
| | | |
Line 1,266: |
Line 1,616: |
| __in u32 num_entries; // number of fence objects being submitted | | __in u32 num_entries; // number of fence objects being submitted |
| __in u32 flags; | | __in u32 flags; |
− | __inout struct fence fence_out; // returned new fence object for others to wait on | + | __inout struct fence fence_out; // returned new fence object for others to wait on |
− | __in struct gpfifo_entry entries[]; // depends on num_entries | + | __in struct gpfifo_entry entries[]; // depends on num_entries |
| }; | | }; |
| | | |
Line 1,279: |
Line 1,629: |
| __in u32 flags; // bit0: LOCKBOOST_ZERO | | __in u32 flags; // bit0: LOCKBOOST_ZERO |
| __out u64 obj_id; // (ignored) used for FREE_OBJ_CTX ioctl, which is not supported | | __out u64 obj_id; // (ignored) used for FREE_OBJ_CTX ioctl, which is not supported |
| + | }; |
| + | |
| + | === NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX === |
| + | Frees a graphics context object. Not supported. |
| + | |
| + | struct { |
| + | __in u64 obj_id; // ignored |
| }; | | }; |
| | | |
Line 1,287: |
Line 1,644: |
| __in u64 gpu_va; | | __in u64 gpu_va; |
| __in u32 mode; // 0=global, 1=no_ctxsw, 2=separate_buffer, 3=part_of_regular_buf | | __in u32 mode; // 0=global, 1=no_ctxsw, 2=separate_buffer, 3=part_of_regular_buf |
− | __in u32 padding; | + | __in u32 reserved; |
| }; | | }; |
| | | |
Line 1,294: |
Line 1,651: |
| | | |
| struct { | | struct { |
− | __in u64 offset; // ignored | + | __in u64 offset; // ignored |
− | __in u64 size; // ignored | + | __in u64 size; // ignored |
− | __in u32 mem; // must be non-zero to initialize, zero to de-initialize | + | __in u32 mem; // must be non-zero to initialize, zero to de-initialize |
− | __in u32 padding; // ignored | + | __in u32 reserved; // ignored |
| }; | | }; |
| | | |
Line 1,325: |
Line 1,682: |
| __in u32 cmd; // 0=disable, 1=enable, 2=clear | | __in u32 cmd; // 0=disable, 1=enable, 2=clear |
| __in u32 id; // same id's as for [[#QueryEvent]] | | __in u32 id; // same id's as for [[#QueryEvent]] |
| + | }; |
| + | |
| + | === NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT === |
| + | Controls the cycle stats snapshot buffer. Identical to Linux driver. |
| + | |
| + | struct { |
| + | __in u32 cmd; // command to handle (0=flush, 1=attach, 2=detach) |
| + | __in u32 dmabuf_fd; // nvmap handle |
| + | __inout u32 extra; // extra payload data/result |
| + | __in u32 padding; // ignored |
| + | }; |
| + | |
| + | === NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO === |
| + | Returns information on the current error notification caught by the error notifier. Exclusive to the Switch. |
| + | |
| + | struct { |
| + | __out u32 error_info[32]; // first word is an error code (0=no_error, 1=gr_error, 2=gr_error, 3=invalid, 4=invalid) |
| }; | | }; |
| | | |
| === NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION === | | === NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION === |
| Returns the current error notification caught by the error notifier. Exclusive to the Switch. | | Returns the current error notification caught by the error notifier. Exclusive to the Switch. |
− |
| |
− | Despite being marked as inout this is all output.
| |
| | | |
| struct { | | struct { |
Line 1,342: |
Line 1,714: |
| Allocates gpfifo entries with additional parameters. Exclusive to the Switch. | | Allocates gpfifo entries with additional parameters. Exclusive to the Switch. |
| | | |
− | struct {
| + | struct fence { |
− | __in u32 num_entries;
| + | u32 syncpt_id; |
− | __in u32 flags;
| + | u32 syncpt_value; |
− | __in u32 unk0; // 1 works
| + | }; |
− | __in u32 unk1;
| + | |
− | __in u32 unk2;
| + | struct { |
− | __in u32 unk3;
| + | __in u32 num_entries; |
− | __in u32 unk4;
| + | __in u32 num_jobs; |
− | __in u32 unk5;
| + | __in u32 flags; |
− | };
| + | __out struct fence fence_out; // returned new fence object for others to wait on |
| + | __in u32 reserved[3]; // ignored |
| + | }; |
| | | |
| === NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY === | | === NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY === |
− | Submits a gpfifo object (async version). Exclusive to the Switch.
| + | Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]. |
− | | |
− | struct {
| |
− | u64 __gpfifo; // in (pointer to gpfifo fence structs; ignored)
| |
− | u32 __num_entries; // in (number of fence objects being submitted)
| |
− | u32 __flags; // in
| |
− | struct fence __fence_out; // out (returned new fence object for others to wait on)
| |
− | struct gpfifo_entry __entries[]; // in (depends on __num_entries)
| |
− | };
| |
| | | |
| === NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2 === | | === NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2 === |
− | Allocates gpfifo entries with additional parameters and returns a fence. Exclusive to the Switch.
| + | Same as [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX|NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]. |
− |
| |
− | struct {
| |
− | u32 __num_entries; // in
| |
− | u32 __flags; // in
| |
− | u32 __unk0; // in (1 works)
| |
− | struct fence __fence_out; // out
| |
− | u32 __unk1; // in
| |
− | u32 __unk2; // in
| |
− | u32 __unk3; // in
| |
− | };
| |
| | | |
| === NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_EX === | | === NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_EX === |
− | Identical to [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]. Uses [[#Ioctl2|Ioctl2]].
| + | Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]], but uses [[#Ioctl2|Ioctl2]]. |
| | | |
− | === NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_EX2 === | + | === NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY_EX === |
− | Identical to [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]. Uses [[#Ioctl2|Ioctl2]].
| + | Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]], but uses [[#Ioctl2|Ioctl2]]. |
| | | |
| === NVGPU_IOCTL_CHANNEL_SET_TIMESLICE === | | === NVGPU_IOCTL_CHANNEL_SET_TIMESLICE === |
Line 1,388: |
Line 1,744: |
| struct { | | struct { |
| __in u32 timeslice; | | __in u32 timeslice; |
| + | }; |
| + | |
| + | === NVGPU_IOCTL_CHANNEL_SET_USER_DATA === |
| + | Sets user specific data. |
| + | |
| + | struct { |
| + | __in u64 data; |
| + | }; |
| + | |
| + | === NVGPU_IOCTL_CHANNEL_GET_USER_DATA === |
| + | Returns user specific data. |
| + | |
| + | struct { |
| + | __out u64 data; |
| }; | | }; |
| | | |
| = nvmemp = | | = nvmemp = |
| NVIDIA memory profiler (this service is not available on retail units). | | NVIDIA memory profiler (this service is not available on retail units). |
− | /dev/nvhost-ctrl sends the ioctl NVHOST_IOCTL_CTRL_GET_CONFIG to check the config "nv!NV_MEMORY_PROFILER". If config_str returns "1", the applications attempts to talk to use nvmemp. | + | /dev/nvhost-ctrl sends the ioctl NVHOST_IOCTL_CTRL_GET_CONFIG to check the config "nv!NV_MEMORY_PROFILER". If config_str returns "1", the application attempts to use nvmemp. |
| | | |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
Line 1,400: |
Line 1,770: |
| | 0 || Open | | | 0 || Open |
| |- | | |- |
− | | 1 || GetPid | + | | 1 || GetAruid |
| |} | | |} |
| | | |
Line 1,410: |
Line 1,780: |
| ! Cmd || Name | | ! Cmd || Name |
| |- | | |- |
− | | 0 || [[#OpenLog]] | + | | 0 || [[#OpenDebugFS]] |
| |- | | |- |
− | | 1 || [[#CloseLog]] | + | | 1 || [[#CloseDebugFS]] |
| |- | | |- |
− | | 2 || [[#ReadLog]] | + | | 2 || [[#GetDebugFSKeys]] |
| |- | | |- |
− | | 3 || | + | | 3 || GetDebugFSValue |
| |- | | |- |
− | | 4 || | + | | 4 || SetDebugFSValue |
| |} | | |} |
| | | |
− | == OpenLog == | + | == OpenDebugFS == |
− | Takes process handle. Returns an fd. | + | Takes a process handle. Returns a u32 '''fd'''. |
| | | |
− | == CloseLog == | + | == CloseDebugFS == |
− | Takes fd and closes it. | + | Takes a u32 '''fd''' and closes it. |
| | | |
− | == ReadLog == | + | == GetDebugFSKeys == |
− | Takes fd and reads log into a type-6 buffer. | + | Takes a u32 '''fd''' and reads debug contents into a type-6 buffer. |
| | | |
| = nvgem:c = | | = nvgem:c = |
Line 1,437: |
Line 1,807: |
| ! Cmd || Name | | ! Cmd || Name |
| |- | | |- |
− | | 0 || | + | | 0 || Initialize |
| |- | | |- |
− | | 1 || | + | | 1 || GetGemEvent |
| |- | | |- |
− | | 2 || | + | | 2 || |
| |- | | |- |
− | | 3 || | + | | 3 || RegisterUnregisterAppIdLocked |
| |- | | |- |
| | 4 || | | | 4 || |
| |- | | |- |
− | | [1.0.0-4.1.0] 5 || | + | | [1.0.0-4.1.0] 5 || GetAruid |
| |- | | |- |
− | | 6 || | + | | 6 || HandleDeferredErrors |
| |- | | |- |
| | 7 || [3.0.0+] | | | 7 || [3.0.0+] |
Line 1,461: |
Line 1,831: |
| ! Cmd || Name | | ! Cmd || Name |
| |- | | |- |
− | | 0 || | + | | 0 || Initialize |
| |- | | |- |
− | | 1 || | + | | 1 || GetAruid |
| |- | | |- |
− | | 2 || | + | | [1.0.0-8.1.0] 2 || ReadNextCdBlock |
| |- | | |- |
| | 3 || [8.0.0+] | | | 3 || [8.0.0+] |