Nintendo Switch Brew

NV services: Difference between revisions

← Older editNewer edit →
(28 intermediate revisions by 4 users not shown)
Line 7: Line 7:


Each service is used by:
Each service is used by:
* "nvdrv": regular applications
* "nvdrv": Applications.
* "nvdrv:a": applets
** [[#Permissions|Permission]] mask is [3.0.0+] 0xA82B ([1.0.0-2.3.0] 0x2B).
* "nvdrv:s": sysmodules
* "nvdrv:a": Applets.
* "nvdrv:t": factory titles
** [[#Permissions|Permission]] mask is [3.0.0+] 0x10A9 ([1.0.0-2.3.0] 0xA9).
* "nvdrv:s": Sysmodules.
** [[#Permissions|Permission]] mask is [3.0.0+] 0x439E ([1.0.0-2.3.0] 0x39E).
* "nvdrv:t": Factory.
** [[#Permissions|Permission]] mask is 0xFFFFFFFF.


{| class="wikitable" border="1"
{| class="wikitable" border="1"
Line 30: Line 34:
| 6 || [[#GetStatus]]
| 6 || [[#GetStatus]]
|-
|-
| 7 || [[#SetAruid]]
| 7 || [[#SetAruidWithoutCheck]]
|-
|-
| 8 || [[#SetAruidByPID]]
| 8 || [[#SetAruid]]
|-
|-
| 9 || [[#DumpGraphicsMemoryInfo]]
| 9 || [[#DumpStatus]]
|-
|-
| 10 || [3.0.0+] [[#InitializeDevtools]]
| 10 || [3.0.0+] [[#InitializeDevtools]]
Line 42: Line 46:
| 12 || [3.0.0+] [[#Ioctl3]]
| 12 || [3.0.0+] [[#Ioctl3]]
|-
|-
| 13 || [3.0.0+] [[#FinishInitialize]]
| 13 || [3.0.0+] [[#SetGraphicsFirmwareMemoryMarginEnabled]]
|}
|}


Line 84: Line 88:
Takes no input. Returns 0x10-bytes and an output u32 ('''error_code''').
Takes no input. Returns 0x10-bytes and an output u32 ('''error_code''').


== SetAruid ==
== SetAruidWithoutCheck ==
Takes an input u64 which must [[IPC_Marshalling|match]] the user-process PID ([[Applet_Manager_services#AppletResourceUserId|AppletResourceUserId]]). Returns an output u32 ('''error_code''').
Takes an input u64 which must [[IPC_Marshalling|match]] the user-process PID ([[Applet_Manager_services#AppletResourceUserId|AppletResourceUserId]]). Returns an output u32 ('''error_code''').


== SetAruidByPID ==
== SetAruid ==
Takes a PID-descriptor and an u64 which must [[IPC_Marshalling|match]] the user-process PID ([[Applet_Manager_services#AppletResourceUserId|AppletResourceUserId]]). Returns an output u32 ('''error_code''').
Takes a PID-descriptor and an u64 which must [[IPC_Marshalling|match]] the user-process PID ([[Applet_Manager_services#AppletResourceUserId|AppletResourceUserId]]). Returns an output u32 ('''error_code''').


== DumpGraphicsMemoryInfo ==
== DumpStatus ==
No input or output. Does nothing.
No input or output.


== InitializeDevtools ==
== InitializeDevtools ==
Takes a copy-handle and an input u32. Returns an output u32 ('''error_code''').
Takes a copy-handle ('''transfer_memory''') and an input u32 ('''transfer_memory_size'''). Returns an output u32 ('''error_code''').


== Ioctl2 ==
== Ioctl2 ==
Line 103: Line 107:
Cmdhdr_word1 is 0x100B instead of 0xC0B.
Cmdhdr_word1 is 0x100B instead of 0xC0B.


== FinishInitialize ==
== SetGraphicsFirmwareMemoryMarginEnabled ==
Takes an input u64. No output.
Takes an input u64. No output.


Line 109: Line 113:


Official user-processes starting with 3.0.0 now use this at the end of nvdrv service init with value 0x1.
Official user-processes starting with 3.0.0 now use this at the end of nvdrv service init with value 0x1.
= Permissions =
Each nvdrv service is initialized with a bitfield that controls access to nodes and other operations.
{| class="wikitable" border="1"
!  Bits
!  Name
!  Description
|-
| 0
| NvDrvPermission_Gpu
| Can access [[#Channels|/dev/nvhost-gpu]], [[#/dev/nvhost-ctrl-gpu|/dev/nvhost-ctrl-gpu]] and [[#/dev/nvhost-as-gpu|/dev/nvhost-as-gpu]].
|-
| 1
| NvDrvPermission_GpuDebug
| Can access [[#/dev/nvhost-dbg-gpu|/dev/nvhost-dbg-gpu]] and [[#/dev/nvhost-prof-gpu|/dev/nvhost-prof-gpu]].
|-
| 2
| NvDrvPermission_GpuSchedule
| Can access [[#/dev/nvsched-ctrl|/dev/nvsched-ctrl]].
|-
| 3
| NvDrvPermission_VIC
| Can access [[#Channels|/dev/nvhost-vic]].
|-
| 4
| NvDrvPermission_VideoEncoder
| Can access [[#Channels|/dev/nvhost-msenc]].
|-
| 5
| NvDrvPermission_VideoDecoder
| Can access [[#Channels|/dev/nvhost-nvdec]].
|-
| 6
| NvDrvPermission_TSEC
| Can access [[#Channels|/dev/nvhost-tsec]].
|-
| 7
| NvDrvPermission_JPEG
| Can access [[#Channels|/dev/nvhost-nvjpg]].
|-
| 8
| NvDrvPermission_Display
| Can access [[#Channels|/dev/nvhost-display]], [[#/dev/nvcec-ctrl|/dev/nvcec-ctrl]], [[#/dev/nvhdcp_up-ctrl|/dev/nvhdcp_up-ctrl]], [[#/dev/nvdisp-ctrl|/dev/nvdisp-ctrl]], [[#/dev/nvdisp-disp0, /dev/nvdisp-disp1|/dev/nvdisp-disp0]], [[#/dev/nvdisp-disp0, /dev/nvdisp-disp1|/dev/nvdisp-disp1]], [[#/dev/nvdcutil-disp0, /dev/nvdcutil-disp1|/dev/nvdcutil-disp0]] and [[#/dev/nvdcutil-disp0, /dev/nvdcutil-disp1|/dev/nvdcutil-disp1]].
|-
| 9
| NvDrvPermission_ImportMemory
| Can duplicate [[#/dev/nvmap|nvmap]] handles from other processes with [[#NVMAP_IOC_FROM_ID|NVMAP_IOC_FROM_ID]].
|-
| 10
| NvDrvPermission_NoCheckedAruid
| Can use [[#SetAruidWithoutCheck|SetAruidWithoutCheck]].
|-
| 11
|
| Can use [[#SetGraphicsFirmwareMemoryMarginEnabled|SetGraphicsFirmwareMemoryMarginEnabled]].
|-
| 12
|
| Can duplicate exported [[#/dev/nvmap|nvmap]] handles from other processes with [[#NVMAP_IOC_FROM_ID|NVMAP_IOC_FROM_ID]].
|-
| 13
|
|
|-
| 14
|
| Can use [[#NVMAP_IOC_EXPORT_FOR_ARUID|NVMAP_IOC_EXPORT_FOR_ARUID]] and [[#NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID|NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID]].
|-
| 15
|
|
|}
Nodes [[#/dev/nvmap|/dev/nvmap]], [[#/dev/nvhost-ctrl|/dev/nvhost-ctrl]] and [[#/dev/nverpt-ctrl|/dev/nverpt-ctrl]] are always accessible.


= Ioctls =
= Ioctls =
Line 138: Line 217:
| 0xC183001B || Inout || 387 || [[#NVHOST_IOCTL_CTRL_GET_CONFIG]]
| 0xC183001B || Inout || 387 || [[#NVHOST_IOCTL_CTRL_GET_CONFIG]]
|-
|-
| 0xC004001C || Inout || 4 || [[#NVHOST_IOCTL_CTRL_EVENT_SIGNAL]]
| 0xC004001C || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_CLEAR_EVENT_WAIT]]
|-
|-
| 0xC010001D || Inout || 16 || [[#NVHOST_IOCTL_CTRL_EVENT_WAIT]]
| 0xC010001D || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_EVENT_WAIT]]
|-
|-
| 0xC010001E || Inout || 16 || [[#NVHOST_IOCTL_CTRL_EVENT_WAIT_ASYNC]]
| 0xC010001E || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_EVENT_WAIT_ASYNC]]
|-
|-
| 0xC004001F || Inout || 4 || [[#NVHOST_IOCTL_CTRL_EVENT_REGISTER]]
| 0xC004001F || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_REGISTER_EVENT]]
|-
|-
| 0xC0040020 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_EVENT_UNREGISTER]]
| 0xC0040020 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_UNREGISTER_EVENT]]
|-
|-
| 0x40080021 || In || 8 || [[#NVHOST_IOCTL_CTRL_EVENT_KILL]]
| 0x40080021 || In || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENTS]]
|-
|-
| 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_GET_MAX_EVENT_FIFO_CHANNEL]]
| 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_GET_MAX_EVENT_FIFO_CHANNEL]]
Line 216: Line 295:


=== NVHOST_IOCTL_CTRL_GET_CONFIG ===
=== NVHOST_IOCTL_CTRL_GET_CONFIG ===
Gets configured settings. Not available in production mode.
Returns configured settings. Not available in production mode.


   struct {
   struct {
Line 224: Line 303:
   };
   };


=== NVHOST_IOCTL_CTRL_EVENT_SIGNAL ===
=== NVHOST_IOCTL_CTRL_SYNCPT_CLEAR_EVENT_WAIT ===
Signals an user event. Exclusive to the Switch.
Clears the wait signal of an event. Exclusive to the Switch.


   struct {
   struct {
     __in u32 user_event_id;     // ranges from 0x00 to 0x3F
     __in u32 event_slot;         // ranges from 0x00 to 0x3F
   };
   };


=== NVHOST_IOCTL_CTRL_EVENT_WAIT ===
=== NVHOST_IOCTL_CTRL_SYNCPT_EVENT_WAIT ===
Waits on an event. If waiting fails, returns error code 0x05 (Timeout) and sets '''value''' to (('''syncpt_id''' << 0x10) | 0x10000000).
Waits on an event. If waiting fails, returns error code 0x05 (Timeout) and sets '''value''' to (('''syncpt_id''' << 0x10) | 0x10000000).


Depending on '''threshold''', an '''user_event_id''' may be returned for using with other event ioctls.
Depending on '''threshold''', an '''event_slot''' may be returned for using with other event ioctls.


   struct {
   struct {
Line 240: Line 319:
     __in    u32 threshold;
     __in    u32 threshold;
     __in    s32 timeout;
     __in    s32 timeout;
     __inout u32 value;          // in=user_event_id (ignored); out=syncpt_value or user_event_id
     __inout u32 value;          // in=event_slot (ignored); out=syncpt_value or event_slot
   };
   };


=== NVHOST_IOCTL_CTRL_EVENT_WAIT_ASYNC ===
=== NVHOST_IOCTL_CTRL_SYNCPT_EVENT_WAIT_ASYNC ===
Waits on an event (async version). If waiting fails, returns error code 0x0B (BadValue).
Waits on an event (async version). If waiting fails, returns error code 0x0B (BadValue).


Depending on '''threshold''', an '''user_event_id''' may be returned for using with other event ioctls.
Depending on '''threshold''', an '''event_slot''' may be returned for using with other event ioctls.


   struct {
   struct {
Line 252: Line 331:
     __in    u32 threshold;
     __in    u32 threshold;
     __in    u32 timeout;
     __in    u32 timeout;
     __inout u32 value;          // in=user_event_id (ignored); out=syncpt_value or user_event_id
     __inout u32 value;          // in=event_slot (ignored); out=syncpt_value or event_slot
   };
   };


=== NVHOST_IOCTL_CTRL_EVENT_REGISTER ===
=== NVHOST_IOCTL_CTRL_SYNCPT_REGISTER_EVENT ===
Registers an user event. Exclusive to the Switch.  
Registers an event. Exclusive to the Switch.  


   struct {
   struct {
     __in u32 user_event_id;     // ranges from 0x00 to 0x3F
     __in u32 event_slot;         // ranges from 0x00 to 0x3F
   };
   };


=== NVHOST_IOCTL_CTRL_EVENT_UNREGISTER ===
=== NVHOST_IOCTL_CTRL_SYNCPT_UNREGISTER_EVENT ===
Unregisters an user event. Exclusive to the Switch.  
Unregisters an event. Exclusive to the Switch.  


   struct {
   struct {
     __in u32 user_event_id;     // ranges from 0x00 to 0x3F
     __in u32 event_slot;         // ranges from 0x00 to 0x3F
   };
   };


=== NVHOST_IOCTL_CTRL_EVENT_KILL ===
=== NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENTS ===
Kills user events. Exclusive to the Switch.  
Frees events. Exclusive to the Switch.  


   struct {
   struct {
     __in u64 user_events;       // 64-bit bitfield where each bit represents one event
     __in u64 events;             // 64-bit bitfield where each bit represents one event
   };
   };


Line 280: Line 359:


   struct {
   struct {
     __out u32 max_channel;     // 0x00 (FIFO disabled) or 0x60 (FIFO enabled)
     __out u32 max_channel;       // 0x00 (FIFO disabled) or 0x60 (FIFO enabled)
   };
   };


Line 366: Line 445:
     __in  u32 handle;
     __in  u32 handle;
     u32      pad;
     u32      pad;
     __out u64 refcount;
     __out u64 address;
     __out u32 size;
     __out u32 size;
     __out u32 flags;    // 1=NOT_FREED_YET
     __out u32 flags;    // 1=NOT_FREED_YET
Line 449: Line 528:
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0x80040212 || Out || 4 || NVDISP_CTRL_GET_NUM_OUTPUTS
| 0x80040212 || Out || 4 || NVDISP_CTRL_NUM_OUTPUTS
|-
|-
| 0xC0140213 || Inout || 20 || NVDISP_CTRL_GET_OUTPUT_PROPERTIES
| 0xC0140213 || Inout || 20 || NVDISP_CTRL_GET_DISPLAY_PROPERTIES
|-
|-
| 0xC1100214 || Inout || 272 || NVDISP_CTRL_GET_OUTPUT_EDID
| 0xC1100214 || Inout || 272 || NVDISP_CTRL_QUERY_EDID
|-
|-
| 0xC0080216</br>([1.0.0-3.0.0] 0xC0040216) || Inout || 8</br>([1.0.0-3.0.0] 4) || NVDISP_CTRL_GET_EXT_HPD_IN_OUT_EVENTS</br>([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_IN_EVENT)
| 0xC0080216</br>([1.0.0-3.0.0] 0xC0040216) || Inout || 8</br>([1.0.0-3.0.0] 4) || NVDISP_CTRL_GET_EXT_HPD_IN_OUT_EVENTS</br>([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_IN_EVENT)
Line 463: Line 542:
| 0xC0100219 || Inout || 16 || NVDISP_CTRL_GET_VBLANK_HEAD1_EVENT
| 0xC0100219 || Inout || 16 || NVDISP_CTRL_GET_VBLANK_HEAD1_EVENT
|-
|-
| 0xC0040220 || Inout || 4 || NVDISP_CTRL_GET_HPD_IRQ
| 0xC0040220 || Inout || 4 || NVDISP_CTRL_SUSPEND
|}
|}


Line 482: Line 561:
| 0x430C0206 || In || 780 || NVDISP_SET_LUT
| 0x430C0206 || In || 780 || NVDISP_SET_LUT
|-
|-
| 0x40010207 || In || 1 || NVDISP_ENABLE_DISABLE_CRC
| 0x40010207 || In || 1 || NVDISP_CONFIG_CRC
|-
|-
| 0x80040208 || Out || 4 || NVDISP_GET_CRC
| 0x80040208 || Out || 4 || NVDISP_GET_CRC
Line 517: Line 596:
|-
|-
| 0xC004021F || Inout || 4 || NVDISP_GET_WINMASK
| 0xC004021F || Inout || 4 || NVDISP_GET_WINMASK
|-
| 0x80080221 || Out || 8 || [10.0.0+] NVDISP_GET_BACKLIGHT_RANGE
|-
| 0x40040222 || In || 4 || [10.0.0+] NVDISP_SET_BACKLIGHT
|}
|}


Line 542: Line 625:
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0xC4880401 || Inout || 1160 || NVHDCP_READ_M
| 0xC4880401 || Inout || 1160 || NVHDCP_READ_STATUS
|-
|-
| 0xC4880402 || Inout || 1160 || NVHDCP_READ_S
| 0xC4880402 || Inout || 1160 || NVHDCP_READ_M
|-
|-
| 0x40010403 || In || 1 || NVHDCP_ON_OFF
| 0x40010403 || In || 1 || NVHDCP_USER_ENABLE
|-
|-
| 0xC0080404 || Inout || 8 || NVHDCP_READ_EVENT
| 0xC0080404 || Inout || 8 || NVHDCP_READ_EVENT
|-
|-
| 0xC0010405 || Inout || 1 || NVHDCP_EVENTS_ON_OFF
| 0xC0010405 || Inout || 1 || NVHDCP_EVENTS_ENABLE
|}
|}


Line 557: Line 640:
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0x40010501 || In || 1 || NVDCUTIL_SW_HOTPLUG_IN_OUT
| 0x40010501 || In || 1 || NVDCUTIL_SW_HOTPLUG
|-
|-
| 0x40010502 || In || 1 || NVDCUTIL_VIRTUAL_EDID_ON_OFF
| 0x40010502 || In || 1 || NVDCUTIL_VIRTUAL_EDID_ENABLE
|-
|-
| 0x42040503 || In || 1056 || NVDCUTIL_VIRTUAL_EDID_SET_DATA
| 0x42040503 || In || 1056 || NVDCUTIL_VIRTUAL_EDID_SET_DATA
Line 565: Line 648:
| 0x803C0504 || Out || 60 || NVDCUTIL_GET_MODE
| 0x803C0504 || Out || 60 || NVDCUTIL_GET_MODE
|-
|-
| 0x40010505 || In || 1 || NVDCUTIL_TELEMETRY_TEST_ON_OFF
| 0x40010505 || In || 1 || NVDCUTIL_TELEMETRY_TEST_ENABLE
|-
|-
| 0x400C0506 || In || 12 || NVDCUTIL_DSI_PACKET_SHORT_WRITE
| 0x400C0506 || In || 12 || NVDCUTIL_DSI_PACKET_SHORT_WRITE
Line 572: Line 655:
|-
|-
| 0xC0F40508 || Inout || 244 || NVDCUTIL_DSI_PACKET_READ
| 0xC0F40508 || Inout || 244 || NVDCUTIL_DSI_PACKET_READ
|-
| 0x40010509 || In || 1 || [10.0.0+] NVDCUTIL_DP_ELEC_TEST_MODE_ENABLE
|-
| 0xC020050A || Inout || 32 || [10.0.0+] NVDCUTIL_DP_ELEC_TEST_SETTINGS
|}
|}


Line 612: Line 699:
| 0x4008060F || In || 8 || [[#NVSCHED_CTRL_DETACH_APPLICATION]]
| 0x4008060F || In || 8 || [[#NVSCHED_CTRL_DETACH_APPLICATION]]
|-
|-
| 0x40100610 || In || 16 || NVSCHED_CTRL_LINK_RUNLIST_EX
| 0x40100610 || In || 16 || NVSCHED_CTRL_SET_APPLICATION_MAX_DEBT
|-
|-
| 0x40100611 || In || 16 || NVSCHED_CTRL_UNLINK_RUNLIST_EX
| 0x40100611 || In || 16 || NVSCHED_CTRL_SET_RUNLIST_MAX_DEBT
|-
|-
| 0x40010612 || In || 1 || NVSCHED_CTRL_OVERRUN_EVENTS_ON_OFF
| 0x40010612 || In || 1 || NVSCHED_CTRL_OVERRUN_EVENTS_ENABLE
|}
|}


Line 718: Line 805:
   struct {
   struct {
     __in u32 fence_id;
     __in u32 fence_id;
     __in u32 fence_value;
     __in u32 fence_thresh;
     __in u32 swap_interval;
     __in u32 swap_interval;
   };
   };
Line 812: Line 899:
| 0xC0084105 || Inout || 8 || [[#NVGPU_AS_IOCTL_UNMAP_BUFFER]]
| 0xC0084105 || Inout || 8 || [[#NVGPU_AS_IOCTL_UNMAP_BUFFER]]
|-
|-
| 0xC0284106 || Inout || 40 || [[#NVGPU_AS_IOCTL_MODIFY]]
| 0xC0284106 || Inout || 40 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX]]
|-
|-
| 0x40104107 || In || 16 || [[#NVGPU_AS_IOCTL_INITIALIZE]]
| 0x40104107 || In || 16 || [[#NVGPU_AS_IOCTL_ALLOC_AS]]
|-
|-
| 0xC0404108 || Inout || 64 || [[#NVGPU_AS_IOCTL_GET_VA_REGIONS]]
| 0xC0404108 || Inout || 64 || [[#NVGPU_AS_IOCTL_GET_VA_REGIONS]]
|-
|-
| 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_INITIALIZE_EX]]
| 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX]]
|-
|-
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX]]
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MODIFY]]
|-
|-
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]
Line 829: Line 916:


   struct {
   struct {
     __in u32 fd;
     __in u32 channel_fd;
   };
   };


Line 839: Line 926:
     __in u32 page_size;
     __in u32 page_size;
     __in u32 flags;
     __in u32 flags;
     u32      pad;
     u32      padding;
     union {
     union {
       __out u64 offset;
       __out u64 offset;
Line 858: Line 945:
Maps a memory region in the device address space. Identical to Linux driver pretty much.
Maps a memory region in the device address space. Identical to Linux driver pretty much.


On success, the mapped memory region is locked by having [[SVC#MemoryState]] bit34 set.
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.


   struct {
   struct {
     __in    u32 flags;        // bit0: fixed_offset, bit2: cacheable
     __in    u32 flags;        // bit0: fixed_offset, bit2: cacheable
     u32        pad;
     u32        reserved;
     __in    u32 nvmap_handle;
     __in    u32 dmabuf_fd;   // nvmap handle
     __inout u32 page_size;    // 0 means don't care
     __inout u32 page_size;    // 0 means don't care
     union {
     union {
Line 871: Line 958:
   };
   };


=== NVGPU_AS_IOCTL_MODIFY ===
=== NVGPU_AS_IOCTL_MAP_BUFFER_EX ===
Modifies a memory region in the device address space.
Maps a memory region in the device address space with extra params.


Unaligned size will cause a [[#Panic]].
Unaligned size will cause a [[#Panic]].


On success, the mapped memory region is locked by having [[SVC#MemoryState]] bit34 set.
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.


   struct {
   struct {
     __in      u32 flags;          // bit0: fixed_offset, bit2: cacheable
     __in      u32 flags;          // bit0: fixed_offset, bit2: cacheable
     __in      u32 kind;          // -1 is default
     __in      u32 kind;          // -1 is default
     __in      u32 nvmap_handle;
     __in      u32 dmabuf_fd;     // nvmap handle
     __inout  u32 page_size;      // 0 means don't care
     __inout  u32 page_size;      // 0 means don't care
     __in      u64 buffer_offset;
     __in      u64 buffer_offset;
Line 895: Line 982:
   };
   };


=== NVGPU_AS_IOCTL_INITIALIZE ===
=== NVGPU_AS_IOCTL_ALLOC_AS ===
Nintendo's custom implementation of NVGPU_GPU_IOCTL_ALLOC_AS (unavailable).
Nintendo's custom implementation for allocating an address space.


   struct {
   struct {
     __in u32 big_page_size;  // depends on GPU's available_big_page_sizes; 0=default
     __in u32 big_page_size;  // depends on GPU's available_big_page_sizes; 0=default
     __in s32 as_fd;          // ignored; passes 0
     __in s32 as_fd;          // ignored; passes 0
     __in u32 flags;          // ignored; passes 0
     __in u64 reserved;        // ignored; passes 0
    __in u32 reserved;        // ignored; passes 0
   };
   };


Line 911: Line 997:
     u64 offset;
     u64 offset;
     u32 page_size;
     u32 page_size;
     u32 pad;
     u32 reserved;
     u64 pages;
     u64 pages;
   };
   };
    
    
   struct {
   struct {
     u64          not_used;   // (contained output user ptr on linux, ignored)
     u64          buf_addr;   // (contained output user ptr on linux, ignored)
     __inout u32  bufsize;    // forced to 2*sizeof(struct va_region)
     __inout u32  buf_size;    // forced to 2*sizeof(struct va_region)
     u32          pad;
     u32          reserved;
     __out struct  va_region regions[2];
     __out struct  va_region regions[2];
   };
   };


=== NVGPU_AS_IOCTL_INITIALIZE_EX ===
=== NVGPU_AS_IOCTL_ALLOC_AS_EX ===
Nintendo's custom implementation of NVGPU_GPU_IOCTL_ALLOC_AS (unavailable) with extra params.
Nintendo's custom implementation for allocating an address space with extra params.


   struct {
   struct {
Line 930: Line 1,016:
     __in u32 flags;          // passes 0
     __in u32 flags;          // passes 0
     __in u32 reserved;        // ignored; passes 0
     __in u32 reserved;        // ignored; passes 0
     __in u64 unk0;
     __in u64 va_range_start;
     __in u64 unk1;
     __in u64 va_range_end;
     __in u64 unk2;
     __in u64 va_range_split;
   };
   };


=== NVGPU_AS_IOCTL_MAP_BUFFER_EX ===
=== NVGPU_AS_IOCTL_MODIFY ===
Maps a memory region in the device address space with extra params.
Modifies a memory region in the device address space.


     struct {
     struct {
     __in      u32 flags;          // bit0: fixed_offset, bit2: cacheable
     __in      u32 flags;          // bit0: fixed_offset, bit2: cacheable
     __in      u32 kind;          // -1 is default
     __in      u32 kind;          // -1 is default
     __in      u32 nvmap_handle;
     __in      u32 dmabuf_fd;     // nvmap handle
     __inout  u32 page_size;      // 0 means don't care
     __inout  u32 page_size;      // 0 means don't care
     __in      u64 buffer_offset;
     __in      u64 buffer_offset;
Line 948: Line 1,034:
     __in      u64 unk0;
     __in      u64 unk0;
     __in      u32 unk1;
     __in      u32 unk1;
     u32           pad;
     u32           reserved;
   };
   };


Line 954: Line 1,040:
Nintendo's custom implementation of address space remapping.
Nintendo's custom implementation of address space remapping.


   struct remap_entry {
   struct remap_op {
     __in u16 flags;       // 0 or 4
     __in u16 flags;                   // 0 or 4
     __in u16 kind;           
     __in u16 kind;           
     __in u32 nvmap_handle;
     __in u32 mem_handle;
     __in u32 reserved;
     __in u32 mem_offset_in_pages;
     __in u32 offset;       // (alloc_space_offset >> 0x10)
     __in u32 virt_offset_in_pages;   // (alloc_space_offset >> 0x10)
     __in u32 pages;       // alloc_space_pages
     __in u32 num_pages;               // alloc_space_pages
   };
   };
   
   
  struct {
  struct {
     __in struct remap_entry entries[];
     __in struct remap_op entries[];
  };
  };


Line 1,060: Line 1,146:
| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
|-
|-
| 0xC0184706 || Inout || 24 || NVGPU_GPU_IOCTL_GET_TPC_MASKS
| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]]
|-
|-
| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]]
| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]]
|-
|-
| 0x4008470D || In || 8 || NVGPU_GPU_IOCTL_INVAL_ICACHE
| 0x4008470D || In || 8 || [[#NVGPU_GPU_IOCTL_INVAL_ICACHE]]
|-
|-
| 0x4008470E || In || 8 || NVGPU_GPU_IOCTL_SET_MMUDEBUG_MODE
| 0x4008470E || In || 8 || [[#NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE]]
|-
|-
| 0x4010470F || In || 16 || NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE
| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]
|-
|-
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || [[#NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE]]
|-
|-
| 0x80084711 || Out || 8 || NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS
| 0x80084711 || Out || 8 || [[#NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS]]
|-
|-
| 0x80084712 || Out || 8 || NVGPU_GPU_IOCTL_NUM_VSMS
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]]
|-
|-
| 0xC0044713 || Inout || 4 || NVGPU_GPU_IOCTL_VSMS_MAPPING
| 0xC0044713 || Inout || 4 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]
|-
|-
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
|-
|-
| 0x80044715 || Out || 4 || NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD
| 0x80044715 || Out || 4 || [[#NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD]]
|-
|-
| 0x40084716 || In || 8 || NVGPU_GPU_IOCTL_SET_CG_CONTROLS
| 0x40084716 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_CG_CONTROLS]]
|-
|-
| 0xC0084717 || Inout || 8 || NVGPU_GPU_IOCTL_GET_CG_CONTROLS
| 0xC0084717 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_CG_CONTROLS]]
|-
|-
| 0x40084718 || In || 8 || NVGPU_GPU_IOCTL_SET_PG_CONTROLS
| 0x40084718 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_PG_CONTROLS]]
|-
|-
| 0xC0084719 || Inout || 8 || NVGPU_GPU_IOCTL_GET_PG_CONTROLS
| 0xC0084719 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_PG_CONTROLS]]
|-
|-
| 0x8018471A || Out || 24 || NVGPU_GPU_IOCTL_PMU_DUMP_ELPG_STATS
| 0x8018471A || Out || 24 || [[#NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING]]
|-
|-
| 0xC008471B || Inout || 8 || NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA
| 0xC008471B || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA]]
|-
|-
| 0xC010471C || Inout || 16 || NVGPU_GPU_IOCTL_GET_GPU_TIME
| 0xC010471C || Inout || 16 || [[#NVGPU_GPU_IOCTL_GET_GPU_TIME]]
|-
|-
| 0xC108471D || Inout || 264 || NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
|}
|}


Line 1,148: Line 1,234:
=== NVGPU_GPU_IOCTL_GET_CHARACTERISTICS ===
=== NVGPU_GPU_IOCTL_GET_CHARACTERISTICS ===
Returns the GPU characteristics. Modified to return inline data instead of using a pointer.
Returns the GPU characteristics. Modified to return inline data instead of using a pointer.
[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].


   struct gpu_characteristics {
   struct gpu_characteristics {
Line 1,191: Line 1,279:
     __in    u64 gpu_characteristics_buf_addr;  // ignored, but must not be NULL
     __in    u64 gpu_characteristics_buf_addr;  // ignored, but must not be NULL
     __out struct gpu_characteristics gc;
     __out struct gpu_characteristics gc;
  };
=== NVGPU_GPU_IOCTL_GET_TPC_MASKS ===
Returns the TPC mask value for each GPC. Modified to return inline data instead of using a pointer.
[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].
  struct {
    __in u32 mask_buf_size;      // ignored, but must not be NULL
    __in u32 reserved[3];
    __out u64 mask_buf;          // receives one 32-bit TPC mask per GPC (GPC 0 and GPC 1)
   };
   };


Line 1,198: Line 1,297:
   struct {
   struct {
     __in u32 flush;          // l2_flush | l2_invalidate << 1 | fb_flush << 2
     __in u32 flush;          // l2_flush | l2_invalidate << 1 | fb_flush << 2
     u32     reserved;
     __in u32 reserved;
   };
   };


=== NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK ===
=== NVGPU_GPU_IOCTL_INVAL_ICACHE ===
Returns the mask value for a ZBC slot.
Invalidates the GPU instruction cache. Identical to Linux driver.


   struct {
   struct {
     __out u32 slot;       // always 0x07
     __in s32 channel_fd;
     __out u32 mask;
     __in u32 reserved;
   };
   };


== Channels ==
=== NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE ===
Channels are a concept for  NVIDIA hardware blocks that share a common interface.
Sets the GPU MMU debug mode. Identical to Linux driver.


{| class="wikitable" border="1"
  struct {
! Path || Name
    __in u32 state;
|-
    __in u32 reserved;
| /dev/nvhost-gpu || GPU
  };
|-
 
| /dev/nvhost-msenc || Video Encoder
=== NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE ===
|-
Sets the GPU SM debug mode. Identical to Linux driver.
| /dev/nvhost-nvdec || Video Decoder
 
|-
  struct {
| /dev/nvhost-nvjpg || JPEG Decoder
    __in s32 channel_fd;
|-
    __in u32 enable;
| /dev/nvhost-vic || Video Image Compositor
    __in u64 sms;
|-
  };
| /dev/nvhost-display || Display
 
|}
=== NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE ===
Waits until all valid warps on the GPU SM are paused and returns their current state.
 
  struct {
    __in u64 pwarpstate;
  };


== Channel Ioctls ==
[6.1.0+] This command was modified to return inline data instead of using a pointer.
{| class="wikitable" border="1"
 
! Value || Size || Description
  struct {
|-
    __out u64 sm0_valid_warps;
| 0xC0??0001 || Variable || NVHOST_IOCTL_CHANNEL_SUBMIT
    __out u64 sm0_trapped_warps;
|-
    __out u64 sm0_paused_warps;
| 0xC0080002 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
    __out u64 sm1_valid_warps;
|-
    __out u64 sm1_trapped_warps;
| 0xC0080003 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
    __out u64 sm1_paused_warps;
|-
  };
| 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
 
|-
=== NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS ===
| 0x40040007 || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
Returns a mask value describing all active TPC exceptions. Identical to Linux driver.
|-
 
| 0x40080008 || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
  struct {
|-
    __out u64 tpc_exception_en_sm_mask;
| 0xC0??0009 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
  };
|-
 
| 0xC0??000A || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
=== NVGPU_GPU_IOCTL_NUM_VSMS ===
|-
Returns the number of GPU SM units present. Identical to Linux driver.
| 0x00000013 || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
 
|-
  struct {
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
    __out u32 num_vsms;
|-
    __out u32 reserved;
| 0xC0??0024 || Variable || NVHOST_IOCTL_CHANNEL_SUBMIT_EX
  };
|-
 
| 0xC0??0025 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
=== NVGPU_GPU_IOCTL_VSMS_MAPPING ===
|-
Returns mapping information on each GPU SM unit. Modified to return inline data instead of using a pointer.
| 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
 
|- style="border-top: double"
  struct {
| 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
    __out u8 sm0_gpc_index;
|-
    __out u8 sm0_tpc_index;
| 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
    __out u8 sm1_gpc_index;
|-
    __out u8 sm1_tpc_index;
| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
  };
|-
 
| 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
=== NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK ===
|-
Returns the mask value for a ZBC slot.
| 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
 
|-
  struct {
| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
    __out u32 slot;      // always 0x07
|-
    __out u32 mask;
| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
  };
|-
 
| 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
=== NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD ===
|-
Returns the GPU load value from the PMU.
| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
 
|-
  struct {
| 0xC018480C || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
    __out u32 pmu_gpu_load;
|-
  };
| 0x4004480D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
 
=== NVGPU_GPU_IOCTL_SET_CG_CONTROLS ===
Sets the clock gate control value.
 
  struct {
    __in u32 cg_mask;
    __in u32 cg_value;
  };
 
=== NVGPU_GPU_IOCTL_GET_CG_CONTROLS ===
Returns the clock gate control value.
 
  struct {
    __in u32 cg_mask;
    __out u32 cg_value;
  };
 
=== NVGPU_GPU_IOCTL_SET_PG_CONTROLS ===
Sets the power gate control value.
 
  struct {
    __in u32 pg_mask;
    __in u32 pg_value;
  };
 
=== NVGPU_GPU_IOCTL_GET_PG_CONTROLS ===
Returns the power gate control value.
 
  struct {
    __in u32 pg_mask;
    __out u32 pg_value;
  };
 
=== NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING ===
Returns the GPU PMU ELPG residency gating values.
 
  struct {
    __out u64 pg_ingating_time_us;
    __out u64 pg_ungating_time_us;
    __out u64 pg_gating_cnt;
  };
 
=== NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA ===
Returns user specific data from the error channel, if one exists.
 
  struct {
    __out u64 data;
  };
 
=== NVGPU_GPU_IOCTL_GET_GPU_TIME ===
Returns the timestamp from the GPU's nanosecond timer (PTIMER). Identical to Linux driver.
 
  struct {
    __out u64 gpu_timestamp;      // raw GPU counter (PTIMER) value
    __out u64 reserved;
  };
 
=== NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO ===
Returns CPU/GPU timestamp pairs for correlation analysis. Identical to Linux driver.
 
struct time_correlation_sample {
  u64 cpu_timestamp;                                  // from CPU's CNTPCT_EL0 register
  u64 gpu_timestamp;                                  // from GPU's PTIMER registers
};
struct {
  __out struct time_correlation_sample samples[16];  // timestamp pairs
  __in u32    count;                                // number of pairs to read
  __in u32    source_id;                            // cpu clock source id (must be 1)
};
 
== Channels ==
Channels are a concept for  NVIDIA hardware blocks that share a common interface.
 
{| class="wikitable" border="1"
! Path || Name
|-
|-
| 0x0000480E || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
| /dev/nvhost-gpu || GPU
|-
|-
| 0x0000480F || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
| /dev/nvhost-msenc || Video Encoder
|-
|-
| 0x00004810 || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
| /dev/nvhost-nvdec || Video Decoder
|-
|-
| 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
| /dev/nvhost-nvjpg || JPEG Decoder
|-
|-
| 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
| /dev/nvhost-vic || Video Image Compositor
|-
|-
| 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
| /dev/nvhost-display || Display
|}
 
== Channel Ioctls ==
{| class="wikitable" border="1"
! Value || Size || Description
|-
|-
| 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
| 0xC0??0001 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT]]
|-
|-
| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
| 0xC0080002 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
|-
|-
| 0x40204818 || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
| 0xC0080003 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
|-
|-
| 0xC0??4819 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
| 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
|-
|-
| 0xC020481A || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
| 0x40040007 || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
|-
|-
| 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_EX]]
| 0x40080008 || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
|-
|-
| 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY_EX]]
| 0xC0??0009 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
|-
|-
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
| 0xC0??000A || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
|-
| 0x00000013 || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
|-
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
|-
| 0xC0??0024 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]
|-
| 0xC0??0025 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
|-
| 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
|- style="border-top: double"
|- style="border-top: double"
| 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
| 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
|-
| 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
|-
| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
|-
| 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
|-
| 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
|-
|-
| 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
|}
|-
 
| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
=== NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT ===
|-
Returns the current syncpoint value for a given module. Identical to Linux driver.
| 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
 
|-
  struct {
| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
    __in    u32 module_id;
|-
    __out  u32 syncpt_value;
| 0xC018480C || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
  };
|-
 
| 0x4004480D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
=== NVHOST_IOCTL_CHANNEL_GET_WAITBASE ===
|-
Returns the current waitbase value for a given module. Always returns 0.
| 0x0000480E || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
 
|-
  struct {
| 0x0000480F || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
    __in    u32 module_id;
|-
    __out  u32 waitbase_value;
| 0x00004810 || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
  };
|-
 
| 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
=== NVHOST_IOCTL_CHANNEL_GET_MODMUTEX ===
|-
Stubbed. Does a debug print and returns 0.
| 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
 
|-
=== NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT ===
| 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
Sets the submit timeout value for the channel. Identical to Linux driver.
|-
 
| 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
  struct {
|-
    __in    u32 timeout;
| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
  };
|-
 
| 0x40204818 || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
=== NVHOST_IOCTL_CHANNEL_SET_CLK_RATE ===
|-
Sets the clock rate value for a given module. Identical to Linux driver.
| 0xC0??4819 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
 
|-
  struct {
| 0xC020481A || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
    __in    u32 clk_rate;
|-
    __in    u32 module_id;
| 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_EX]]
  };
|-
| 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY_EX]]
|-
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
|- style="border-top: double"
| 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
|-
| 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
|}


=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER ===
=== NVHOST_IOCTL_CHANNEL_SUBMIT ===
Uses '''nvmap_pin''' internally to pin a given number of nvmap handles to an appropriate device physical address.
Submits data to the channel.


   struct handle {
   struct cmdbuf {
     u32 handle_id_in;                 // nvmap handle to map
     u32 mem;
     u32 phys_addr_out;               // returned device physical address mapped to the handle
     u32 offset;
    u32 words;
  };
 
  struct reloc {
    u32 cmdbuf_mem;
    u32 cmdbuf_offset;
    u32 target;
    u32 target_offset;
   };
   };
 
   struct {
   struct reloc_shift {
     __in    u32 num_handles;         // number of nvmap handles to map
     u32 shift;
    __in    u32 reserved;             // ignored
  };
    __in    u8  is_compr;            // memory to map is compressed
 
     __in    u8  padding[3];           // ignored
  struct syncpt_incr {
     __inout struct handle handles[]; // depends on num_handles
     u32 syncpt_id;
     u32 syncpt_incrs;
   };
   };
 
 
=== NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER ===
   struct fence {
Uses '''nvmap_unpin''' internally to unpin a given number of nvmap handles from their device physical address.
     u32 id;
 
     u32 thresh;
   struct handle {
     u32 handle_id_in;                 // nvmap handle to unmap
     u32 reserved;                     // ignored
   };
   };
 
   struct {
   struct {
     __in    u32 num_handles;         // number of nvmap handles to unmap
     __in    u32 num_cmdbufs;
     __in    u32 reserved;             // ignored
    __in    u32 num_relocs;
     __in    u8  is_compr;             // memory to unmap is compressed
    __in    u32 num_syncpt_incrs;
     __in    u8  padding[3];           // ignored
    __in    u32 num_fences;
     __inout struct handle handles[]; // depends on num_handles
    __in    struct cmdbuf cmdbufs[];              // depends on num_cmdbufs
     __in    struct reloc relocs[];                 // depends on num_relocs
     __in    struct reloc_shift reloc_shifts[];     // depends on num_relocs
     __in    struct syncpt_incr syncpt_incrs[];     // depends on num_syncpt_incrs
     __out  struct fence fences[];                 // depends on num_fences
   };
   };


=== NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX ===
=== NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT ===
Sets the global timeout value for the channel. Identical to Linux driver.
Returns the current syncpoint value for a given module. Identical to Linux driver.


   struct {
   struct {
     __in    u32 timeout;
     __in    u32 module_id;
     __in    u32 flags;
     __out  u32 syncpt_value;
   };
   };


=== NVHOST_IOCTL_CHANNEL_GET_CLK_RATE ===
=== NVHOST_IOCTL_CHANNEL_GET_WAITBASE ===
Returns the clock rate value for a given module. Identical to Linux driver.
Returns the current waitbase value for a given module. Always returns 0.


   struct {
   struct {
    __out  u32 clk_rate;
     __in    u32 module_id;
     __in    u32 module_id;
    __out  u32 waitbase_value;
   };
   };


=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX ===
=== NVHOST_IOCTL_CHANNEL_GET_MODMUTEX ===
Same as [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]], but calls '''nvmap_unpin''' internally in case of error.
Stubbed. Does a debug print and returns 0.


=== NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX ===
=== NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT ===
Same as [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]].
Sets the submit timeout value for the channel. Identical to Linux driver.
 
=== NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD ===
Binds a nvmap object to this channel. Identical to Linux driver.


   struct {
   struct {
     __in u32 nvmap_fd;
     __in   u32 timeout;
   };
   };


=== NVGPU_IOCTL_CHANNEL_SET_TIMEOUT ===
=== NVHOST_IOCTL_CHANNEL_SET_CLK_RATE ===
Sets the timeout value for the GPU channel. Identical to Linux driver.
Sets the clock rate value for a given module. Identical to Linux driver.


   struct {
   struct {
     __in    u32 timeout;
     __in    u32 clk_rate;
    __in    u32 module_id;
   };
   };


=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO ===
=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER ===
Allocates gpfifo entries. Identical to Linux driver.
Uses '''nvmap_pin''' internally to pin a given number of nvmap handles to an appropriate device physical address.


  struct handle {
    u32 handle_id_in;                // nvmap handle to map
    u32 phys_addr_out;                // returned device physical address mapped to the handle
  };
   struct {
   struct {
     __in u32 num_entries;
     __in   u32 num_handles;         // number of nvmap handles to map
     __in u32 flags;
     __in   u32 reserved;             // ignored
    __in    u8  is_compr;            // memory to map is compressed
    __in    u8  padding[3];          // ignored
    __inout struct handle handles[];  // depends on num_handles
   };
   };


=== NVGPU_IOCTL_CHANNEL_WAIT ===
=== NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER ===
Waits on channel. Identical to Linux driver.
Uses '''nvmap_unpin''' internally to unpin a given number of nvmap handles from their device physical address.


  struct handle {
    u32 handle_id_in;                // nvmap handle to unmap
    u32 reserved;                    // ignored
  };
   struct {
   struct {
     __in u32 type;           // wait type (0=notifier, 1=semaphore)
     __in   u32 num_handles;         // number of nvmap handles to unmap
     __in u32 timeout;         // wait timeout value
     __in   u32 reserved;             // ignored
     __in u32 dmabuf_fd;       // nvmap handle
     __in   u8  is_compr;             // memory to unmap is compressed
    __in u32 offset;          // nvmap memory offset
     __in   u8  padding[3];           // ignored
     __in u32 payload;         // payload data (semaphore only)
     __inout struct handle handles[]; // depends on num_handles
     __in u32 padding;         // ignored
   };
   };


=== NVGPU_IOCTL_CHANNEL_CYCLE_STATS ===
=== NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX ===
Maps memory for the cycle stats buffer. Identical to Linux driver.
Sets the global timeout value for the channel. Identical to Linux driver.


   struct {
   struct {
     __in u32 dmabuf_fd;   // nvmap handle
     __in   u32 timeout;
    __in    u32 flags;
   };
   };


=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO ===
=== NVHOST_IOCTL_CHANNEL_GET_CLK_RATE ===
Submits a gpfifo object. Modified to take inline entry objects instead of a pointer.
Returns the clock rate value for a given module. Identical to Linux driver.


   struct fence {
   struct {
     u32 syncpt_id;
     __out   u32 clk_rate;
    u32 syncpt_value;
     __in    u32 module_id;
  };
 
  struct gpfifo_entry {
    u64 entry;                              // gpu_iova | (unk_2bits << 40) | (size << 42) | (unk_flag << 63)
  };
 
   struct {
    __in    u64 gpfifo;                      // (ignored) pointer to gpfifo fence structs
    __in    u32 num_entries;                 // number of fence objects being submitted
     __in    u32 flags;
    __inout struct fence fence_out;          // returned new fence object for others to wait on
    __in    struct gpfifo_entry entries[];   // depends on num_entries
   };
   };


=== NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX ===
=== NVHOST_IOCTL_CHANNEL_SUBMIT_EX ===
Allocates a graphics context object. Modified to ignore object's ID.
Same as [[#NVHOST_IOCTL_CHANNEL_SUBMIT|NVHOST_IOCTL_CHANNEL_SUBMIT]].
 
=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX ===
Same as [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]], but calls '''nvmap_unpin''' internally in case of error.
 
=== NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX ===
Same as [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]].


You can only have one object context allocated at a time. You must have bound an address space before using this.
=== NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD ===
Binds a nvmap object to this channel. Identical to Linux driver.


   struct {
   struct {
     __in u32 class_num;   // 0x902D=2d, 0xB197=3d, 0xB1C0=compute, 0xA140=kepler, 0xB0B5=DMA, 0xB06F=channel_gpfifo
     __in u32 nvmap_fd;
    __in  u32 flags;        // bit0: LOCKBOOST_ZERO
    __out u64 obj_id;      // (ignored) used for FREE_OBJ_CTX ioctl, which is not supported
   };
   };


=== NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX ===
=== NVGPU_IOCTL_CHANNEL_SET_TIMEOUT ===
Frees a graphics context object. Not supported.
Sets the timeout value for the GPU channel. Identical to Linux driver.


   struct {
   struct {
     __in u64 obj_id;       // ignored
     __in u32 timeout;
   };
   };


=== NVGPU_IOCTL_CHANNEL_ZCULL_BIND ===
=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO ===
Binds a ZCULL context to the channel. Identical to Linux driver.
Allocates gpfifo entries. Identical to Linux driver.


struct {
  struct {
    __in u64 gpu_va;
     __in u32 num_entries;
     __in u32 mode;         // 0=global, 1=no_ctxsw, 2=separate_buffer, 3=part_of_regular_buf
     __in u32 flags;
     __in u32 reserved;
   };
   };


=== NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER ===
=== NVGPU_IOCTL_CHANNEL_WAIT ===
Initializes the error notifier for this channel. Unlike for the Linux kernel, the Switch driver cannot write to an arbitrary userspace buffer. Thus new ioctls have been introduced to fetch the error information rather than using a shared memory buffer.
Waits on channel. Identical to Linux driver.


   struct {
   struct {
     __in u64 offset;   // ignored
     __in u32 type;            // wait type (0=notifier, 1=semaphore)
     __in u64 size;    // ignored
    __in u32 timeout;         // wait timeout value
     __in u32 mem;     // must be non-zero to initialize, zero to de-initialize
     __in u32 dmabuf_fd;       // nvmap handle
     __in u32 reserved; // ignored
     __in u32 offset;          // nvmap memory offset
     __in u32 payload;         // payload data (semaphore only)
     __in u32 padding;         // ignored
   };
   };


=== NVGPU_IOCTL_CHANNEL_SET_PRIORITY ===
=== NVGPU_IOCTL_CHANNEL_CYCLE_STATS ===
Changes channel's priority. Identical to Linux driver.
Maps memory for the cycle stats buffer. Identical to Linux driver.


   struct {
   struct {
     __in u32 priority;   // 0x32 is low, 0x64 is medium and 0x96 is high
     __in u32 dmabuf_fd;   // nvmap handle
   };
   };


=== NVGPU_IOCTL_CHANNEL_ENABLE ===
=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO ===
Enables the current channel. Identical to Linux driver.
Submits a gpfifo object. Modified to take inline entry objects instead of a pointer.


=== NVGPU_IOCTL_CHANNEL_DISABLE ===
  struct fence {
Disables the current channel. Identical to Linux driver.
    u32 id;
    u32 thresh;
  };
 
  struct gpfifo_entry {
    u64 entry;                              // gpu_iova | (unk_2bits << 40) | (size << 42) | (unk_flag << 63)
  };
 
  struct {
    __in    u64 gpfifo;                      // (ignored) pointer to gpfifo fence structs
    __in    u32 num_entries;                // number of fence objects being submitted
    __in    u32 flags;
    __inout struct fence fence_out;          // returned new fence object for others to wait on
    __in    struct gpfifo_entry entries[];  // depends on num_entries
  };


=== NVGPU_IOCTL_CHANNEL_PREEMPT ===
=== NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX ===
Clears the FIFO pipe for this channel. Identical to Linux driver.
Allocates a graphics context object. Modified to ignore object's ID.


=== NVGPU_IOCTL_CHANNEL_FORCE_RESET ===
You can only have one object context allocated at a time. You must have bound an address space before using this.
Forces the channel to reset. Identical to Linux driver.
 
=== NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL ===
Controls event notifications.


   struct {
   struct {
     __in u32 cmd;    // 0=disable, 1=enable, 2=clear
     __in u32 class_num;    // 0x902D=2d, 0xB197=3d, 0xB1C0=compute, 0xA140=kepler, 0xB0B5=DMA, 0xB06F=channel_gpfifo
     __in u32 id;    // same id's as for [[#QueryEvent]]
     __in u32 flags;       // bit0: LOCKBOOST_ZERO
     __out u64 obj_id;      // (ignored) used for FREE_OBJ_CTX ioctl, which is not supported
   };
   };


=== NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT ===
=== NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX ===
Controls the cycle stats snapshot buffer. Identical to Linux driver.
Frees a graphics context object. Not supported.


   struct {
   struct {
     __in   u32 cmd;        // command to handle (0=flush, 1=attach, 2=detach)
     __in u64 obj_id;      // ignored
    __in    u32 dmabuf_fd;  // nvmap handle
    __inout u32 extra;      // extra payload data/result
    __in    u32 padding;    // ignored
   };
   };


=== NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO ===
=== NVGPU_IOCTL_CHANNEL_ZCULL_BIND ===
Returns information on the current error notification caught by the error notifier. Exclusive to the Switch.
Binds a ZCULL context to the channel. Identical to Linux driver.


  struct {
struct {
     __out u32 error_info[32];   // first word is an error code (0=no_error, 1=gr_error, 2=gr_error, 3=invalid, 4=invalid)
     __in u64 gpu_va;
    __in u32 mode;         // 0=global, 1=no_ctxsw, 2=separate_buffer, 3=part_of_regular_buf
    __in u32 reserved;
   };
   };


=== NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION ===
=== NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER ===
Returns the current error notification caught by the error notifier. Exclusive to the Switch.
Initializes the error notifier for this channel. Unlike for the Linux kernel, the Switch driver cannot write to an arbitrary userspace buffer. Thus new ioctls have been introduced to fetch the error information rather than using a shared memory buffer.


   struct {
   struct {
     __out u64 timestamp;   // fetched straight from armGetSystemTick
     __in u64 offset;   // ignored
     __out u32 info32;       // error code
     __in u64 size;     // ignored
     __out u16 info16;       // additional error info
     __in u32 mem;     // must be non-zero to initialize, zero to de-initialize
     __out u16 status;       // always 0xFFFF
     __in u32 reserved; // ignored
   };
   };


=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX ===
=== NVGPU_IOCTL_CHANNEL_SET_PRIORITY ===
Allocates gpfifo entries with additional parameters. Exclusive to the Switch.
Changes channel's priority. Identical to Linux driver.
 
  struct {
    __in u32 priority;    // 0x32 is low, 0x64 is medium and 0x96 is high
  };


struct fence {
=== NVGPU_IOCTL_CHANNEL_ENABLE ===
  u32 syncpt_id;
Enables the current channel. Identical to Linux driver.
  u32 syncpt_value;
};
struct {
  __in    u32 num_entries;
  __in    u32 num_jobs;
  __in    u32 flags;
  __out  struct fence fence_out;          // returned new fence object for others to wait on
  __in    u32 reserved[3];                // ignored
};


=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY ===
=== NVGPU_IOCTL_CHANNEL_DISABLE ===
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]].
Disables the current channel. Identical to Linux driver.


=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2 ===
=== NVGPU_IOCTL_CHANNEL_PREEMPT ===
Same as [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX|NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]].
Clears the FIFO pipe for this channel. Identical to Linux driver.


=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_EX ===
=== NVGPU_IOCTL_CHANNEL_FORCE_RESET ===
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]], but uses [[#Ioctl2|Ioctl2]].
Forces the channel to reset. Identical to Linux driver.


=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY_EX ===
=== NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL ===
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]], but uses [[#Ioctl2|Ioctl2]].
Controls event notifications.
 
=== NVGPU_IOCTL_CHANNEL_SET_TIMESLICE ===
Changes channel's timeslice. Identical to Linux driver.


   struct {
   struct {
     __in u32 timeslice;
     __in u32 cmd;   // 0=disable, 1=enable, 2=clear
    __in u32 id;    // same id's as for [[#QueryEvent]]
   };
   };


=== NVGPU_IOCTL_CHANNEL_SET_USER_DATA ===
=== NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT ===
Sets user specific data.
Controls the cycle stats snapshot buffer. Identical to Linux driver.
 
  struct {
    __in    u32 cmd;        // command to handle (0=flush, 1=attach, 2=detach)
    __in    u32 dmabuf_fd;  // nvmap handle
    __inout u32 extra;      // extra payload data/result
    __in    u32 padding;    // ignored
  };
 
=== NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO ===
Returns information on the current error notification caught by the error notifier. Exclusive to the Switch.


   struct {
   struct {
     __in u64 data;
     __out u32 error_info[32];   // first word is an error code (0=no_error, 1=gr_error, 2=gr_error, 3=invalid, 4=invalid)
   };
   };


=== NVGPU_IOCTL_CHANNEL_GET_USER_DATA ===
=== NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION ===
Gets user specific data.
Returns the current error notification caught by the error notifier. Exclusive to the Switch.


   struct {
   struct {
     __out u64 data;
     __out u64 timestamp;   // fetched straight from armGetSystemTick
    __out u32 info32;      // error code
    __out u16 info16;      // additional error info
    __out u16 status;      // always 0xFFFF
   };
   };
 
 
= nvmemp =
=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX ===
NVIDIA memory profiler (this service is not available on retail units).  
Allocates gpfifo entries with additional parameters. Exclusive to the Switch.
/dev/nvhost-ctrl sends the ioctl NVHOST_IOCTL_CTRL_GET_CONFIG to check the config "nv!NV_MEMORY_PROFILER". If config_str returns "1", the application attempts to use nvmemp.
 
 
struct fence {
{| class="wikitable" border="1"
    u32 id;
    u32 thresh;
};
struct {
  __in    u32 num_entries;
  __in    u32 num_jobs;
  __in    u32 flags;
  __out  struct fence fence_out;          // returned new fence object for others to wait on
  __in    u32 reserved[3];                // ignored
};
 
=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY ===
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]].
 
=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2 ===
Same as [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX|NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]].
 
=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_EX ===
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]], but uses [[#Ioctl2|Ioctl2]].
 
=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY_EX ===
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]], but uses [[#Ioctl2|Ioctl2]].
 
=== NVGPU_IOCTL_CHANNEL_SET_TIMESLICE ===
Changes channel's timeslice. Identical to Linux driver.
 
  struct {
    __in u32 timeslice;
  };
 
=== NVGPU_IOCTL_CHANNEL_SET_USER_DATA ===
Sets user specific data.
 
  struct {
    __in u64 data;
  };
 
=== NVGPU_IOCTL_CHANNEL_GET_USER_DATA ===
Returns user specific data.
 
  struct {
    __out u64 data;
  };
 
= nvmemp =
This is "nv::MemoryProfiler::IMemoryProfiler".
 
/dev/nvhost-ctrl sends the ioctl NVHOST_IOCTL_CTRL_GET_CONFIG to check the config "nv!NV_MEMORY_PROFILER". If config_str returns "1", the application attempts to use nvmemp.
 
{| class="wikitable" border="1"
|-
! Cmd || Name
|-
| 0 || Open
|-
| 1 || GetPid
|}
 
= nvdrvdbg =
This is "nns::nvdrv::INvDrvDebugFSServices".
 
{| class="wikitable" border="1"
|-
! Cmd || Name
|-
| 0 || [[#OpenDebugFS]]
|-
| 1 || [[#CloseDebugFS]]
|-
| 2 || [[#GetDebugFSKeys]]
|-
| 3 || GetDebugFSValue
|-
| 4 || SetDebugFSValue
|}
 
== OpenDebugFS ==
Takes a process handle. Returns a u32 '''fd'''.
 
== CloseDebugFS ==
Takes a u32 '''fd''' and closes it.
 
== GetDebugFSKeys ==
Takes a u32 '''fd''' and reads debug contents into a type-6 buffer.
 
= nvgem:c =
This is "nv::gemcontrol::INvGemControl".
 
{| class="wikitable" border="1"
|-
! Cmd || Name
|-
| 0 || Initialize
|-
| 1 || GetEventHandle
|-
| 2 || ControlNotification
|-
| 3 || SetNotificationPerm
|-
| 4 || SetCoreDumpPerm
|-
| 5 || [1.0.0-4.1.0] GetAruid
|-
| 6 || Reset
|-
| 7 || [3.0.0+]
|}
 
= nvgem:cd =
This is "nv::gemcoredump::INvGemCoreDump".
 
{| class="wikitable" border="1"
|-
! Cmd || Name
|-
| 0 || Initialize
|-
| 1 || GetAruid
|-
| 2 || [1.0.0-8.1.0] ReadNextBlock
|-
| 3 || [8.0.0+]
|-
| 4 || [8.0.0+]
|}
 
= nvdbg:d =
This is "nns::nvdrv::INvDrvDebugSvcServices". This was added with [10.0.0+].
 
This service has no commands.
 
= Errors =
Most nvidia driver commands return an error code apart from the normal return code.
 
{| class="wikitable" border="1"
|-
! Value || Name
|-
| 0x0 || NvError_Success
|-
| 0x1 || NvError_NotImplemented
|-
| 0x2 || NvError_NotSupported
|-
| 0x3 || NvError_NotInitialized
|-
| 0x4 || NvError_BadParameter
|-
| 0x5 || NvError_Timeout
|-
|-
! Cmd || Name
| 0x6 || NvError_InsufficientMemory
|-
|-
| 0 || Open
| 0x7 || NvError_ReadOnlyAttribute
|-
|-
| 1 || GetAruid
| 0x8 || NvError_InvalidState
|}
 
= nvdrvdbg =
This is "nns::nvdrv::INvDrvDebugFSServices".
 
{| class="wikitable" border="1"
|-
|-
! Cmd || Name
| 0x9 || NvError_InvalidAddress
|-
|-
| 0 || [[#OpenDebugFS]]
| 0xA || NvError_InvalidSize
|-
|-
| 1 || [[#CloseDebugFS]]
| 0xB || NvError_BadValue
|-
|-
| 2 || [[#GetDebugFSKeys]]
| 0xD || NvError_AlreadyAllocated
|-
|-
| 3 || GetDebugFSValue
| 0xE || NvError_Busy
|-
|-
| 4 || SetDebugFSValue
| 0xF || NvError_ResourceError
|}
 
== OpenDebugFS ==
Takes a process handle. Returns a u32 '''fd'''.
 
== CloseDebugFS ==
Takes a u32 '''fd''' and closes it.
 
== GetDebugFSKeys ==
Takes a u32 '''fd''' and reads debug contents into a type-6 buffer.
 
= nvgem:c =
This is "nv::gemcontrol::INvGemControl".
 
{| class="wikitable" border="1"
|-
|-
! Cmd || Name
| 0x10 || NvError_CountMismatch
|-
|-
| 0 || Initialize
| 0x11 || NvError_OverFlow
|-
|-
| 1 || GetGemEvent
| 0x1000 || NvError_InsufficientTransferMemory
|-
|-
| 2 ||  
| 0x10000 || NvError_InsufficientVideoMemory
|-
|-
| 3 || RegisterUnregisterAppIdLocked
| 0x10001 || NvError_BadSurfaceColorScheme
|-
|-
| 4 ||
| 0x10002 || NvError_InvalidSurface
|-
|-
| [1.0.0-4.1.0] 5 || GetAruid
| 0x10003 || NvError_SurfaceNotSupported
|-
|-
| 6 || HandleDeferredErrors
| 0x20000 || NvError_DispInitFailed
|-
|-
| 7 || [3.0.0+]
| 0x20001 || NvError_DispAlreadyAttached
|}
 
= nvgem:cd =
This is "nv::gemcoredump::INvGemCoreDump".
 
{| class="wikitable" border="1"
|-
|-
! Cmd || Name
| 0x20002 || NvError_DispTooManyDisplays
|-
|-
| 0 || Initialize
| 0x20003 || NvError_DispNoDisplaysAttached
|-
|-
| 1 || GetAruid
| 0x20004 || NvError_DispModeNotSupported
|-
|-
| [1.0.0-8.1.0] 2 || ReadNextCdBlock
| 0x20005 || NvError_DispNotFound
|-
|-
| 3 || [8.0.0+]
| 0x20006 || NvError_DispAttachDissallowed
|-
|-
| 4 || [8.0.0+]
| 0x20007 || NvError_DispTypeNotSupported
|}
 
= Errors =
Most nvidia driver commands return an error code apart from the normal return code.
 
{| class="wikitable" border="1"
|-
|-
! Cmd || Name
| 0x20008 || NvError_DispAuthenticationFailed
|-
|-
| 0 || Success
| 0x20009 || NvError_DispNotAttached
|-
|-
| 1 || NotImplemented
| 0x2000A || NvError_DispSamePwrState
|-
|-
| 2 || NotSupported
| 0x2000B || NvError_DispEdidFailure
|-
|-
| 3 || NotInitialized
| 0x2000C || NvError_DispDsiReadAckError
|-
|-
| 4 || BadParameter
| 0x2000D || NvError_DispDsiReadInvalidResp
|-
|-
| 5 || Timeout
| 0x30000 || NvError_FileWriteFailed
|-
|-
| 6 || InsufficientMemory
| 0x30001 || NvError_FileReadFailed
|-
|-
| 7 || ReadOnlyAttribute
| 0x30002 || NvError_EndOfFile
|-
|-
| 8 || InvalidState
| 0x30003 || NvError_FileOperationFailed
|-
|-
| 9 || InvalidAddress
| 0x30004 || NvError_DirOperationFailed
|-
|-
| 0xA || InvalidSize
| 0x30005 || NvError_EndOfDirList
|-
|-
| 0xB || BadValue
| 0x30006 || NvError_ConfigVarNotFound
|-
|-
| 0xD || AlreadyAllocated
| 0x30007 || NvError_InvalidConfigVar
|-
|-
| 0xE || Busy
| 0x30008 || NvError_LibraryNotFound
|-
|-
| 0xF || ResourceError
| 0x30009 || NvError_SymbolNotFound
|-
|-
| 0x10 || CountMismatch
| 0x3000A || NvError_MemoryMapFailed
|-
|-
| 0x1000 || SharedMemoryTooSmall
| 0x3000F || NvError_IoctlFailed                       
|-
|-
| 0x30003 || FileOperationFailed
| 0x30010 || NvError_AccessDenied
|-
|-
| 0x30004 || DirOperationFailed
| 0x30011 || NvError_DeviceNotFound
|-
|-
| 0x3000F || IoctlFailed                       
| 0x30012 || NvError_KernelDriverNotFound
|-
|-
| 0x30010 || AccessDenied
| 0x30013 || NvError_FileNotFound
|-
|-
| 0x30013 || FileNotFound
| 0x30014 || NvError_PathAlreadyExists
|-
|-
| 0xA000E || ModuleNotPresent
| 0xA000E || NvError_ModuleNotPresent
|}
|}


Retrieved from "https://switchbrew.org/wiki/NV_services"