Changes

Jump to navigation Jump to search

Fuses (view source)

Revision as of 18:49, 12 December 2019

8,275 bytes added ,  18:49, 12 December 2019
→‎FUSE_RESERVED_ODM4
Line 1: Line 1:  
The Nintendo Switch makes use of Tegra's fuse driver for a number of operations. This driver is mapped to physical address 0x7000F800 with a total size of 0x400 bytes and exposes several registers for fuse programming.
 
The Nintendo Switch makes use of Tegra's fuse driver for a number of operations. This driver is mapped to physical address 0x7000F800 with a total size of 0x400 bytes and exposes several registers for fuse programming.
   −
Registers from 0x7000F800 to 0x7000F800 + 0xFF can be used to directly program the hardware fuse array, while registers from 0x7000F800 + 0x100 (FUSE_CHIP_REG_START_OFFSET) to 0x7000F800 + 0x3FC (FUSE_CHIP_REG_END_OFFSET) represent cached values read from certain fuses.
+
Registers from 0x7000F800 to 0x7000F800 + 0xFF can be used to directly program the hardware fuse bitmap, while registers from 0x7000F800 + 0x100 (FUSE_CHIP_REG_START_OFFSET) to 0x7000F800 + 0x3FC (FUSE_CHIP_REG_END_OFFSET) represent cached values read from certain fuses.
    
== Registers ==
 
== Registers ==
Line 23: Line 23:  
| 0x7000F80C
 
| 0x7000F80C
 
|-
 
|-
−
| FUSE_FUSETIME_RD1
+
| [[#FUSE_FUSETIME_RD1|FUSE_FUSETIME_RD1]]
 
| 0x7000F810
 
| 0x7000F810
 
|-
 
|-
−
| FUSE_FUSETIME_RD2
+
| [[#FUSE_FUSETIME_RD2|FUSE_FUSETIME_RD2]]
 
| 0x7000F814
 
| 0x7000F814
 
|-
 
|-
−
| FUSE_FUSETIME_PGM1
+
| [[#FUSE_FUSETIME_PGM1|FUSE_FUSETIME_PGM1]]
 
| 0x7000F818
 
| 0x7000F818
 
|-
 
|-
Line 38: Line 38:  
| 0x7000F820
 
| 0x7000F820
 
|-
 
|-
−
| FUSE_FUSEBYPASS
+
| [[#FUSE_FUSEBYPASS|FUSE_FUSEBYPASS]]
 
| 0x7000F824
 
| 0x7000F824
 
|-
 
|-
−
| FUSE_PRIVATEKEYDISABLE
+
| [[#FUSE_PRIVATEKEYDISABLE|FUSE_PRIVATEKEYDISABLE]]
 
| 0x7000F828
 
| 0x7000F828
 
|-
 
|-
Line 50: Line 50:  
| 0x7000F830
 
| 0x7000F830
 
|-
 
|-
−
| FUSE_PWR_GOOD_SW
+
| [[#FUSE_PWR_GOOD_SW|FUSE_PWR_GOOD_SW]]
 
| 0x7000F834
 
| 0x7000F834
 
|-
 
|-
−
| FUSE_PRIV2RESHIFT
+
| [[#FUSE_PRIV2RESHIFT|FUSE_PRIV2RESHIFT]]
 
| 0x7000F83C
 
| 0x7000F83C
 
|-
 
|-
−
| FUSE_FUSETIME_RD3
+
| [[#FUSE_FUSETIME_RD3|FUSE_FUSETIME_RD3]]
 
| 0x7000F84C
 
| 0x7000F84C
 
|-
 
|-
−
| FUSE_PRIVATE_KEY0_NONZERO
+
| [[#FUSE_PRIVATE_KEY0_NONZERO|FUSE_PRIVATE_KEY0_NONZERO]]
 
| 0x7000F880
 
| 0x7000F880
 
|-
 
|-
−
| FUSE_PRIVATE_KEY1_NONZERO
+
| [[#FUSE_PRIVATE_KEY1_NONZERO|FUSE_PRIVATE_KEY1_NONZERO]]
 
| 0x7000F884
 
| 0x7000F884
 
|-
 
|-
−
| FUSE_PRIVATE_KEY2_NONZERO
+
| [[#FUSE_PRIVATE_KEY2_NONZERO|FUSE_PRIVATE_KEY2_NONZERO]]
 
| 0x7000F888
 
| 0x7000F888
 
|-
 
|-
−
| FUSE_PRIVATE_KEY3_NONZERO
+
| [[#FUSE_PRIVATE_KEY3_NONZERO|FUSE_PRIVATE_KEY3_NONZERO]]
 
| 0x7000F88C
 
| 0x7000F88C
 
|-
 
|-
−
| FUSE_PRIVATE_KEY4_NONZERO
+
| [[#FUSE_PRIVATE_KEY4_NONZERO|FUSE_PRIVATE_KEY4_NONZERO]]
 
| 0x7000F890
 
| 0x7000F890
 
|}
 
|}
Line 104: Line 104:  
  0x0D: STATE_WRITE_ADDR_HOLD
 
  0x0D: STATE_WRITE_ADDR_HOLD
 
  0x0E: STATE_FUSE_SRC_HOLD
 
  0x0E: STATE_FUSE_SRC_HOLD
−
  0x0F: STATE_READ_BEFORE_WRITE_SETUP
+
  0x0F: STATE_LOAD_RIR
 +
0x10: STATE_READ_BEFORE_WRITE_SETUP
 +
0x11: STATE_READ_DEASSERT_PD
 
|-
 
|-
 
| 21
 
| 21
Line 131: Line 133:  
|}
 
|}
   −
Before fuse reading/writing the power down mode must be disabled.
+
FUSE_FUSECTRL_CMD takes the fuse controller's operation mode. READ and WRITE interact directly with the hardware fuse bitmap while SENSE_CTRL flushes programmed values into the [[Fuses#Cache_registers|cache registers]].
−
SENSE_CTRL mode flushes programmed values into the [[Fuses#Cache_registers|cache registers]].
     −
==== FUSE_FUSEADDR ====
+
FUSE_FUSECTRL_STATE returns the current state of the fuse controller.
−
This register takes the address of the fuse to be read/written/sensed.
+
 
 +
FUSE_FUSECTRL_MARGIN_READ changes the fuse read trip point setting to margin read mode.
 +
 
 +
FUSE_FUSECTRL_RWL selects the fuse redundancy information row.
   −
==== FUSE_FUSERDATA ====
+
FUSE_FUSECTRL_PD_CTRL controls the fuse macro's power down mode.
−
This register receives the value read from the fuse.
     −
==== FUSE_FUSEWDATA ====
+
FUSE_FUSECTRL_FUSE_SENSE_DONE is set if fuse sensing is completed.
−
This register takes the value to be written to the fuse.
     −
==== FUSE_FUSETIME_PGM2 ====
+
FUSE_FUSECTRL_RECORD_SHIFT_DONE is set if ramrepair shift is completed.
−
This register takes the fuse programming pulse (0xC0 == 19200 kHz).
     −
==== FUSE_PRIV2INTFC_START ====
+
==== FUSE_FUSEADDR ====
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0-7
−
| FUSE_PRIV2INTFC_START_DATA
+
| FUSE_FUSEADDR_VLDFLD
 +
|}
 +
 
 +
Takes the address of the fuse to be read/written/sensed.
 +
 
 +
==== FUSE_FUSERDATA ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| 1
+
| 0-31
−
| FUSE_PRIV2INTFC_START_SKIP_RECORDS
+
| FUSE_FUSERDATA_DATA
 
|}
 
|}
   −
==== FUSE_DISABLEREGPROGRAM ====
+
Returns the value read from the fuse.
−
If set to 0x01, this register disables fuse programming.
     −
==== FUSE_WRITE_ACCESS_SW ====
+
==== FUSE_FUSEWDATA ====
−
If set to 0x01, this register disables software writes to the fuse driver registers.
  −
 
  −
=== Cache registers ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
−
!  Name
+
!  Bits
−
!  Address
+
!  Description
 
|-
 
|-
−
| FUSE_PRODUCTION_MODE
+
| 0-31
−
| 0x7000F900
+
| FUSE_FUSEWDATA_DATA
 +
|}
 +
 
 +
Takes the value to be written to the fuse.
 +
 
 +
==== FUSE_FUSETIME_RD1 ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| FUSE_JTAG_SECUREID_VALID
+
| 0-7
−
| 0x7000F904
+
| FUSE_FUSETIME_RD1_TSUR_MAX
 
|-
 
|-
−
| FUSE_ODM_LOCK
+
| 8-15
−
| 0x7000F908
+
| FUSE_FUSETIME_RD1_TSUR_FUSEOUT
 
|-
 
|-
−
| FUSE_OPT_OPENGL_EN
+
| 16-23
−
| 0x7000F90C
+
| FUSE_FUSETIME_RD1_THR_MAX
 +
|}
 +
 
 +
FUSE_FUSETIME_RD1_TSUR_MAX takes the maximum time for [[#FUSE_FUSECTRL|STATE_READ_SETUP]].
 +
 
 +
FUSE_FUSETIME_RD1_TSUR_FUSEOUT takes the time to spend on [[#FUSE_FUSECTRL|STATE_SAMPLE_FUSES]].
 +
 
 +
FUSE_FUSETIME_RD1_THR_MAX takes the maximum time for [[#FUSE_FUSECTRL|STATE_READ_HOLD]].
 +
 
 +
==== FUSE_FUSETIME_RD2 ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| [[#FUSE_SKU_INFO|FUSE_SKU_INFO]]
+
| 0-15
−
| 0x7000F910
+
| FUSE_FUSETIME_RD2_TWIDTH_RD
 +
|}
 +
 
 +
Takes the read strobe pulse width used during [[#FUSE_FUSECTRL|STATE_READ_STROBE]].
 +
 
 +
==== FUSE_FUSETIME_PGM1 ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| FUSE_CPU_SPEEDO_0_CALIB
+
| 0-7
−
| 0x7000F914
+
| FUSE_FUSETIME_PGM1_TSUP_MAX
 
|-
 
|-
−
| FUSE_CPU_IDDQ_CALIB
+
| 8-15
−
| 0x7000F918
+
| FUSE_FUSETIME_PGM1_TSUP_ADDR
 
|-
 
|-
−
| FUSE_DAC_CRT_CALIB
+
| 16-23
−
| 0x7000F91C
+
| FUSE_FUSETIME_PGM1_THP_ADDR
 
|-
 
|-
−
| FUSE_DAC_HDTV_CALIB
+
| 24-31
−
| 0x7000F920
+
| FUSE_FUSETIME_PGM1_THP_PS
 +
|}
 +
 
 +
FUSE_FUSETIME_PGM1_TSUP_MAX takes the maximum time for [[#FUSE_FUSECTRL|STATE_WRITE_SETUP]].
 +
 
 +
FUSE_FUSETIME_PGM1_TSUP_ADDR takes the time to spend on [[#FUSE_FUSECTRL|STATE_WRITE_ADDR_SETUP]].
 +
 
 +
FUSE_FUSETIME_PGM1_THP_ADDR takes the time to spend on [[#FUSE_FUSECTRL|STATE_WRITE_ADDR_HOLD]].
 +
 
 +
FUSE_FUSETIME_PGM1_THP_PS takes the time to spend on [[#FUSE_FUSECTRL|STATE_FUSE_SRC_HOLD]].
 +
 
 +
==== FUSE_FUSETIME_PGM2 ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| FUSE_DAC_SDTV_CALIB
+
| 0-15
−
| 0x7000F924
+
| FUSE_FUSETIME_PGM2_TWIDTH_PGM
 
|-
 
|-
−
| [[#FUSE_OPT_FT_REV|FUSE_OPT_FT_REV]]
+
| 16-23
−
| 0x7000F928
+
| FUSE_FUSETIME_PGM2_TSUP_PS
 
|-
 
|-
−
| FUSE_CPU_SPEEDO_1_CALIB
+
| 24-31
−
| 0x7000F92C
+
| FUSE_FUSETIME_PGM2_THP_CSPS
 +
|}
 +
 
 +
FUSE_FUSETIME_PGM2_TWIDTH_PGM takes the program strobe pulse width used during [[#FUSE_FUSECTRL|STATE_WRITE_PROGRAM]].
 +
 
 +
FUSE_FUSETIME_PGM2_TSUP_PS takes the time to spend on [[#FUSE_FUSECTRL|STATE_FUSE_SRC_SETUP]].
 +
 
 +
FUSE_FUSETIME_PGM2_THP_CSPS takes the time to spend on [[#FUSE_FUSECTRL|STATE_READ_BEFORE_WRITE_SETUP]].
 +
 
 +
==== FUSE_PRIV2INTFC_START ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| FUSE_CPU_SPEEDO_2_CALIB
+
| 0
−
| 0x7000F930
+
| FUSE_PRIV2INTFC_START_DATA
 
|-
 
|-
−
| FUSE_SOC_SPEEDO_0_CALIB
+
| 1
−
| 0x7000F934
+
| FUSE_PRIV2INTFC_SKIP_RECORDS
 +
|}
 +
 
 +
Controls the interface between the internal fuse chip (INTFC) and the fuse cache registers (PRIV).
 +
 
 +
==== FUSE_FUSEBYPASS ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| [[#FUSE_SOC_SPEEDO_1_CALIB|FUSE_SOC_SPEEDO_1_CALIB]]
+
| 0
−
| 0x7000F938
+
| FUSE_FUSEBYPASS_VAL
−
|-
+
|}
−
| FUSE_SOC_SPEEDO_2_CALIB
+
 
−
| 0x7000F93C
+
If set, this register enables fuse bypass mode. This is only available in hardware where the [[#Bitmap|production_mode]] fuse remains unburnt.
 +
 
 +
==== FUSE_PRIVATEKEYDISABLE ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| FUSE_SOC_IDDQ_CALIB
+
| 0
−
| 0x7000F940
+
| FUSE_PRIVATEKEYDISABLE_VAL
 
|-
 
|-
−
| FUSE_RESERVED_PRODUCTION_WP
+
| 4
−
| 0x7000F944
+
| FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT_VAL
 +
|}
 +
 
 +
If set, this register hides the [[#Bitmap|private_key]] fuses until the next reset.
 +
 
 +
==== FUSE_DISABLEREGPROGRAM ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| [[#FUSE_FA|FUSE_FA]]
+
| 0
−
| 0x7000F948
+
| FUSE_DISABLEREGPROGRAM_VAL
 +
|}
 +
 
 +
If set, this register disables fuse programming until the next reset.
 +
 
 +
==== FUSE_WRITE_ACCESS_SW ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| FUSE_RESERVED_PRODUCTION
+
| 0
−
| 0x7000F94C
+
| FUSE_WRITE_ACCESS_SW_CTRL
 
|-
 
|-
−
| FUSE_HDMI_LANE0_CALIB
+
| 16
−
| 0x7000F950
+
| FUSE_WRITE_ACCESS_SW_STATUS
 +
|}
 +
 
 +
Controls and returns the status of software writes to the fuse cache registers.
 +
 
 +
==== FUSE_PWR_GOOD_SW ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| FUSE_HDMI_LANE1_CALIB
+
| 0
−
| 0x7000F954
+
| FUSE_PWR_GOOD_SW_VAL
 +
|}
 +
 
 +
This register is deprecated and has no effect.
 +
 
 +
==== FUSE_PRIV2RESHIFT ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| FUSE_HDMI_LANE2_CALIB
+
| 0
−
| 0x7000F958
+
| FUSE_PRIV2RESHIFT_TRIGENABLE_VAL
 
|-
 
|-
−
| FUSE_HDMI_LANE3_CALIB
+
| 1
−
| 0x7000F95C
+
| FUSE_PRIV2RESHIFT_TRIG_1_FCPU0_VAL
 
|-
 
|-
−
| FUSE_ENCRYPTION_RATE
+
| 2
−
| 0x7000F960
+
| FUSE_PRIV2RESHIFT_TRIG_1_FCPU1_VAL
 
|-
 
|-
−
| [[#FUSE_PUBLIC_KEY|FUSE_PUBLIC_KEY0]]
+
| 3
−
| 0x7000F964
+
| FUSE_PRIV2RESHIFT_TRIG_1_FCPU2_VAL
 
|-
 
|-
−
| [[#FUSE_PUBLIC_KEY|FUSE_PUBLIC_KEY1]]
+
| 4
−
| 0x7000F968
+
| FUSE_PRIV2RESHIFT_TRIG_1_FCPU3_VAL
 
|-
 
|-
−
| [[#FUSE_PUBLIC_KEY|FUSE_PUBLIC_KEY2]]
+
| 5
−
| 0x7000F96C
+
| FUSE_PRIV2RESHIFT_TRIG_1_FL2_TBANK0_VAL
 
|-
 
|-
−
| [[#FUSE_PUBLIC_KEY|FUSE_PUBLIC_KEY3]]
+
| 6
−
| 0x7000F970
+
| FUSE_PRIV2RESHIFT_TRIG_1_FL2_TBANK1_VAL
 
|-
 
|-
−
| [[#FUSE_PUBLIC_KEY|FUSE_PUBLIC_KEY4]]
+
| 7
−
| 0x7000F974
+
| FUSE_PRIV2RESHIFT_TRIG_1_FL2_TBANK2_VAL
 
|-
 
|-
−
| [[#FUSE_PUBLIC_KEY|FUSE_PUBLIC_KEY5]]
+
| 8
−
| 0x7000F978
+
| FUSE_PRIV2RESHIFT_TRIG_1_FL2_TBANK3_VAL
 
|-
 
|-
−
| [[#FUSE_PUBLIC_KEY|FUSE_PUBLIC_KEY6]]
+
| 9
−
| 0x7000F97C
+
| FUSE_PRIV2RESHIFT_TRIG_1_SCPU_VAL
 
|-
 
|-
−
| [[#FUSE_PUBLIC_KEY|FUSE_PUBLIC_KEY7]]
+
| 10
−
| 0x7000F980
+
| FUSE_PRIV2RESHIFT_TRIG_1_SL2_TBANK_VAL
 
|-
 
|-
−
| FUSE_TSENSOR1_CALIB
+
| 11
−
| 0x7000F984
+
| FUSE_PRIV2RESHIFT_STATUS_1_FCPU0_VAL
 
|-
 
|-
−
| FUSE_TSENSOR2_CALIB
+
| 12
−
| 0x7000F988
+
| FUSE_PRIV2RESHIFT_STATUS_1_FCPU1_VAL
 
|-
 
|-
−
| FUSE_VSENSOR_CALIB
+
| 13
−
| 0x7000F98C
+
| FUSE_PRIV2RESHIFT_STATUS_1_FCPU2_VAL
 
|-
 
|-
−
| [[#FUSE_OPT_CP_REV|FUSE_OPT_CP_REV]]
+
| 14
−
| 0x7000F990
+
| FUSE_PRIV2RESHIFT_STATUS_1_FCPU3_VAL
 
|-
 
|-
−
| FUSE_OPT_PFG
+
| 15
−
| 0x7000F994
+
| FUSE_PRIV2RESHIFT_STATUS_1_FL2_TBANK0_VAL
 
|-
 
|-
−
| FUSE_TSENSOR0_CALIB
+
| 16
−
| 0x7000F998
+
| FUSE_PRIV2RESHIFT_STATUS_1_FL2_TBANK1_VAL
 
|-
 
|-
−
| FUSE_FIRST_BOOTROM_PATCH_SIZE
+
| 17
−
| 0x7000F99C
+
| FUSE_PRIV2RESHIFT_STATUS_1_FL2_TBANK2_VAL
 
|-
 
|-
−
| FUSE_SECURITY_MODE
+
| 18
−
| 0x7000F9A0
+
| FUSE_PRIV2RESHIFT_STATUS_1_FL2_TBANK3_VAL
 
|-
 
|-
−
| [[#FUSE_PRIVATE_KEY|FUSE_PRIVATE_KEY0]]
+
| 19
−
| 0x7000F9A4
+
| FUSE_PRIV2RESHIFT_STATUS_1_SCPU_VAL
 
|-
 
|-
−
| [[#FUSE_PRIVATE_KEY|FUSE_PRIVATE_KEY1]]
+
| 20
−
| 0x7000F9A8
+
| FUSE_PRIV2RESHIFT_STATUS_1_SL2_TBANK_VAL
−
|-
+
|}
−
| [[#FUSE_PRIVATE_KEY|FUSE_PRIVATE_KEY2]]
+
 
−
| 0x7000F9AC
+
Controls and returns the status of the RESHIFT hardware block used in RAM repair.
 +
 
 +
==== FUSE_FUSETIME_RD3 ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| [[#FUSE_PRIVATE_KEY|FUSE_PRIVATE_KEY3]]
+
| 0-15
−
| 0x7000F9B0
+
| FUSE_FUSETIME_RD3_TSUR_PDCS
 +
|}
 +
 
 +
Takes the time to spend on [[#FUSE_FUSECTRL|STATE_READ_DEASSERT_PD]].
 +
 
 +
==== FUSE_PRIVATE_KEY0_NONZERO ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| [[#FUSE_PRIVATE_KEY|FUSE_PRIVATE_KEY4]]
+
| 0
−
| 0x7000F9B4
+
| FUSE_PRIVATE_KEY0_NONZERO_DATA
 +
|}
 +
 
 +
Returns whether [[#Bitmap|private_key0]] is empty or not.
 +
 
 +
==== FUSE_PRIVATE_KEY1_NONZERO ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| FUSE_ARM_JTAG_DIS
+
| 0
−
| 0x7000F9B8
+
| FUSE_PRIVATE_KEY1_NONZERO_DATA
−
|-
+
|}
−
| FUSE_BOOT_DEVICE_INFO
+
 
−
| 0x7000F9BC
+
Returns whether [[#Bitmap|private_key1]] is empty or not.
 +
 
 +
==== FUSE_PRIVATE_KEY2_NONZERO ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| [[#FUSE_RESERVED_SW|FUSE_RESERVED_SW]]
+
| 0
−
| 0x7000F9C0
+
| FUSE_PRIVATE_KEY2_NONZERO_DATA
 +
|}
 +
 
 +
Returns whether [[#Bitmap|private_key2]] is empty or not.
 +
 
 +
==== FUSE_PRIVATE_KEY3_NONZERO ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| FUSE_OPT_VP9_DISABLE
+
| 0
−
| 0x7000F9C4
+
| FUSE_PRIVATE_KEY3_NONZERO_DATA
 +
|}
 +
 
 +
Returns whether [[#Bitmap|private_key3]] is empty or not.
 +
 
 +
==== FUSE_PRIVATE_KEY4_NONZERO ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| [[#FUSE_RESERVED_ODM0|FUSE_RESERVED_ODM0]]
+
| 0
−
| 0x7000F9C8
+
| FUSE_PRIVATE_KEY4_NONZERO_DATA
−
|-
+
|}
−
| [[#FUSE_RESERVED_ODM1|FUSE_RESERVED_ODM1]]
+
 
−
| 0x7000F9CC
+
Returns whether [[#Bitmap|private_key4]] is empty or not.
 +
 
 +
=== Cache registers ===
 +
{| class="wikitable" border="1"
 +
!  Name
 +
!  Address
 
|-
 
|-
−
| [[#FUSE_RESERVED_ODM2|FUSE_RESERVED_ODM2]]
+
| FUSE_PRODUCTION_MODE
−
| 0x7000F9D0
+
| 0x7000F900
 
|-
 
|-
−
| [[#FUSE_RESERVED_ODM3|FUSE_RESERVED_ODM3]]
+
| FUSE_JTAG_SECUREID_VALID
−
| 0x7000F9D4
+
| 0x7000F904
 
|-
 
|-
−
| [[#FUSE_RESERVED_ODM4|FUSE_RESERVED_ODM4]]
+
| FUSE_ODM_LOCK
−
| 0x7000F9D8
+
| 0x7000F908
 
|-
 
|-
−
| FUSE_RESERVED_ODM5
+
| FUSE_OPT_OPENGL_EN
−
| 0x7000F9DC
+
| 0x7000F90C
 
|-
 
|-
−
| [[#FUSE_RESERVED_ODM6|FUSE_RESERVED_ODM6]]
+
| [[#FUSE_SKU_INFO|FUSE_SKU_INFO]]
−
| 0x7000F9E0
+
| 0x7000F910
 
|-
 
|-
−
| [[#FUSE_RESERVED_ODM7|FUSE_RESERVED_ODM7]]
+
| FUSE_CPU_SPEEDO_0_CALIB
−
| 0x7000F9E4
+
| 0x7000F914
 
|-
 
|-
−
| FUSE_OBS_DIS
+
| FUSE_CPU_IDDQ_CALIB
−
| 0x7000F9E8
+
| 0x7000F918
 
|-
 
|-
−
| FUSE_NOR_INFO
+
| FUSE_DAC_CRT_CALIB
−
| 0x7000F9EC
+
| 0x7000F91C
 
|-
 
|-
−
| FUSE_USB_CALIB
+
| FUSE_DAC_HDTV_CALIB
−
| 0x7000F9F0
+
| 0x7000F920
 
|-
 
|-
−
| FUSE_SKU_DIRECT_CONFIG
+
| FUSE_DAC_SDTV_CALIB
−
| 0x7000F9F4
+
| 0x7000F924
 
|-
 
|-
−
| FUSE_KFUSE_PRIVKEY_CTRL
+
| [[#FUSE_OPT_FT_REV|FUSE_OPT_FT_REV]]
−
| 0x7000F9F8
+
| 0x7000F928
 
|-
 
|-
−
| FUSE_PACKAGE_INFO
+
| FUSE_CPU_SPEEDO_1_CALIB
−
| 0x7000F9FC
+
| 0x7000F92C
 
|-
 
|-
−
| FUSE_OPT_VENDOR_CODE
+
| FUSE_CPU_SPEEDO_2_CALIB
−
| 0x7000FA00
+
| 0x7000F930
 
|-
 
|-
−
| FUSE_OPT_FAB_CODE
+
| FUSE_SOC_SPEEDO_0_CALIB
−
| 0x7000FA04
+
| 0x7000F934
 
|-
 
|-
−
| FUSE_OPT_LOT_CODE_0
+
| [[#FUSE_SOC_SPEEDO_1_CALIB|FUSE_SOC_SPEEDO_1_CALIB]]
−
| 0x7000FA08
+
| 0x7000F938
 
|-
 
|-
−
| FUSE_OPT_LOT_CODE_1
+
| FUSE_SOC_SPEEDO_2_CALIB
−
| 0x7000FA0C
+
| 0x7000F93C
 
|-
 
|-
−
| FUSE_OPT_WAFER_ID
+
| FUSE_SOC_IDDQ_CALIB
−
| 0x7000FA10
+
| 0x7000F940
 
|-
 
|-
−
| FUSE_OPT_X_COORDINATE
+
| FUSE_RESERVED_PRODUCTION_WP
−
| 0x7000FA14
+
| 0x7000F944
 
|-
 
|-
−
| FUSE_OPT_Y_COORDINATE
+
| [[#FUSE_FA|FUSE_FA]]
−
| 0x7000FA18
+
| 0x7000F948
 
|-
 
|-
−
| FUSE_OPT_SEC_DEBUG_EN
+
| FUSE_RESERVED_PRODUCTION
−
| 0x7000FA1C
+
| 0x7000F94C
 
|-
 
|-
−
| FUSE_OPT_OPS_RESERVED
+
| FUSE_HDMI_LANE0_CALIB
−
| 0x7000FA20
+
| 0x7000F950
 
|-
 
|-
−
| FUSE_SATA_CALIB
+
| FUSE_HDMI_LANE1_CALIB
−
| 0x7000FA24
+
| 0x7000F954
 
|-
 
|-
−
| FUSE_GPU_IDDQ_CALIB
+
| FUSE_HDMI_LANE2_CALIB
−
| 0x7000FA28
+
| 0x7000F958
 
|-
 
|-
−
| FUSE_TSENSOR3_CALIB
+
| FUSE_HDMI_LANE3_CALIB
−
| 0x7000FA2C
+
| 0x7000F95C
 
|-
 
|-
−
| FUSE_SKU_BOND_OUT_L
+
| FUSE_ENCRYPTION_RATE
−
| 0x7000FA30
+
| 0x7000F960
 
|-
 
|-
−
| FUSE_SKU_BOND_OUT_H
+
| [[#FUSE_PUBLIC_KEY|FUSE_PUBLIC_KEY0]]
−
| 0x7000FA34
+
| 0x7000F964
 
|-
 
|-
−
| FUSE_SKU_BOND_OUT_U
+
| [[#FUSE_PUBLIC_KEY|FUSE_PUBLIC_KEY1]]
−
| 0x7000FA38
+
| 0x7000F968
 
|-
 
|-
−
| FUSE_SKU_BOND_OUT_V
+
| [[#FUSE_PUBLIC_KEY|FUSE_PUBLIC_KEY2]]
−
| 0x7000FA3C
+
| 0x7000F96C
 
|-
 
|-
−
| FUSE_SKU_BOND_OUT_W
+
| [[#FUSE_PUBLIC_KEY|FUSE_PUBLIC_KEY3]]
−
| 0x7000FA40
+
| 0x7000F970
 
|-
 
|-
−
| FUSE_OPT_SAMPLE_TYPE
+
| [[#FUSE_PUBLIC_KEY|FUSE_PUBLIC_KEY4]]
−
| 0x7000FA44
+
| 0x7000F974
 
|-
 
|-
−
| FUSE_OPT_SUBREVISION
+
| [[#FUSE_PUBLIC_KEY|FUSE_PUBLIC_KEY5]]
−
| 0x7000FA48
+
| 0x7000F978
 
|-
 
|-
−
| FUSE_OPT_SW_RESERVED_0
+
| [[#FUSE_PUBLIC_KEY|FUSE_PUBLIC_KEY6]]
−
| 0x7000FA4C
+
| 0x7000F97C
 
|-
 
|-
−
| FUSE_OPT_SW_RESERVED_1
+
| [[#FUSE_PUBLIC_KEY|FUSE_PUBLIC_KEY7]]
−
| 0x7000FA50
+
| 0x7000F980
 
|-
 
|-
−
| FUSE_TSENSOR4_CALIB
+
| FUSE_TSENSOR1_CALIB
−
| 0x7000FA54
+
| 0x7000F984
 
|-
 
|-
−
| FUSE_TSENSOR5_CALIB
+
| FUSE_TSENSOR2_CALIB
−
| 0x7000FA58
+
| 0x7000F988
 
|-
 
|-
−
| FUSE_TSENSOR6_CALIB
+
| FUSE_VSENSOR_CALIB
−
| 0x7000FA5C
+
| 0x7000F98C
 
|-
 
|-
−
| FUSE_TSENSOR7_CALIB
+
| [[#FUSE_OPT_CP_REV|FUSE_OPT_CP_REV]]
−
| 0x7000FA60
+
| 0x7000F990
 
|-
 
|-
−
| FUSE_OPT_PRIV_SEC_EN
+
| FUSE_OPT_PFG
−
| 0x7000FA64
+
| 0x7000F994
 
|-
 
|-
−
| [[#FUSE_PKC_DISABLE|FUSE_PKC_DISABLE]]
+
| FUSE_TSENSOR0_CALIB
−
| 0x7000FA68
+
| 0x7000F998
 
|-
 
|-
−
| FUSE_FUSE2TSEC_DEBUG_DISABLE
+
| FUSE_FIRST_BOOTROM_PATCH_SIZE
−
| 0x7000FA7C
+
| 0x7000F99C
 
|-
 
|-
−
| FUSE_TSENSOR_COMMON
+
| FUSE_SECURITY_MODE
−
| 0x7000FA80
+
| 0x7000F9A0
 
|-
 
|-
−
| FUSE_OPT_CP_BIN
+
| [[#FUSE_PRIVATE_KEY|FUSE_PRIVATE_KEY0]]
−
| 0x7000FA84
+
| 0x7000F9A4
 
|-
 
|-
−
| FUSE_OPT_GPU_DISABLE
+
| [[#FUSE_PRIVATE_KEY|FUSE_PRIVATE_KEY1]]
−
| 0x7000FA88
+
| 0x7000F9A8
 
|-
 
|-
−
| FUSE_OPT_FT_BIN
+
| [[#FUSE_PRIVATE_KEY|FUSE_PRIVATE_KEY2]]
−
| 0x7000FA8C
+
| 0x7000F9AC
 
|-
 
|-
−
| FUSE_OPT_DONE_MAP
+
| [[#FUSE_PRIVATE_KEY|FUSE_PRIVATE_KEY3]]
−
| 0x7000FA90
+
| 0x7000F9B0
 
|-
 
|-
−
| FUSE_APB2JTAG_DISABLE
+
| [[#FUSE_PRIVATE_KEY|FUSE_PRIVATE_KEY4]]
−
| 0x7000FA98
+
| 0x7000F9B4
 
|-
 
|-
−
| FUSE_ODM_INFO
+
| FUSE_ARM_JTAG_DIS
−
| 0x7000FA9C
+
| 0x7000F9B8
 
|-
 
|-
−
| FUSE_ARM_CRYPT_DE_FEATURE
+
| FUSE_BOOT_DEVICE_INFO
−
| 0x7000FAA8
+
| 0x7000F9BC
 
|-
 
|-
−
| FUSE_WOA_SKU_FLAG
+
| [[#FUSE_RESERVED_SW|FUSE_RESERVED_SW]]
−
| 0x7000FAC0
+
| 0x7000F9C0
 
|-
 
|-
−
| FUSE_ECO_RESERVE_1
+
| FUSE_OPT_VP9_DISABLE
−
| 0x7000FAC4
+
| 0x7000F9C4
 
|-
 
|-
−
| FUSE_GCPLEX_CONFIG_FUSE
+
| [[#FUSE_RESERVED_ODM0|FUSE_RESERVED_ODM0]]
−
| 0x7000FAC8
+
| 0x7000F9C8
 
|-
 
|-
−
| FUSE_PRODUCTION_MONTH
+
| [[#FUSE_RESERVED_ODM1|FUSE_RESERVED_ODM1]]
−
| 0x7000FACC
+
| 0x7000F9CC
 
|-
 
|-
−
| FUSE_RAM_REPAIR_INDICATOR
+
| [[#FUSE_RESERVED_ODM2|FUSE_RESERVED_ODM2]]
−
| 0x7000FAD0
+
| 0x7000F9D0
 
|-
 
|-
−
| FUSE_TSENSOR9_CALIB
+
| [[#FUSE_RESERVED_ODM3|FUSE_RESERVED_ODM3]]
−
| 0x7000FAD4
+
| 0x7000F9D4
 
|-
 
|-
−
| FUSE_VMIN_CALIBRATION
+
| [[#FUSE_RESERVED_ODM4|FUSE_RESERVED_ODM4]]
−
| 0x7000FADC
+
| 0x7000F9D8
 
|-
 
|-
−
| FUSE_AGING_SENSOR_CALIBRATION
+
| FUSE_RESERVED_ODM5
−
| 0x7000FAE0
+
| 0x7000F9DC
 
|-
 
|-
−
| FUSE_DEBUG_AUTHENTICATION
+
| [[#FUSE_RESERVED_ODM6|FUSE_RESERVED_ODM6]]
−
| 0x7000FAE4
+
| 0x7000F9E0
 
|-
 
|-
−
| FUSE_SECURE_PROVISION_INDEX
+
| [[#FUSE_RESERVED_ODM7|FUSE_RESERVED_ODM7]]
−
| 0x7000FAE8
+
| 0x7000F9E4
 
|-
 
|-
−
| FUSE_SECURE_PROVISION_INFO
+
| FUSE_OBS_DIS
−
| 0x7000FAEC
+
| 0x7000F9E8
 
|-
 
|-
−
| FUSE_OPT_GPU_DISABLE_CP1
+
| FUSE_NOR_INFO
−
| 0x7000FAF0
+
| 0x7000F9EC
 
|-
 
|-
−
| FUSE_SPARE_ENDIS
+
| FUSE_USB_CALIB
−
| 0x7000FAF4
+
| 0x7000F9F0
 
|-
 
|-
−
| FUSE_ECO_RESERVE_0
+
| FUSE_SKU_DIRECT_CONFIG
−
| 0x7000FAF8
+
| 0x7000F9F4
 
|-
 
|-
−
| FUSE_SPARE_REALIGNMENT_REG_OLD
+
| FUSE_KFUSE_PRIVKEY_CTRL
−
| 0x7000FAFC
+
| 0x7000F9F8
 
|-
 
|-
−
| FUSE_RESERVED_CALIB0
+
| FUSE_PACKAGE_INFO
−
| 0x7000FB04
+
| 0x7000F9FC
 
|-
 
|-
−
| FUSE_RESERVED_CALIB1
+
| FUSE_OPT_VENDOR_CODE
−
| 0x7000FB08
+
| 0x7000FA00
 
|-
 
|-
−
| FUSE_OPT_GPU_TPC0_DISABLE
+
| FUSE_OPT_FAB_CODE
−
| 0x7000FB0C
+
| 0x7000FA04
 
|-
 
|-
−
| FUSE_OPT_GPU_TPC0_DISABLE_CP1
+
| FUSE_OPT_LOT_CODE_0
−
| 0x7000FB10
+
| 0x7000FA08
 
|-
 
|-
−
| FUSE_OPT_CPU_DISABLE
+
| FUSE_OPT_LOT_CODE_1
−
| 0x7000FB14
+
| 0x7000FA0C
 
|-
 
|-
−
| FUSE_OPT_CPU_DISABLE_CP1
+
| FUSE_OPT_WAFER_ID
−
| 0x7000FB18
+
| 0x7000FA10
 
|-
 
|-
−
| FUSE_TSENSOR10_CALIB
+
| FUSE_OPT_X_COORDINATE
−
| 0x7000FB1C
+
| 0x7000FA14
 
|-
 
|-
−
| FUSE_TSENSOR10_CALIB_AUX
+
| FUSE_OPT_Y_COORDINATE
−
| 0x7000FB20
+
| 0x7000FA18
 
|-
 
|-
−
| FUSE_OPT_RAM_SVOP_DP
+
| [[#FUSE_OPT_SEC_DEBUG_EN|FUSE_OPT_SEC_DEBUG_EN]]
−
| 0x7000FB24
+
| 0x7000FA1C
 
|-
 
|-
−
| FUSE_OPT_RAM_SVOP_PDP
+
| FUSE_OPT_OPS_RESERVED
−
| 0x7000FB28
+
| 0x7000FA20
 
|-
 
|-
−
| FUSE_OPT_RAM_SVOP_REG
+
| FUSE_SATA_CALIB
−
| 0x7000FB2C
+
| 0x7000FA24
 
|-
 
|-
−
| FUSE_OPT_RAM_SVOP_SP
+
| FUSE_GPU_IDDQ_CALIB
−
| 0x7000FB30
+
| 0x7000FA28
 
|-
 
|-
−
| FUSE_OPT_RAM_SVOP_SMPDP
+
| FUSE_TSENSOR3_CALIB
−
| 0x7000FB34
+
| 0x7000FA2C
 
|-
 
|-
−
| FUSE_OPT_GPU_TPC0_DISABLE_CP2
+
| FUSE_SKU_BOND_OUT_L
−
| 0x7000FB38
+
| 0x7000FA30
 
|-
 
|-
−
| FUSE_OPT_GPU_TPC1_DISABLE
+
| FUSE_SKU_BOND_OUT_H
−
| 0x7000FB3C
+
| 0x7000FA34
 
|-
 
|-
−
| FUSE_OPT_GPU_TPC1_DISABLE_CP1
+
| FUSE_SKU_BOND_OUT_U
−
| 0x7000FB40
+
| 0x7000FA38
 
|-
 
|-
−
| FUSE_OPT_GPU_TPC1_DISABLE_CP2
+
| FUSE_SKU_BOND_OUT_V
−
| 0x7000FB44
+
| 0x7000FA3C
 
|-
 
|-
−
| FUSE_OPT_CPU_DISABLE_CP2
+
| FUSE_SKU_BOND_OUT_W
−
| 0x7000FB48
+
| 0x7000FA40
 
|-
 
|-
−
| FUSE_OPT_GPU_DISABLE_CP2
+
| FUSE_OPT_SAMPLE_TYPE
−
| 0x7000FB4C
+
| 0x7000FA44
 
|-
 
|-
−
| FUSE_USB_CALIB_EXT
+
| FUSE_OPT_SUBREVISION
−
| 0x7000FB50
+
| 0x7000FA48
 
|-
 
|-
−
| FUSE_RESERVED_FIELD
+
| FUSE_OPT_SW_RESERVED_0
−
| 0x7000FB54
+
| 0x7000FA4C
 
|-
 
|-
−
| FUSE_OPT_ECC_EN
+
| FUSE_OPT_SW_RESERVED_1
−
| 0x7000FB58
+
| 0x7000FA50
 
|-
 
|-
−
| FUSE_SPARE_REALIGNMENT_REG
+
| FUSE_TSENSOR4_CALIB
−
| 0x7000FB7C
+
| 0x7000FA54
 
|-
 
|-
−
| FUSE_SPARE_BIT_0
+
| FUSE_TSENSOR5_CALIB
−
| 0x7000FB80
+
| 0x7000FA58
 
|-
 
|-
−
| FUSE_SPARE_BIT_1
+
| FUSE_TSENSOR6_CALIB
−
| 0x7000FB84
+
| 0x7000FA5C
 
|-
 
|-
−
| [[#FUSE_SPARE_BIT_2|FUSE_SPARE_BIT_2]]
+
| FUSE_TSENSOR7_CALIB
−
| 0x7000FB88
+
| 0x7000FA60
 
|-
 
|-
−
| [[#FUSE_SPARE_BIT_3|FUSE_SPARE_BIT_3]]
+
| [[#FUSE_OPT_PRIV_SEC_EN|FUSE_OPT_PRIV_SEC_EN]]
−
| 0x7000FB8C
+
| 0x7000FA64
 
|-
 
|-
−
| [[#FUSE_SPARE_BIT_4|FUSE_SPARE_BIT_4]]
+
| [[#FUSE_PKC_DISABLE|FUSE_PKC_DISABLE]]
−
| 0x7000FB90
+
| 0x7000FA68
 
|-
 
|-
−
| [[#FUSE_SPARE_BIT_5|FUSE_SPARE_BIT_5]]
+
| FUSE_FUSE2TSEC_DEBUG_DISABLE
−
| 0x7000FB94
+
| 0x7000FA7C
 
|-
 
|-
−
| FUSE_SPARE_BIT_6
+
| FUSE_TSENSOR_COMMON
−
| 0x7000FB98
+
| 0x7000FA80
 
|-
 
|-
−
| FUSE_SPARE_BIT_7
+
| FUSE_OPT_CP_BIN
−
| 0x7000FB9C
+
| 0x7000FA84
 
|-
 
|-
−
| FUSE_SPARE_BIT_8
+
| FUSE_OPT_GPU_DISABLE
−
| 0x7000FBA0
+
| 0x7000FA88
 
|-
 
|-
−
| FUSE_SPARE_BIT_9
+
| FUSE_OPT_FT_BIN
−
| 0x7000FBA4
+
| 0x7000FA8C
 
|-
 
|-
−
| FUSE_SPARE_BIT_10
+
| FUSE_OPT_DONE_MAP
−
| 0x7000FBA8
+
| 0x7000FA90
 
|-
 
|-
−
| FUSE_SPARE_BIT_11
+
| FUSE_APB2JTAG_DISABLE
−
| 0x7000FBAC
+
| 0x7000FA98
 
|-
 
|-
−
| FUSE_SPARE_BIT_12
+
| FUSE_ODM_INFO
−
| 0x7000FBB0
+
| 0x7000FA9C
 
|-
 
|-
−
| FUSE_SPARE_BIT_13
+
| FUSE_ARM_CRYPT_DE_FEATURE
−
| 0x7000FBB4
+
| 0x7000FAA8
 
|-
 
|-
−
| FUSE_SPARE_BIT_14
+
| FUSE_WOA_SKU_FLAG
−
| 0x7000FBB8
+
| 0x7000FAC0
 
|-
 
|-
−
| FUSE_SPARE_BIT_15
+
| FUSE_ECO_RESERVE_1
−
| 0x7000FBBC
+
| 0x7000FAC4
 
|-
 
|-
−
| FUSE_SPARE_BIT_16
+
| FUSE_GCPLEX_CONFIG_FUSE
−
| 0x7000FBC0
+
| 0x7000FAC8
 
|-
 
|-
−
| FUSE_SPARE_BIT_17
+
| FUSE_PRODUCTION_MONTH
−
| 0x7000FBC4
+
| 0x7000FACC
 
|-
 
|-
−
| FUSE_SPARE_BIT_18
+
| FUSE_RAM_REPAIR_INDICATOR
−
| 0x7000FBC8
+
| 0x7000FAD0
 
|-
 
|-
−
| FUSE_SPARE_BIT_19
+
| FUSE_TSENSOR9_CALIB
−
| 0x7000FBCC
+
| 0x7000FAD4
 
|-
 
|-
−
| FUSE_SPARE_BIT_20
+
| FUSE_VMIN_CALIBRATION
−
| 0x7000FBD0
+
| 0x7000FADC
 
|-
 
|-
−
| FUSE_SPARE_BIT_21
+
| FUSE_AGING_SENSOR_CALIBRATION
−
| 0x7000FBD4
+
| 0x7000FAE0
 
|-
 
|-
−
| FUSE_SPARE_BIT_22
+
| FUSE_DEBUG_AUTHENTICATION
−
| 0x7000FBD8
+
| 0x7000FAE4
 
|-
 
|-
−
| FUSE_SPARE_BIT_23
+
| FUSE_SECURE_PROVISION_INDEX
−
| 0x7000FBDC
+
| 0x7000FAE8
 
|-
 
|-
−
| FUSE_SPARE_BIT_24
+
| FUSE_SECURE_PROVISION_INFO
−
| 0x7000FBE0
+
| 0x7000FAEC
 
|-
 
|-
−
| FUSE_SPARE_BIT_25
+
| FUSE_OPT_GPU_DISABLE_CP1
−
| 0x7000FBE4
+
| 0x7000FAF0
 
|-
 
|-
−
| FUSE_SPARE_BIT_26
+
| FUSE_SPARE_ENDIS
−
| 0x7000FBE8
+
| 0x7000FAF4
 
|-
 
|-
−
| FUSE_SPARE_BIT_27
+
| [[#FUSE_ECO_RESERVE_0|FUSE_ECO_RESERVE_0]]
−
| 0x7000FBEC
+
| 0x7000FAF8
 
|-
 
|-
−
| FUSE_SPARE_BIT_28
+
| FUSE_RESERVED_CALIB0
−
| 0x7000FBF0
+
| 0x7000FB04
 
|-
 
|-
−
| FUSE_SPARE_BIT_29
+
| FUSE_RESERVED_CALIB1
−
| 0x7000FBF4
+
| 0x7000FB08
 
|-
 
|-
−
| FUSE_SPARE_BIT_30
+
| FUSE_OPT_GPU_TPC0_DISABLE
−
| 0x7000FBF8
+
| 0x7000FB0C
 +
|-
 +
| FUSE_OPT_GPU_TPC0_DISABLE_CP1
 +
| 0x7000FB10
 +
|-
 +
| FUSE_OPT_CPU_DISABLE
 +
| 0x7000FB14
 +
|-
 +
| FUSE_OPT_CPU_DISABLE_CP1
 +
| 0x7000FB18
 +
|-
 +
| FUSE_TSENSOR10_CALIB
 +
| 0x7000FB1C
 
|-
 
|-
−
| FUSE_SPARE_BIT_31
+
| FUSE_TSENSOR10_CALIB_AUX
−
| 0x7000FBFC
+
| 0x7000FB20
−
|}
  −
 
  −
==== FUSE_SKU_INFO ====
  −
Stores the SKU ID (must be 0x83).
  −
 
  −
==== FUSE_OPT_FT_REV ====
  −
Stores the FT (Final Test) revision.
  −
 
  −
Original launch units have this value set to 0xA0 (revision 5.0). The first batch of patched units have this value set to 0xC0 (revision 6.0). The second batch of patched units have this value set to 0xE0 (revision 7.0)
  −
 
  −
==== FUSE_FA ====
  −
Stores failure analysis mode.
  −
 
  −
==== FUSE_SOC_SPEEDO_1_CALIB ====
  −
Stores the bootrom patch version.
  −
 
  −
==== FUSE_RESERVED_ODM0 ====
  −
This stores an hardware ID.
  −
 
  −
==== FUSE_RESERVED_ODM1 ====
  −
This stores an hardware ID.
  −
 
  −
==== FUSE_RESERVED_ODM2 ====
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0-4
+
| FUSE_OPT_RAM_SVOP_DP
−
| [5.0.0+] Used as key generation (patched units only)
+
| 0x7000FB24
−
|}
  −
 
  −
This stores an hardware ID in original launch units, but in patched units it stores a single value (key generation).
  −
 
  −
==== FUSE_RESERVED_ODM3 ====
  −
This stores an hardware ID in original launch units, but in patched units it's empty.
  −
 
  −
==== FUSE_RESERVED_ODM4 ====
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0-1
+
| FUSE_OPT_RAM_SVOP_PDP
−
| Unit type (3 = debug; 0 = retail)
+
| 0x7000FB28
 
|-
 
|-
−
| 2
+
| FUSE_OPT_RAM_SVOP_REG
−
| Unknown config (must be 1 on retail)
+
| 0x7000FB2C
 +
|-
 +
| FUSE_OPT_RAM_SVOP_SP
 +
| 0x7000FB30
 
|-
 
|-
−
| [1.0.0-3.0.2] 3-5
+
| FUSE_OPT_RAM_SVOP_SMPDP
−
[4.0.0+] 3-7
+
| 0x7000FB34
−
| DRAM ID
   
|-
 
|-
−
| 8
+
| FUSE_OPT_GPU_TPC0_DISABLE_CP2
−
| Unknown config mask (must be 0 on retail)
+
| 0x7000FB38
 
|-
 
|-
−
| 9
+
| FUSE_OPT_GPU_TPC1_DISABLE
−
| Unit type mask (0 = debug; 1 = retail)
+
| 0x7000FB3C
 
|-
 
|-
−
| 10
+
| FUSE_OPT_GPU_TPC1_DISABLE_CP1
−
| [3.0.0+] Kiosk mode (0 = retail; 1 = kiosk)
+
| 0x7000FB40
 
|-
 
|-
−
| 11
+
| FUSE_OPT_GPU_TPC1_DISABLE_CP2
−
| [5.0.0+] Unit patch flag (0 = unpatched; 1 = patched)
+
| 0x7000FB44
 
|-
 
|-
−
| 16-19
+
| FUSE_OPT_CPU_DISABLE_CP2
−
| [4.0.0+] New unit type (0 = Erista; 1 = Mariko; 2 = Mariko Lite)
+
| 0x7000FB48
−
|}
  −
 
  −
This stores some device configuration parameters.
  −
 
  −
==== FUSE_RESERVED_ODM6 ====
  −
This register returns the value programmed into fuse [[#reserved_odm6|reserved_odm6]].
  −
 
  −
==== FUSE_RESERVED_ODM7 ====
  −
This register returns the value programmed into fuse [[#reserved_odm7|reserved_odm7]].
  −
 
  −
==== FUSE_PUBLIC_KEY ====
  −
This stores the SHA256 hash of the 2048-bit RSA key expected at BCT+0x210.
  −
 
  −
==== FUSE_OPT_CP_REV ====
  −
Stores the CP (Chip Probing) revision.
  −
 
  −
Original launch units have this value set to 0xA0 (revision 5.0). Patched units have this value set to 0x103 (revision 8.3).
  −
 
  −
==== FUSE_PRIVATE_KEY ====
  −
This stores the 160-bit private key (128 bit SBK + 32-bit device key).
  −
Reads to these registers after the SBK is locked out produce all-FF output.
  −
 
  −
==== FUSE_RESERVED_SW ====
  −
{| class="wikitable" border="1"
  −
!  Bits
  −
!  Description
   
|-
 
|-
−
| 0-2
+
| FUSE_OPT_GPU_DISABLE_CP2
−
| Boot device
+
| 0x7000FB4C
 
|-
 
|-
−
| 3
+
| FUSE_USB_CALIB_EXT
−
| Skip device selection straps (0 = don't skip; 1 = skip)
+
| 0x7000FB50
 
|-
 
|-
−
| 4
+
| FUSE_RESERVED_FIELD
−
| ENABLE_CHARGER_DETECT
+
| 0x7000FB54
 +
|-
 +
| FUSE_OPT_ECC_EN
 +
| 0x7000FB58
 +
|-
 +
| FUSE_SPARE_REALIGNMENT_REG
 +
| 0x7000FB7C
 +
|-
 +
| FUSE_SPARE_BIT_0
 +
| 0x7000FB80
 
|-
 
|-
−
| 5
+
| FUSE_SPARE_BIT_1
−
| ENABLE_WATCHDOG
+
| 0x7000FB84
 
|-
 
|-
−
| 6
+
| [[#FUSE_SPARE_BIT_2|FUSE_SPARE_BIT_2]]
−
| Forced RCM two button mode (0 = Only VOLUME_UP; 1 = VOLUME_UP + HOME)
+
| 0x7000FB88
 
|-
 
|-
−
| 7
+
| [[#FUSE_SPARE_BIT_3|FUSE_SPARE_BIT_3]]
−
| RCM USB controller mode (0 = USB 2.0; 1 = XUSB)
+
| 0x7000FB8C
−
|}
  −
 
  −
This caches the value of the reserved_sw fuse from the hardware bitmap.
  −
 
  −
Original launch units have the RCM USB controller mode set to USB 2.0, while the first batch of patched units have the RCM USB controller mode set to XUSB.
  −
 
  −
==== FUSE_PKC_DISABLE ====
  −
This caches the value of the pkc_disable fuse from the hardware array.
  −
 
  −
==== FUSE_SPARE_BIT_2 ====
  −
Stores part of the speedo fusing revision.
  −
 
  −
==== FUSE_SPARE_BIT_3 ====
  −
Stores part of the speedo fusing revision.
  −
 
  −
==== FUSE_SPARE_BIT_4 ====
  −
Stores part of the speedo fusing revision.
  −
 
  −
==== FUSE_SPARE_BIT_5 ====
  −
Must be non-zero on retail units, otherwise the first bootloader panics.
  −
On debug units it can be zero, which tells the bootloader to choose from two debug master key seeds. If set to non-zero on a debug unit, it tells the bootloader to choose from two master key seeds (with the second one being the retail master key seed).
  −
 
  −
[4.0.0+] This value is no longer used during boot.
  −
 
  −
== Bitmap ==
  −
The actual hardware fuses are stored in a bitmap and may be programmed through the fuse driver after enabling fuse programming.
  −
 
  −
Fuse numbers are relative to the start of the fuse bitmap where each element is a 4 byte word and has a redundant alias. A single fuse write operation must always write the same value to '''fuse_bitmap + ((fuse_number + 0) << 2)''' (PRIMARY_ALIAS) and '''fuse_bitmap + ((fuse_number + 1) << 2)''' (REDUNDANT_ALIAS). However, after offset 0x180 in the fuse bitmap, fuses no longer have a redundant alias.
  −
 
  −
Below is a list of common fuses used by Tegra devices (and applicable to the Switch).
  −
 
  −
{| class="wikitable" border="1"
  −
!  Name
  −
!  Number
  −
!  Redundant number
  −
!  Bits
   
|-
 
|-
−
| enable_fuse_program
+
| [[#FUSE_SPARE_BIT_4|FUSE_SPARE_BIT_4]]
−
| 0
+
| 0x7000FB90
−
| 1
  −
| 0
   
|-
 
|-
−
| disable_fuse_program
+
| [[#FUSE_SPARE_BIT_5|FUSE_SPARE_BIT_5]]
−
| 0
+
| 0x7000FB94
−
| 1
  −
| 1
   
|-
 
|-
−
| bypass_fuses
+
| FUSE_SPARE_BIT_6
−
| 0
+
| 0x7000FB98
−
| 1
  −
| 2
   
|-
 
|-
−
| jtag_direct_access_disable
+
| FUSE_SPARE_BIT_7
−
| 0
+
| 0x7000FB9C
−
| 1
  −
| 3
   
|-
 
|-
−
| production_mode
+
| FUSE_SPARE_BIT_8
−
| 0
+
| 0x7000FBA0
−
| 1
  −
| 4
   
|-
 
|-
−
| jtag_secureid_valid
+
| FUSE_SPARE_BIT_9
−
| 0
+
| 0x7000FBA4
−
| 1
  −
| 5
   
|-
 
|-
−
| odm_lock
+
| FUSE_SPARE_BIT_10
−
| 0
+
| 0x7000FBA8
−
| 1
+
|-
−
| 6-9
+
| FUSE_SPARE_BIT_11
 +
| 0x7000FBAC
 
|-
 
|-
−
| fa_mode
+
| FUSE_SPARE_BIT_12
−
| 0
+
| 0x7000FBB0
−
| 1
  −
| 10
   
|-
 
|-
−
| security_mode
+
| FUSE_SPARE_BIT_13
−
| 0
+
| 0x7000FBB4
−
| 1
  −
| 11
   
|-
 
|-
−
| arm_debug_dis
+
| FUSE_SPARE_BIT_14
−
| 0
+
| 0x7000FBB8
−
| 1
  −
| 12
   
|-
 
|-
−
| obs_dis
+
| FUSE_SPARE_BIT_15
−
| 0
+
| 0x7000FBBC
−
| 1
  −
| 13
   
|-
 
|-
−
| public_key0
+
| FUSE_SPARE_BIT_16
−
| 10
+
| 0x7000FBC0
−
| 11
  −
| 30-31
   
|-
 
|-
−
| public_key0
+
| FUSE_SPARE_BIT_17
−
| 12
+
| 0x7000FBC4
−
| 13
  −
| 0-29
   
|-
 
|-
−
| public_key1
+
| FUSE_SPARE_BIT_18
−
| 12
+
| 0x7000FBC8
−
| 13
  −
| 30-31
   
|-
 
|-
−
| public_key1
+
| FUSE_SPARE_BIT_19
−
| 14
+
| 0x7000FBCC
−
| 15
  −
| 0-29
   
|-
 
|-
−
| public_key2
+
| FUSE_SPARE_BIT_20
−
| 14
+
| 0x7000FBD0
−
| 15
  −
| 30-31
   
|-
 
|-
−
| public_key2
+
| FUSE_SPARE_BIT_21
−
| 16
+
| 0x7000FBD4
−
| 17
  −
| 0-29
   
|-
 
|-
−
| public_key3
+
| FUSE_SPARE_BIT_22
−
| 16
+
| 0x7000FBD8
−
| 17
  −
| 30-31
   
|-
 
|-
−
| public_key3
+
| FUSE_SPARE_BIT_23
−
| 18
+
| 0x7000FBDC
−
| 19
  −
| 0-29
   
|-
 
|-
−
| public_key4
+
| FUSE_SPARE_BIT_24
−
| 18
+
| 0x7000FBE0
−
| 19
  −
| 30-31
   
|-
 
|-
−
| public_key4
+
| FUSE_SPARE_BIT_25
−
| 20
+
| 0x7000FBE4
−
| 21
+
|-
−
| 0-29
+
| FUSE_SPARE_BIT_26
 +
| 0x7000FBE8
 
|-
 
|-
−
| public_key5
+
| FUSE_SPARE_BIT_27
−
| 20
+
| 0x7000FBEC
−
| 21
  −
| 30-31
   
|-
 
|-
−
| public_key5
+
| FUSE_SPARE_BIT_28
−
| 22
+
| 0x7000FBF0
−
| 23
  −
| 0-29
   
|-
 
|-
−
| public_key6
+
| FUSE_SPARE_BIT_29
−
| 22
+
| 0x7000FBF4
−
| 23
  −
| 30-31
   
|-
 
|-
−
| public_key6
+
| FUSE_SPARE_BIT_30
−
| 24
+
| 0x7000FBF8
−
| 25
  −
| 0-29
   
|-
 
|-
−
| public_key7
+
| FUSE_SPARE_BIT_31
−
| 24
+
| 0x7000FBFC
−
| 25
+
|}
−
| 30-31
+
 
−
|-
+
==== FUSE_SKU_INFO ====
−
| public_key7
+
Stores the SKU ID (must be 0x83).
−
| 26
+
 
−
| 27
+
==== FUSE_OPT_FT_REV ====
−
| 0-29
+
Stores the FT (Final Test) revision.
−
|-
+
 
−
| private_key0
+
Original launch units have this value set to 0xA0 (revision 5.0). The first batch of patched units have this value set to 0xC0 (revision 6.0). The second batch of patched units have this value set to 0xE0 (revision 7.0)
−
| 34
+
 
−
| 35
+
==== FUSE_SOC_SPEEDO_1_CALIB ====
−
| 12-31
+
Stores the bootrom patch version.
 +
 
 +
==== FUSE_FA ====
 +
Stores failure analysis mode.
 +
 
 +
==== FUSE_PUBLIC_KEY ====
 +
Stores the SHA256 hash of the 2048-bit RSA key expected at BCT+0x210.
 +
 
 +
==== FUSE_OPT_CP_REV ====
 +
Stores the CP (Chip Probing) revision.
 +
 
 +
Original launch units have this value set to 0xA0 (revision 5.0). Patched units have this value set to 0x103 (revision 8.3).
 +
 
 +
==== FUSE_PRIVATE_KEY ====
 +
Stores the 160-bit private key (128 bit SBK + 32-bit device key).
 +
 
 +
Reads to these registers after the SBK is locked out produce all-FF output.
 +
 
 +
==== FUSE_RESERVED_SW ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| private_key0
+
| 0-2
−
| 36
+
| Boot device
−
| 37
  −
| 0-11
   
|-
 
|-
−
| private_key1
+
| 3
−
| 36
+
| Skip device selection straps (0 = don't skip; 1 = skip)
−
| 37
  −
| 12-31
   
|-
 
|-
−
| private_key1
+
| 4
−
| 38
+
| ENABLE_CHARGER_DETECT
−
| 39
  −
| 0-11
   
|-
 
|-
−
| private_key2
+
| 5
−
| 38
+
| ENABLE_WATCHDOG
−
| 39
  −
| 12-31
   
|-
 
|-
−
| private_key2
+
| 6
−
| 40
+
| Forced RCM two button mode (0 = Only VOLUME_UP; 1 = VOLUME_UP + HOME)
−
| 41
  −
| 0-11
   
|-
 
|-
−
| private_key3
+
| 7
−
| 40
+
| RCM USB controller mode (0 = USB 2.0; 1 = XUSB)
−
| 41
+
|}
−
| 12-31
+
 
 +
Stores software reserved configuration values.
 +
 
 +
Original launch units have the RCM USB controller mode set to USB 2.0, while the first batch of patched units have the RCM USB controller mode set to XUSB.
 +
 
 +
==== FUSE_RESERVED_ODM0 ====
 +
Stores an hardware ID.
 +
 
 +
==== FUSE_RESERVED_ODM1 ====
 +
Stores an hardware ID.
 +
 
 +
==== FUSE_RESERVED_ODM2 ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| private_key3
+
| 0-4
−
| 42
+
| [5.0.0+] Used as key generation (patched units only)
−
| 43
+
|}
−
| 0-11
+
 
 +
Stores an hardware ID in original launch units, but in patched units it stores a single value (key generation).
 +
 
 +
==== FUSE_RESERVED_ODM3 ====
 +
Stores an hardware ID in original launch units, but is empty in patched units.
 +
 
 +
==== FUSE_RESERVED_ODM4 ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| private_key4
+
| 0-1
−
| 42
+
| Unit type (0x00 = Retail, 0x03 = Debug)
−
| 43
+
|-
−
| 12-31
+
| 2
 +
| Production flag (0x00 = Prototype, 0x01 = Production)
 
|-
 
|-
−
| private_key4
+
| [1.0.0-3.0.2] 3-5
−
| 44
+
[4.0.0+] 3-7
−
| 45
+
| DRAM ID
−
| 0-11
   
|-
 
|-
−
| boot_device_info
+
| 8
−
| 44
+
| Development flag (0x00 = Retail, 0x01 = Development)
−
| 45
  −
| 12-27
   
|-
 
|-
−
| reserved_sw
+
| 9
−
| 44
+
| Unit type flag (0x00 = Debug, 0x01 = Retail)
−
| 45
  −
| 28-31
   
|-
 
|-
−
| reserved_sw
+
| 10
−
| 46
+
| [3.0.0+] Kiosk flag (0x00 = Retail, 0x01 = Kiosk/Quest)
−
| 47
  −
| 0-3
   
|-
 
|-
−
| reserved_odm0
+
| 11
−
| 46
+
| [5.0.0+] Patch flag (0x00 = Unpatched, 0x01 = Patched)
−
| 47
  −
| 5-31
   
|-
 
|-
−
| reserved_odm0
+
| 16-19
−
| 48
+
| [4.0.0+] New hardware type (0x00 = Icosa, 0x01 = Iowa, 0x02 = Hoag)
−
| 49
+
|}
−
| 0-4
+
 
 +
Stores some device configuration parameters.
 +
 
 +
==== FUSE_RESERVED_ODM5 ====
 +
Empty and unused.
 +
 
 +
==== FUSE_RESERVED_ODM6 ====
 +
Returns the value of the [[#reserved_odm6|reserved_odm6]] anti-downgrade fuse.
 +
 
 +
==== FUSE_RESERVED_ODM7 ====
 +
Returns the value of the [[#reserved_odm7|reserved_odm7]] anti-downgrade fuse.
 +
 
 +
==== FUSE_OPT_SEC_DEBUG_EN ====
 +
Controls the [[TSEC#TSEC_SCP_CTL_STAT|Falcon SCP]] debug mode.
 +
 
 +
==== FUSE_OPT_PRIV_SEC_EN ====
 +
Controls the [[TSEC#FALCON_SCTL|Falcon Light Secure]] feature.
 +
 
 +
==== FUSE_PKC_DISABLE ====
 +
Returns if public key crypto is used or not.
 +
 
 +
==== FUSE_ECO_RESERVE_0 ====
 +
Returns the chip unique AID.
 +
 
 +
==== FUSE_SPARE_BIT_2 ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| reserved_odm1
+
| 0
−
| 48
+
| Speedo fusing revision
−
| 49
+
|}
−
| 5-31
+
 
 +
==== FUSE_SPARE_BIT_3 ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| reserved_odm1
+
| 0
−
| 50
+
| Speedo fusing revision
−
| 51
+
|}
−
| 0-4
+
 
 +
==== FUSE_SPARE_BIT_4 ====
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| reserved_odm2
+
| 0
−
| 50
+
| Speedo fusing revision
−
| 51
+
|}
−
| 5-31
+
 
−
|-
+
==== FUSE_SPARE_BIT_5 ====
−
| reserved_odm2
+
Must be non-zero on retail units, otherwise the first bootloader panics.
−
| 52
+
On prototype units it can be zero, which tells the bootloader to choose from two pre-production master key seeds. If set to non-zero on a prototype unit, it tells the bootloader to choose from two master key seeds (with the second one being the same as the retail master key seed).
−
| 53
+
 
−
| 0-4
+
[4.0.0+] This value is no longer used during boot.
 +
 
 +
== Bitmap ==
 +
The actual hardware fuses are stored in a bitmap and may be programmed through the fuse driver after enabling fuse programming.
 +
 
 +
Fuse numbers are relative to the start of the fuse bitmap where each element is a 4 byte word and has a redundant alias. A single fuse write operation must always write the same value to '''fuse_bitmap + ((fuse_number + 0) << 2)''' (PRIMARY_ALIAS) and '''fuse_bitmap + ((fuse_number + 1) << 2)''' (REDUNDANT_ALIAS). However, spare bits and all fuses afterwards in the fuse bitmap, no longer have a redundant alias.
 +
 
 +
Below is a list of common fuses used by Tegra devices (and applicable to the Switch).
 +
 
 +
{| class="wikitable" border="1"
 +
!  Name
 +
!  Number
 +
!  Redundant number
 +
!  Bits
 
|-
 
|-
−
| reserved_odm3
+
| enable_fuse_program
−
| 52
+
| 0
−
| 53
+
| 1
−
| 5-31
+
| 0
 
|-
 
|-
−
| reserved_odm3
+
| disable_fuse_program
−
| 54
+
| 0
−
| 55
+
| 1
−
| 0-4
+
| 1
 
|-
 
|-
−
| reserved_odm4
+
| bypass_fuses
−
| 54
+
| 0
−
| 55
+
| 1
−
| 5-31
+
| 2
 
|-
 
|-
−
| reserved_odm4
+
| jtag_direct_access_disable
−
| 56
+
| 0
−
| 57
+
| 1
−
| 0-4
+
| 3
 
|-
 
|-
−
| reserved_odm5
+
| production_mode
−
| 56
+
| 0
−
| 57
+
| 1
−
| 5-31
+
| 4
 
|-
 
|-
−
| reserved_odm5
+
| jtag_secureid_valid
−
| 58
+
| 0
−
| 59
+
| 1
−
| 0-4
+
| 5
 
|-
 
|-
−
| [[#reserved_odm6|reserved_odm6]]
+
| odm_lock
−
| 58
+
| 0
−
| 59
+
| 1
−
| 5-31
+
| 6-9
 
|-
 
|-
−
| [[#reserved_odm6|reserved_odm6]]
+
| fa_mode
−
| 60
+
| 0
−
| 61
+
| 1
−
| 0-4
+
| 10
 
|-
 
|-
−
| [[#reserved_odm7|reserved_odm7]]
+
| security_mode
−
| 60
+
| 0
−
| 61
+
| 1
−
| 5-31
+
| 11
 
|-
 
|-
−
| [[#reserved_odm7|reserved_odm7]]
+
| arm_debug_dis
−
| 62
+
| 0
−
| 63
+
| 1
−
| 0-4
+
| 12
 
|-
 
|-
−
| kfuse_privkey_ctrl
+
| obs_dis
−
| 64
+
| 0
−
| 65
+
| 1
−
| 13-14
+
| 13
 
|-
 
|-
−
| package_info
+
| public_key0
−
| 64
+
| 10
−
| 65
+
| 11
−
| 15-18
+
| 30-31
 
|-
 
|-
−
| opt_vendor_code
+
| public_key0
−
| 64
+
| 12
−
| 65
+
| 13
−
| 19-22
+
| 0-29
 
|-
 
|-
−
| opt_fab_code
+
| public_key1
−
| 64
+
| 12
−
| 65
+
| 13
−
| 23-28
+
| 30-31
 
|-
 
|-
−
| opt_lot_code_0
+
| public_key1
−
| 64
+
| 14
−
| 65
+
| 15
−
| 29-31
+
| 0-29
 
|-
 
|-
−
| opt_lot_code_0
+
| public_key2
−
| 66
+
| 14
−
| 67
+
| 15
−
| 0-28
+
| 30-31
 
|-
 
|-
−
| opt_lot_code_1
+
| public_key2
−
| 66
+
| 16
−
| 67
+
| 17
−
| 29-31
+
| 0-29
 
|-
 
|-
−
| opt_lot_code_1
+
| public_key3
−
| 68
+
| 16
−
| 69
+
| 17
−
| 0-24
+
| 30-31
 
|-
 
|-
−
| opt_wafer_id
+
| public_key3
−
| 68
+
| 18
−
| 69
+
| 19
−
| 25-30
+
| 0-29
 
|-
 
|-
−
| opt_x_coordinate
+
| public_key4
−
| 68
+
| 18
−
| 69
+
| 19
−
| 31
+
| 30-31
 
|-
 
|-
−
| opt_x_coordinate
+
| public_key4
−
| 70
+
| 20
−
| 71
+
| 21
−
| 0-7
+
| 0-29
 
|-
 
|-
−
| opt_y_coordinate
+
| public_key5
−
| 70
+
| 20
−
| 71
+
| 21
−
| 8-16
+
| 30-31
 
|-
 
|-
−
| opt_sec_debug_en
+
| public_key5
−
| 70
+
| 22
−
| 71
+
| 23
−
| 17
+
| 0-29
 
|-
 
|-
−
| opt_ops_reserved
+
| public_key6
−
| 70
+
| 22
−
| 71
+
| 23
−
| 18-23
+
| 30-31
 
|-
 
|-
−
| sata_calib
+
| public_key6
−
| 70
+
| 24
−
| 71
+
| 25
−
| 24-25
+
| 0-29
 
|-
 
|-
−
| opt_priv_sec_en
+
| public_key7
−
| 90
+
| 24
−
| 91
+
| 25
−
| 8
+
| 30-31
 
|-
 
|-
−
| pkc_disable
+
| public_key7
−
| 90
+
| 26
−
| 91
+
| 27
−
| 9
+
| 0-29
−
|-
+
|-
−
| fuse2tsec_debug_disable
+
| private_key0
−
| 90
+
| 34
−
| 91
+
| 35
−
| 10
+
| 12-31
−
|-
+
|-
−
| secure_provision_index
+
| private_key0
−
| 90
+
| 36
−
| 91
+
| 37
−
| 24-27
+
| 0-11
−
|-
+
|-
−
| secure_provision_info
+
| private_key1
−
| 90
+
| 36
−
| 91
+
| 37
−
| 28-29
+
| 12-31
−
|-
+
|-
−
| aid
+
| private_key1
−
| 103
+
| 38
−
| None
+
| 39
−
| 0-31
+
| 0-11
−
|-
+
|-
−
| [[#irom_patch|irom_patch]]
+
| private_key2
−
| 114
+
| 38
−
| None
+
| 39
−
| Variable
+
| 12-31
−
|}
+
|-
−
 
+
| private_key2
−
=== reserved_odm6 ===
+
| 40
−
Used for anti-downgrade control.
+
| 41
−
 
+
| 0-11
−
=== reserved_odm7 ===
+
|-
−
Used for anti-downgrade control.
+
| private_key3
−
 
+
| 40
 +
| 41
 +
| 12-31
 +
|-
 +
| private_key3
 +
| 42
 +
| 43
 +
| 0-11
 +
|-
 +
| private_key4
 +
| 42
 +
| 43
 +
| 12-31
 +
|-
 +
| private_key4
 +
| 44
 +
| 45
 +
| 0-11
 +
|-
 +
| boot_device_info
 +
| 44
 +
| 45
 +
| 12-27
 +
|-
 +
| reserved_sw
 +
| 44
 +
| 45
 +
| 28-31
 +
|-
 +
| reserved_sw
 +
| 46
 +
| 47
 +
| 0-3
 +
|-
 +
| reserved_odm0
 +
| 46
 +
| 47
 +
| 5-31
 +
|-
 +
| reserved_odm0
 +
| 48
 +
| 49
 +
| 0-4
 +
|-
 +
| reserved_odm1
 +
| 48
 +
| 49
 +
| 5-31
 +
|-
 +
| reserved_odm1
 +
| 50
 +
| 51
 +
| 0-4
 +
|-
 +
| reserved_odm2
 +
| 50
 +
| 51
 +
| 5-31
 +
|-
 +
| reserved_odm2
 +
| 52
 +
| 53
 +
| 0-4
 +
|-
 +
| reserved_odm3
 +
| 52
 +
| 53
 +
| 5-31
 +
|-
 +
| reserved_odm3
 +
| 54
 +
| 55
 +
| 0-4
 +
|-
 +
| reserved_odm4
 +
| 54
 +
| 55
 +
| 5-31
 +
|-
 +
| reserved_odm4
 +
| 56
 +
| 57
 +
| 0-4
 +
|-
 +
| reserved_odm5
 +
| 56
 +
| 57
 +
| 5-31
 +
|-
 +
| reserved_odm5
 +
| 58
 +
| 59
 +
| 0-4
 +
|-
 +
| [[#reserved_odm6|reserved_odm6]]
 +
| 58
 +
| 59
 +
| 5-31
 +
|-
 +
| [[#reserved_odm6|reserved_odm6]]
 +
| 60
 +
| 61
 +
| 0-4
 +
|-
 +
| [[#reserved_odm7|reserved_odm7]]
 +
| 60
 +
| 61
 +
| 5-31
 +
|-
 +
| [[#reserved_odm7|reserved_odm7]]
 +
| 62
 +
| 63
 +
| 0-4
 +
|-
 +
| kfuse_privkey_ctrl
 +
| 64
 +
| 65
 +
| 13-14
 +
|-
 +
| package_info
 +
| 64
 +
| 65
 +
| 15-18
 +
|-
 +
| opt_vendor_code
 +
| 64
 +
| 65
 +
| 19-22
 +
|-
 +
| opt_fab_code
 +
| 64
 +
| 65
 +
| 23-28
 +
|-
 +
| opt_lot_code_0
 +
| 64
 +
| 65
 +
| 29-31
 +
|-
 +
| opt_lot_code_0
 +
| 66
 +
| 67
 +
| 0-28
 +
|-
 +
| opt_lot_code_1
 +
| 66
 +
| 67
 +
| 29-31
 +
|-
 +
| opt_lot_code_1
 +
| 68
 +
| 69
 +
| 0-24
 +
|-
 +
| opt_wafer_id
 +
| 68
 +
| 69
 +
| 25-30
 +
|-
 +
| opt_x_coordinate
 +
| 68
 +
| 69
 +
| 31
 +
|-
 +
| opt_x_coordinate
 +
| 70
 +
| 71
 +
| 0-7
 +
|-
 +
| opt_y_coordinate
 +
| 70
 +
| 71
 +
| 8-16
 +
|-
 +
| opt_sec_debug_en
 +
| 70
 +
| 71
 +
| 17
 +
|-
 +
| opt_ops_reserved
 +
| 70
 +
| 71
 +
| 18-23
 +
|-
 +
| sata_calib
 +
| 70
 +
| 71
 +
| 24-25
 +
|-
 +
| opt_priv_sec_en
 +
| 90
 +
| 91
 +
| 8
 +
|-
 +
| pkc_disable
 +
| 90
 +
| 91
 +
| 9
 +
|-
 +
| fuse2tsec_debug_disable
 +
| 90
 +
| 91
 +
| 10
 +
|-
 +
| secure_provision_index
 +
| 90
 +
| 91
 +
| 24-27
 +
|-
 +
| secure_provision_info
 +
| 90
 +
| 91
 +
| 28-29
 +
|-
 +
| spare_bit_0
 +
| 100
 +
| None
 +
| 16
 +
|-
 +
| spare_bit_1
 +
| 100
 +
| None
 +
| 17
 +
|-
 +
| spare_bit_2
 +
| 100
 +
| None
 +
| 18
 +
|-
 +
| spare_bit_3
 +
| 100
 +
| None
 +
| 19
 +
|-
 +
| spare_bit_4
 +
| 100
 +
| None
 +
| 20
 +
|-
 +
| spare_bit_5
 +
| 100
 +
| None
 +
| 21
 +
|-
 +
| spare_bit_6
 +
| 100
 +
| None
 +
| 22
 +
|-
 +
| spare_bit_7
 +
| 100
 +
| None
 +
| 23
 +
|-
 +
| spare_bit_8
 +
| 100
 +
| None
 +
| 24
 +
|-
 +
| spare_bit_9
 +
| 100
 +
| None
 +
| 25
 +
|-
 +
| spare_bit_10
 +
| 100
 +
| None
 +
| 26
 +
|-
 +
| spare_bit_11
 +
| 100
 +
| None
 +
| 27
 +
|-
 +
| spare_bit_12
 +
| 100
 +
| None
 +
| 28
 +
|-
 +
| spare_bit_13
 +
| 100
 +
| None
 +
| 29
 +
|-
 +
| spare_bit_14
 +
| 100
 +
| None
 +
| 30
 +
|-
 +
| spare_bit_15
 +
| 100
 +
| None
 +
| 31
 +
|-
 +
| spare_bit_16
 +
| 101
 +
| None
 +
| 16
 +
|-
 +
| spare_bit_17
 +
| 101
 +
| None
 +
| 17
 +
|-
 +
| spare_bit_18
 +
| 101
 +
| None
 +
| 18
 +
|-
 +
| spare_bit_19
 +
| 101
 +
| None
 +
| 19
 +
|-
 +
| spare_bit_20
 +
| 101
 +
| None
 +
| 20
 +
|-
 +
| spare_bit_21
 +
| 101
 +
| None
 +
| 21
 +
|-
 +
| spare_bit_22
 +
| 101
 +
| None
 +
| 22
 +
|-
 +
| spare_bit_23
 +
| 101
 +
| None
 +
| 23
 +
|-
 +
| spare_bit_24
 +
| 101
 +
| None
 +
| 24
 +
|-
 +
| spare_bit_25
 +
| 101
 +
| None
 +
| 25
 +
|-
 +
| spare_bit_26
 +
| 101
 +
| None
 +
| 26
 +
|-
 +
| spare_bit_27
 +
| 101
 +
| None
 +
| 27
 +
|-
 +
| spare_bit_28
 +
| 101
 +
| None
 +
| 28
 +
|-
 +
| spare_bit_29
 +
| 101
 +
| None
 +
| 29
 +
|-
 +
| spare_bit_30
 +
| 101
 +
| None
 +
| 30
 +
|-
 +
| spare_bit_31
 +
| 101
 +
| None
 +
| 31
 +
|-
 +
| aid
 +
| 103
 +
| None
 +
| 2-31
 +
|-
 +
| aid
 +
| 104
 +
| None
 +
| 0-1
 +
|-
 +
| ramrepair_record0
 +
| 106
 +
| None
 +
| 0-31
 +
|-
 +
| ramrepair_record1
 +
| 107
 +
| None
 +
| 0-31
 +
|-
 +
| ramrepair_record2
 +
| 108
 +
| None
 +
| 0-31
 +
|-
 +
| ramrepair_record3
 +
| 109
 +
| None
 +
| 0-31
 +
|-
 +
| ramrepair_record4
 +
| 110
 +
| None
 +
| 0-31
 +
|-
 +
| ramrepair_record5
 +
| 111
 +
| None
 +
| 0-31
 +
|-
 +
| ramrepair_record6
 +
| 112
 +
| None
 +
| 0-31
 +
|-
 +
| ramrepair_record7
 +
| 113
 +
| None
 +
| 0-31
 +
|-
 +
| [[#irom_patch|irom_patch]]
 +
| 114
 +
| None
 +
| Variable
 +
|}
 +
 
 +
=== reserved_odm6 ===
 +
Used for [[#Anti-downgrade|anti-downgrade]] control.
 +
 
 +
=== reserved_odm7 ===
 +
Used for [[#Anti-downgrade|anti-downgrade]] control.
 +
 
 
=== irom_patch ===
 
=== irom_patch ===
 
Tegra210 based hardware such as the Switch provides support for bootrom patches. The patch data is burned to the hardware fuse bitmap using a specific format (see [https://gist.github.com/shuffle2/f8728159da100e9df2606d43925de0af shuffle2's ipatch decoder]). The bootrom reads these fuses in order to initialize the IPATCH hardware, which allows overriding data returned for code and data fetches done by BPMP.
 
Tegra210 based hardware such as the Switch provides support for bootrom patches. The patch data is burned to the hardware fuse bitmap using a specific format (see [https://gist.github.com/shuffle2/f8728159da100e9df2606d43925de0af shuffle2's ipatch decoder]). The bootrom reads these fuses in order to initialize the IPATCH hardware, which allows overriding data returned for code and data fetches done by BPMP.
Line 1,735: Line 2,275:  
| 1
 
| 1
 
|-
 
|-
−
| 9.0.0
+
| 9.0.0-9.0.1
 
| 11
 
| 11
 +
| 1
 +
|-
 +
| 9.1.0
 +
| 12
 
| 1
 
| 1
 
|}
 
|}
Retrieved from "https://switchbrew.org/wiki/Special:MobileDiff/7988...8560"

Navigation menu