Line 1,264: |
Line 1,264: |
| | 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]] | | | 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]] |
| |- | | |- |
− | | 0x40184806 || || NVGPU_IOCTL_CHANNEL_WAIT | + | | 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]] |
| |- | | |- |
| | 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]] | | | 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]] |
Line 1,272: |
Line 1,272: |
| | 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]] | | | 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]] |
| |- | | |- |
− | | 0x4008480A || || NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX | + | | 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]] |
| |- | | |- |
| | 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]] | | | 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]] |
Line 1,308: |
Line 1,308: |
| | 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]] | | | 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]] |
| |- style="border-top: double" | | |- style="border-top: double" |
− | | 0x40084714 || 8 || NVGPU_IOCTL_CHANNEL_SET_USER_DATA | + | | 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]] |
| |- | | |- |
− | | 0x80084715 || 8 || NVGPU_IOCTL_CHANNEL_GET_USER_DATA | + | | 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]] |
| |} | | |} |
| | | |
Line 1,421: |
Line 1,421: |
| __in u32 num_entries; | | __in u32 num_entries; |
| __in u32 flags; | | __in u32 flags; |
| + | }; |
| + | |
| + | === NVGPU_IOCTL_CHANNEL_WAIT === |
| + | Waits on channel. Identical to Linux driver. |
| + | |
| + | struct { |
| + | __in u32 type; // wait type (0=notifier, 1=semaphore) |
| + | __in u32 timeout; // wait timeout value |
| + | __in u32 dmabuf_fd; // nvmap handle |
| + | __in u32 offset; // nvmap memory offset |
| + | __in u32 payload; // payload data (semaphore only) |
| + | __in u32 padding; // ignored |
| }; | | }; |
| | | |
Line 1,427: |
Line 1,439: |
| | | |
| struct { | | struct { |
− | __in u32 dmabuf_fd; // nvmap handle | + | __in u32 dmabuf_fd; // nvmap handle |
| }; | | }; |
| | | |
Line 1,459: |
Line 1,471: |
| __in u32 flags; // bit0: LOCKBOOST_ZERO | | __in u32 flags; // bit0: LOCKBOOST_ZERO |
| __out u64 obj_id; // (ignored) used for FREE_OBJ_CTX ioctl, which is not supported | | __out u64 obj_id; // (ignored) used for FREE_OBJ_CTX ioctl, which is not supported |
| + | }; |
| + | |
| + | === NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX === |
| + | Frees a graphics context object. Not supported. |
| + | |
| + | struct { |
| + | __in u64 obj_id; // ignored |
| }; | | }; |
| | | |
Line 1,567: |
Line 1,586: |
| struct { | | struct { |
| __in u32 timeslice; | | __in u32 timeslice; |
| + | }; |
| + | |
| + | === NVGPU_IOCTL_CHANNEL_SET_USER_DATA === |
| + | Sets user specific data. |
| + | |
| + | struct { |
| + | __in u64 data; |
| + | }; |
| + | |
| + | === NVGPU_IOCTL_CHANNEL_GET_USER_DATA === |
| + | Gets user specific data. |
| + | |
| + | struct { |
| + | __out u64 data; |
| }; | | }; |
| | | |