888
edits
Changes
→Secure Monitor: .
* CPU Suspend SMC code now explicitly initializes the state of I2C5 before communicating with the PMIC, instead of assuming that it is in a valid state.
* CPU Suspend SMC code now explicitly initializes the state of I2C5 before communicating with the PMIC, instead of assuming that it is in a valid state.
* Code for initializing MMIO inside package2ldr now writes random values to a number of PMC secure scratch registers, and validates that the written values are read back successfully before locking the scratch.
* Code for initializing MMIO inside package2ldr now writes random values to a number of PMC secure scratch registers, and validates that the written values are read back successfully before locking the scratch.
** TODO: Check back later for information on what these scratch do.
** This writes to secscratch 4-7 (used to store SRK), then locks them.
*** The SE will overwrite these values during context save despite the lock.
** This then writes to secscratch 112-115 and 24-25, used by TZ during context save to store a MAC and a key source, respectively.
*** These too will be overwritten during context save, as the scratch are not locked.
** secscratch 4-7 are then locked a second time.
====KernelLdr====
====KernelLdr====