2,939
edits
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| 0xC0344704 || Inout || 52 || NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE ||
| 0xC0344704 || Inout || 52 || NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE ||
|-
|-
| 0xC0B04705 || Inout || 176 || NVGPU_GPU_IOCTL_GET_CHARACTERISTICS ||
| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]] ||
|-
|-
| 0xC0184706 || Inout || 24 || NVGPU_GPU_IOCTL_GET_TPC_MASKS ||
| 0xC0184706 || Inout || 24 || NVGPU_GPU_IOCTL_GET_TPC_MASKS ||
| 0xC010471C || Inout || 16 || ||
| 0xC010471C || Inout || 16 || ||
|}
|}
=== NVGPU_GPU_IOCTL_GET_CHARACTERISTICS ===
Returns the GPU characteristics. Modified to return inline data instead of using a pointer.
struct __gpu_characteristics {
u32 __arch; // 0x120 (NVGPU_GPU_ARCH_GM200)
u32 __impl; // 0xB (NVGPU_GPU_IMPL_GM20B)
u32 __rev; // 0xA1 (Revision A1)
u32 __num_gpc; // 0x1
u64 __L2_cache_size; // 0x40000
u64 __on_board_video_memory_size; // 0x0 (not used)
u32 __num_tpc_per_gpc; // 0x2
u32 __bus_type; // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
u32 __big_page_size; // 0x20000
u32 __compression_page_size; // 0x20000
u32 __pde_coverage_bit_count; // 0x1B
u32 __available_big_page_sizes; // 0x30000
u32 __gpc_mask; // 0x1
u32 __sm_arch_sm_version; // 0x503 (Maxwell Generation 5.0.3?)
u32 __sm_arch_spa_version; // 0x503 (Maxwell Generation 5.0.3?)
u32 __sm_arch_warp_count; // 0x80
u32 __gpu_va_bit_count; // 0x28
u32 __reserved; // NULL
u64 __flags; // 0x55
u32 __twod_class; // 0x902D (FERMI_TWOD_A)
u32 __threed_class; // 0xB197 (MAXWELL_B)
u32 __compute_class; // 0xB1C0 (MAXWELL_COMPUTE_B)
u32 __gpfifo_class; // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
u32 __inline_to_memory_class; // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
u32 __dma_copy_class; // 0xB0B5 (MAXWELL_DMA_COPY_A)
u32 __max_fbps_count; // 0x1
u32 __fbp_en_mask; // 0x0 (disabled)
u32 __max_ltc_per_fbp; // 0x2
u32 __max_lts_per_ltc; // 0x1
u32 __max_tex_per_tpc; // 0x0 (not supported)
u32 __max_gpc_count; // 0x1
u32 __rop_l2_en_mask_0; // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
u32 __rop_l2_en_mask_1; // 0x0
u64 __chipname; // 0x6230326D67 ("gm20b")
u64 __gr_compbit_store_base_hw; // 0x0 (not supported)
};
struct {
u64 __gpu_characteristics_buf_size; // in/out (must not be NULL, but gets overwritten with 0xA0=max_size)
u64 __gpu_characteristics_buf_addr; // in (ignored, but must not be NULL)
struct __gpu_characteristics gc; // out
};
== Channels ==
== Channels ==
struct {
struct {
u32 __class_num; // in (0xB197=2d, 0xB1C0=compute, 0xA140=kepler, 0xB0B5=DMA, 0xB06F=channel_gpfifo)
u32 __class_num; // in (0x902D=2d, 0xB197=3d, 0xB1C0=compute, 0xA140=kepler, 0xB0B5=DMA, 0xB06F=channel_gpfifo)
u32 __flags; // in
u32 __flags; // in
u64 __obj_id; // out (ignored; used for FREE_OBJ_CTX ioctl, which is not supported)
u64 __obj_id; // out (ignored; used for FREE_OBJ_CTX ioctl, which is not supported)