Nintendo Switch Brew

Changes

14.0.0 (view source)

Revision as of 09:34, 22 March 2022

11,341 bytes added ,  09:34, 22 March 2022
→‎BootImagePackage: secmon/kernel
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=== BootImagePackage ===
 
=== BootImagePackage ===
 
All files in RomFs were updated.
 
All files in RomFs were updated.
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====Secure Monitor====
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* Compiler upgrade to latest llvm (now using same compiler revision as kernel).
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** Secure Monitor is now compiled with -fomit-frame-pointer.
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*** >:(
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* GenerateSeTestVectorImpl now uses a helper to mix each key into the vector.
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* ExceptionHandler is now linked in (@ .text + 0x3E04).
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** Previously, this was garbage collected/only present in debug secure monitors.
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** NOTE: This is unreachable, and stripped (as e.g. logging isn't emitted, likely because the macros are empty on release builds).
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====Kernel====
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* Kernel is now compiled with -O3 again instead of -Os
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** >:(
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* crt0 no longer supports booting in EL2.
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** Infinite Loop/Panic is performed instead.
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* Initialize0 changes:
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** KernelStack setup now uses same helper to determine aslr as other random aligned regions.
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** KernelTemp setup now uses same helper to determine aslr as other random aligned regions.
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* Slab changes:
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** When assigned extra resource, the slab heap is now 0x148000 larger instead of 0x68000 larger.
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** Correspondingly, instead of increasing the thread resource limit by 160, the thread resource limit is now increased by 736.
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*** This corresponds to changes in userland for pm management of resource limits.
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*** Old Intended Resource Limits:
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**** System (96 + 512) -> (256 + 512)
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**** Applet 96 -> 96
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**** Application 96 -> 96
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*** New Intended Resource Limits:
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**** System (96 + 512) -> 1024
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**** Applet 96 -> 256
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**** Application 96 -> 256
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* SetupPoolPartitionMemoryRegions now panics if the end of the pool partition region is not coincidence with the end of dram.
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* KThreadContext was completely revised.
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** Most of KThreadContext is now stored inline in kernel stack.
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*** Kernel stack layout is now u8 stack[0xDB0]; KThreadContext thread_context; KThreadStackParameters stack_parameters;
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** KThreadContext now only stores the 8 callee-save FPU registers.
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*** The remaining 24 caller-save FPU registers are stored inside KThread, where KThreadContext used to be.
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*** NOTE that 32-bit fpu has 4 callee-save FPU registers and 12 caller-save registers, which use the start of the relevant 64-bit storages as usual.
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** KThreadStackParameters was revised to facilitate this.
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*** The pointer to KThreadContext previously stored in stack parameters now points to the external FPU register array.
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*** The members at end of params are now: u16 disable_count; u8 current_svc_id; u8 unused_2c; u8 exception_flags; u8 is_pinned; u8 unused_2f;
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**** The "exception_flags" field is a new set of bitflags (encoding old state was were previously separate bools + new state).
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***** Bit 0x1  = is_calling_svc
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***** Bit 0x2  = is_in_exception_handler
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***** Bit 0x4  = is_fpu_state_restore_needed
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***** Bit 0x8  = is_64_bit_fpu
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***** Bit 0x10 = has_exception_svc_permissions
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***** Bit 0x20 = is_in_cache_operation
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***** Bit 0x40 = is_in_tlb_operation
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** Exception exits now check is_fpu_state_restore_needed, and restore FPU registers only if needed (and clear is_fpu_state_restore_needed on restore).
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*** is_fpu_state_restore_needed is set to true *only* on thread switch with FPU enabled.
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**** Caller-save FPU registers are saved *only* if a thread is in an SVC and does not have exception svc permissions.
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**** All other thread switches save only the 8 (or 4) callee-save FPU registers.
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**** All thread switches now guarantee as post-condition that the fpu is disabled leaving the switch (it will be re-enabled on exception exit if needed).
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*** On SVC exception return, all caller-save FPU registers are set to zero unless the thread has exception svc permissions.
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** KThread::CloneFpuStatus now uses KScopedDisableInterrupt
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* Various hw maintenance changes:
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** KernelLdr no longer does cache maintenance by set/way when setting up initial identity mapping, no longer invalidates instruction cache/tlb, no longer does dsb after setting sctlr_el1.
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** FlushEntireDataCacheLocal/Shared in init now perform dsb sy, FlushEntireDataCacheAndInvalidateTlbForInit no longer does after calling them.
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** dsb sy/isb is now performed after setting sctlr_el1, when disabling mmu/icache.
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** KInitialPageTable::Map no longer does dsb ish after all attribute writes.
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*** Instead does it before writing table entries, and at the end of the function.
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** KInitialPageTable::PhysicallyRandomize no longer does StoreEntireCacheForInit.
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*** Now does dc cvac on randomized virtual address range, dsb ish, ic iallu, dsb ish, isb. (see weaker-barriers section of diff)
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** KInitialPageTable::SwapBlocks now does dsb ish after memcpy to swap blocks.
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** KInitialPageTable::Reprotect no longer does dsb ish before performing reprotection.
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** KInitialProcessReader::Load no longer calls cpu::FlushEntireDataCache/cpu::InvalidateInstructionCache.
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** Set/way cache operations now perform dsb sy before configuring csselr.
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*** This affects InvalidateDataCacheForResumeEntry, FlushEntireDataCache, KCacheHelperInterruptHandler, and the initial cache maintenance when disabling the mmu.
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** FlushEntireDataCache now does dsb sy after doing full set/way cache flush, instead of after each set/way op.
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*** NOTE: This is still only a local flush without coherence guarantees, set/way aren't supposed to be used after multiple cores are online.
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** KSystemControl::CpuSleepHandler no longer embeds unreachable cache maintenance assembly after CpuSuspend.
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** Kernel now performs different hw maintenance if a thread is in a hw maintenance operation when interrupted:
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*** If a thread is interrupted while performing cache maintenance in EL1 (tracked via new exception flags bit 0x20), KInterruptManager::OnHandleInterrupt performs dsb sy.
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**** Set and cleared for scope of cpu::InvalidateDataCache instead of disabling core migration.
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**** Set and cleared for scope of cpu::StoreDataCache instead of disabling core migration.
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**** Set and cleared for scope of cpu::FlushDataCache instead of disabling core migration.
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*** If a thread is interrupted while performing tlb maintenance in EL1 (tracked via new exception flags bit 0x40), KInterruptManager::OnHandleInterrupt performs dsb ish.
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**** Set and cleared for scope of KPageTable::NoteUpdated
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*** If a thread is interrupted while performing cache maintenance in EL0 (tracked via new bool @ TLS + 0x104), KInterruptManager::OnHandleInterrupt performs dsb sy.
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**** This is equivalent to the EL1 cache maintenance tracking above, providing an opt-in way for userland to ensure its cache maintenance is coherent even when interrupted.
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**** Note that official userland code now sets this bit before performing cache maintenance.
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** Memory barriers were revised in many places -- barriers were weakened in many places, and some functions which previously lacked barriers had them added, including:
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*** cpu::InvalidateEntireInstructionCache: dsb sy -> dsb ish
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*** cpu::EnsureInstructionConsistency: dsb sy; isb; -> dsb ish; isb;
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**** NOTE: Functions written in assembly still use the old pattern for ensuring instruction consistency.
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*** KCacheInterruptHandler::RequestOperation: dsb sy -> dsb ish
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*** KScheduler::EnableScheduling: dsb sy -> dsb ish
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*** KScheduler::SwitchThread no longer does dsb sy before setting ttbr0/contextidr_el1.
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*** KPageTable::NoteUpdated: dsb sy; if (m_kernel) { ... dsb sy; } else { ... dsb sy; isb; } -- dsb ishst; if (m_kernel) { ... dsb ish; } else { ... dsb ish; isb; }
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**** KPageTable::NoteSingleKernelPageUpdated now similarly does dsb ishst for outer and dsb ish for inner barriers.
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*** KPageTable::ClearPageTable: now does dsb ish after clearing page to zero via dc zva
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*** KPageTable::MapContiguous: now does dsb ishst after merging pages.
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*** KPageTable::MapPageGroup: now does dsb ishst after merging pages.
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*** KPageTable::PteDataSynchronizationBarrier: now dmb ishst instead of dsb ish (probably KPageTable::PteDataMemoryBarrier, now?)
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*** KPageTable::MapL2Blocks/MapL3Blocks: pattern for setting entry for new table went from Barrier(); WriteEntry(); Barrier(); -> Barrier(); WriteEntry();
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**** This was PteDataSynchronizationBarrier(), and correspondingly asm is dsb ish; str; dsb ish; -> dmb ishst; str;
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*** KSupervisorPageTable::SetTtbr0 no longer does dsb sy before setting ttbr0/contextidr_el1.
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** UserspaceAccess::InvalidateInstructionCache was removed (previously unused).
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* Various changes to KInterruptName/interrupt management:
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** Enum values for IPIs were revised:
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*** KInterruptName_ThreadTerminate    4 -> 0
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*** KInterruptName_CacheOperation    5 -> 1
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*** KInterruptName_Scheduler          6 -> 2
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** New KInterruptName (KInterruptName_CoreBarrier) = 3
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*** Interrupt handler for this is registered with KInterruptControllerPriority_Scheduler after ThreadTerminate handler is registered.
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** Interrupt handler for the user cycle counter interrupt is no longer registered.
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*** This is presumably now under the same ifdef that enables svc::InfoType_PerformanceCounter.
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* KCapability now has a new member "physical_core_mask", which tracks what physical cores are allowable.
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** KThread::FinishTermination now calls a new function (cpu::ForceSynchronizeAllCores) after waiting for the thread to not be current on any scheduler.
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*** This function sends an IPI (KInterruptName_CoreBarrier) to all cores, and waits for all cores to acknowledge the interrupt.
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* Changes to KMemoryManager allocation:
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** KPageHeap now has an additional KPageHeapBitmapRng @ 0x328 to facilitate additional allocation randomization.
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** KMemoryManager::AllocateAndOpenContinuous now uses a new KPageHeap method "AllocateRandomBlock"
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*** KPhysicalAddress KPageHeap::AllocateRandomBlock(s32 index, size_t num_pages, size_t align_pages);
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*** This method allocates `num_pages` pages (aligned to at least `align_pages`) at random.
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**** First, the kernel chooses a random block index to allocate from.
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***** This is done by increasing the block index until there are at least 4 possible random choices for the desired alignment, then selecting the block that corresponds to a random pick from those choices.
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**** Next, the kernel allocates a random block from within that index.
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**** Finally, the kernel selects a random (align_pages)-aligned offset within that block, frees the memory before/after the allocated chunk, and returns the memory.
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** Allocation of KPageGroups still uses a `random` argument, however:
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*** KPageHeap::PopBlock no longer takes a random argument.
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*** KPageHeap::AllocateBlock now calls new new KPageHeap method "AllocateRandomBlock".
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**** KPageHeap::AllocateRandomBlock(s32 index, size_t num_pages);
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**** This is effectively the same logic as above, but with align_pages == # of pages for the argument block index.
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* CreateProcess now calls a new function to validate the user-capabilities before creating the KProcess.
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** This checks that the capabilities are user-readable and that the map region capabilities correspond to actually-present regions.
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** This corresponds to changes in Loader allowing for map region capabilities (previously, these were only allowed via KIP, and Loader always rejected them).
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* New InfoType 0x1A ("InfoType_IsSvcPermitted").
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** Returns whether the current process can access a given SVC.
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** Nintendo returns InvalidCombination when checking SVCs other than SynchronizePreemptionState.
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*** Official userland code now aborts if the process does not have permission to use SynchronizePreemptionState before incrementing ThreadLocalRegion->disable_count for the first time.
    
==See Also==
 
==See Also==
Retrieved from "https://switchbrew.org/wiki/Special:MobileDiff/11554"