2,939
edits
Changes
→/dev/nvhost-as-gpu
| 0xC0084105 || Inout || 8 || [[#NVGPU_AS_IOCTL_UNMAP_BUFFER]]
| 0xC0084105 || Inout || 8 || [[#NVGPU_AS_IOCTL_UNMAP_BUFFER]]
|-
|-
| 0xC0284106 || Inout || 40 || [[#NVGPU_AS_IOCTL_MODIFY]]
| 0xC0284106 || Inout || 40 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX]]
|-
|-
| 0x40104107 || In || 16 || [[#NVGPU_AS_IOCTL_ALLOC_AS]]
| 0x40104107 || In || 16 || [[#NVGPU_AS_IOCTL_ALLOC_AS]]
| 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX]]
| 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX]]
|-
|-
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX]]
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MODIFY]]
|-
|-
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]
struct {
struct {
__in u32 fd;
__in u32 channel_fd;
};
};
__in u32 page_size;
__in u32 page_size;
__in u32 flags;
__in u32 flags;
u32 pad;
u32 padding;
union {
union {
__out u64 offset;
__out u64 offset;
struct {
struct {
__in u32 flags; // bit0: fixed_offset, bit2: cacheable
__in u32 flags; // bit0: fixed_offset, bit2: cacheable
u32 pad;
u32 reserved;
__in u32 nvmap_handle;
__in u32 dmabuf_fd; // nvmap handle
__inout u32 page_size; // 0 means don't care
__inout u32 page_size; // 0 means don't care
union {
union {
};
};
=== NVGPU_AS_IOCTL_MODIFY ===
=== NVGPU_AS_IOCTL_MAP_BUFFER_EX ===
Maps a memory region in the device address space with extra params.
Unaligned size will cause a [[#Panic]].
Unaligned size will cause a [[#Panic]].
__in u32 flags; // bit0: fixed_offset, bit2: cacheable
__in u32 flags; // bit0: fixed_offset, bit2: cacheable
__in u32 kind; // -1 is default
__in u32 kind; // -1 is default
__in u32 nvmap_handle;
__in u32 dmabuf_fd; // nvmap handle
__inout u32 page_size; // 0 means don't care
__inout u32 page_size; // 0 means don't care
__in u64 buffer_offset;
__in u64 buffer_offset;
__in u32 big_page_size; // depends on GPU's available_big_page_sizes; 0=default
__in u32 big_page_size; // depends on GPU's available_big_page_sizes; 0=default
__in s32 as_fd; // ignored; passes 0
__in s32 as_fd; // ignored; passes 0
__in u32 flags; // ignored; passes 0
__in u64 reserved; // ignored; passes 0
};
};
u64 offset;
u64 offset;
u32 page_size;
u32 page_size;
u32 pad;
u32 reserved;
u64 pages;
u64 pages;
};
};
struct {
struct {
u64 not_used; // (contained output user ptr on linux, ignored)
u64 buf_addr; // (contained output user ptr on linux, ignored)
__inout u32 bufsize; // forced to 2*sizeof(struct va_region)
__inout u32 buf_size; // forced to 2*sizeof(struct va_region)
u32 pad;
u32 reserved;
__out struct va_region regions[2];
__out struct va_region regions[2];
};
};
};
};
=== NVGPU_AS_IOCTL_MAP_BUFFER_EX ===
=== NVGPU_AS_IOCTL_MODIFY ===
Modifies a memory region in the device address space.
struct {
struct {
__in u32 flags; // bit0: fixed_offset, bit2: cacheable
__in u32 flags; // bit0: fixed_offset, bit2: cacheable
__in u32 kind; // -1 is default
__in u32 kind; // -1 is default
__in u32 nvmap_handle;
__in u32 dmabuf_fd; // nvmap handle
__inout u32 page_size; // 0 means don't care
__inout u32 page_size; // 0 means don't care
__in u64 buffer_offset;
__in u64 buffer_offset;
__in u64 unk0;
__in u64 unk0;
__in u32 unk1;
__in u32 unk1;
u32 pad;
u32 reserved;
};
};
Nintendo's custom implementation of address space remapping.
Nintendo's custom implementation of address space remapping.
struct remap_entry {
struct remap_op {
__in u16 flags; // 0 or 4
__in u16 flags; // 0 or 4
__in u16 kind;
__in u16 kind;
__in u32 nvmap_handle;
__in u32 mem_handle;
__in u32 map_offset;
__in u32 mem_offset_in_pages;
__in u32 gpu_offset; // (alloc_space_offset >> 0x10)
__in u32 virt_offset_in_pages; // (alloc_space_offset >> 0x10)
__in u32 pages; // alloc_space_pages
__in u32 num_pages; // alloc_space_pages
};
};
struct {
struct {
__in struct remap_entry entries[];
__in struct remap_op entries[];
};
};