Difference between revisions of "Gamecard"
(Renumber cart pins to make end-end trace easier, at expense of dat lines becoming swizzled) |
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Line 27: | Line 27: | ||
! Description | ! Description | ||
|- | |- | ||
− | | | + | | 1, 2 |
− | | CD# | + | | CD# |
| Output | | Output | ||
− | | Single pin on cartridge side (hardwired to | + | | Card Detect; Single pin on cartridge side (hardwired to GND). Bridges pin 1 (GND) and 2 (CD#) on slot side as cartridge is inserted |
− | |- | + | |- |
− | | | + | | 3 |
+ | | CLK | ||
+ | | Input | ||
+ | | Clock, 25MHz | ||
+ | |- | ||
+ | | 4 | ||
| RCLK | | RCLK | ||
| Output | | Output | ||
| Return clock; Game cartridge sends back CLK signal delayed by a few ns | | Return clock; Game cartridge sends back CLK signal delayed by a few ns | ||
− | |- | + | |- |
− | | | + | | 5 |
− | |||
− | |||
− | |||
− | |||
− | |||
| CS# | | CS# | ||
| Input | | Input | ||
| Chip Select | | Chip Select | ||
− | |- | + | |- |
− | | | + | | 6 |
− | | DAT0 | + | | DAT1 |
+ | | Inout | ||
+ | | Data bus pin 1 | ||
+ | |- | ||
+ | | 7 | ||
+ | | DAT0 | ||
| Inout | | Inout | ||
| Data bus pin 0 | | Data bus pin 0 | ||
− | |- | + | |- |
− | | | + | | 8 |
− | + | | VCC 3.3v | |
− | |||
− | |||
− | |||
− | |||
− | | VCC 3.3v | ||
| Input | | Input | ||
| | | | ||
− | |- | + | |- |
− | | | + | | 9 |
− | | DAT2 | + | | DAT3 |
+ | | Inout | ||
+ | | Data bus pin 3 | ||
+ | |- | ||
+ | | 10 | ||
+ | | DAT2 | ||
| Inout | | Inout | ||
| Data bus pin 2 | | Data bus pin 2 | ||
− | |- | + | |- |
− | | | + | | 11 |
− | + | | VCC 1.8v | |
− | |||
− | |||
− | |||
− | |||
− | | VCC 1.8v | ||
| Input | | Input | ||
| | | | ||
− | |- | + | |- |
− | | | + | | 12 |
− | |||
− | |||
− | |||
− | |||
− | |||
| DAT5 | | DAT5 | ||
| Inout | | Inout | ||
| Data bus pin 5 | | Data bus pin 5 | ||
+ | |- | ||
+ | | 13 | ||
+ | | DAT4 | ||
+ | | Inout | ||
+ | | Data bus pin 4 | ||
|- | |- | ||
− | | | + | | 14 |
| DAT6 | | DAT6 | ||
| Inout | | Inout | ||
| Data bus pin 6 | | Data bus pin 6 | ||
− | |- | + | |- |
− | | | + | | 15 |
| DAT7 | | DAT7 | ||
| Inout | | Inout | ||
| Data bus pin 7 | | Data bus pin 7 | ||
− | |- | + | |- |
− | | | + | | 16 |
| GND | | GND | ||
− | | | + | | |
− | | | + | | |
− | |- | + | |- |
− | | | + | | 17 |
| RST# | | RST# | ||
| Input | | Input | ||
| Reset | | Reset | ||
− | |- | + | |- |
|} | |} | ||
Line 114: | Line 114: | ||
[[File:Card_slot.jpg|500px|thumb|right|Annotated slot pinout]] | [[File:Card_slot.jpg|500px|thumb|right|Annotated slot pinout]] | ||
− | + | This just maps the [[#Pinout|cartridge pinout]] onto the slot on the console. | |
{| class="wikitable" | {| class="wikitable" |
Revision as of 08:37, 21 June 2020
This page documents the Nintendo Switch Gamecard.
For the Gamecard partitions that can be mounted, see here.
For the Gamecard image format, see here.
For the Gamecard ASIC, see here.
Pinout
Pin | Name | Direction | Description |
---|---|---|---|
1, 2 | CD# | Output | Card Detect; Single pin on cartridge side (hardwired to GND). Bridges pin 1 (GND) and 2 (CD#) on slot side as cartridge is inserted |
3 | CLK | Input | Clock, 25MHz |
4 | RCLK | Output | Return clock; Game cartridge sends back CLK signal delayed by a few ns |
5 | CS# | Input | Chip Select |
6 | DAT1 | Inout | Data bus pin 1 |
7 | DAT0 | Inout | Data bus pin 0 |
8 | VCC 3.3v | Input | |
9 | DAT3 | Inout | Data bus pin 3 |
10 | DAT2 | Inout | Data bus pin 2 |
11 | VCC 1.8v | Input | |
12 | DAT5 | Inout | Data bus pin 5 |
13 | DAT4 | Inout | Data bus pin 4 |
14 | DAT6 | Inout | Data bus pin 6 |
15 | DAT7 | Inout | Data bus pin 7 |
16 | GND | ||
17 | RST# | Input | Reset |
All IO use 1.8V for logic HIGH and 0V for logic LOW.
Slot Pinout
This just maps the cartridge pinout onto the slot on the console.
Pin | Name |
---|---|
1 | GND |
2 | CD# |
3 | CLK |
4 | RCLK |
5 | CS# |
6 | DAT1 |
7 | DAT0 |
8 | VCC 3.3v |
9 | DAT3 |
10 | DAT2 |
11 | VCC 1.8v |
12 | DAT5 |
13 | DAT4 |
14 | DAT6 |
15 | DAT7 |
16 | GND |
17 | RST# |
Protocol
Switch game cartridges use a simple (but Nintendo proprietery) SPI-like bus with 8-bit width (DAT7..0). It is very similar to the bus interface of 3DS game cartridges, except with very different commands.
The Switch host starts a transfer by first pulling CS low, followed by clocking a byte each clock cycle. The bus data will always be ready before the rising edge of the CLK signal, so that it can be captured on the rising edge. After command bytes are written to the bus, the direction of the bus implicitly changes and the game cartridge responds. The Switch host keeps clocking while the game cartridge responds. After the transfer is ended, the CS line is pulled high again.
Commands are 16 bytes long, and followed immediately by a 4-byte CRC-32 over the command bytes. After this, the Switch stops driving the data bus, and the bus will be 'floating'. Due to the pull-ups on the bus, it will slowly converge to logic HIGH state. The Switch will clock 2 cycles to allow the bus to settle a direction change. The Switch host will then clock another cycle and if the game cartridge didn't receive the CRC OK, it will respond with "01". Otherwise it will respond with "00" and pull DAT0 low on the next cycle to signal it is busy. The Switch host will then keep clocking until the cartridge is ready.
When the game cartridge is ready to send the actual data response, it will pull the DAT0 pin high for 2 cycles to let the Switch host know. After this, the game cartridge will send the actual data response bytes.
The actual response bytes are also followed immediately by a 4-byte CRC-32 over the actual data response bytes.
A typical boot up sequence of a game cartridge (in this case, the game "1,2 Switch") looks like this:
Command | Size | Description |
---|---|---|
5B000000000000010000000000000000
|
0x200 | Read sector 0, contains "HEAD" blob |
5B000000000000010000000000000000
|
0x200 | Read sector 0, contains "HEAD" blob |
56000000000000000000000000000000
|
0x4 | Read card id "AE F8 01 21" |
28000000000000000000000000000000
|
0x4 | Read ??? "02 00 00 00" |
A5000000000000000000000000000000
|
0x4 | Read ??? "00 00 00 00" |
56000000000000000000000000000000
|
0x4 | Read card id "AE F8 01 21" |
28000000000000000000000000000000
|
0x4 | Read ??? "02 00 00 00" |
5B000000380000010000000000000000
|
0x200 | Read sector 0x38, contains "CERT" blob |
E2000000000000000000000000000000
|
0x4 | Read ??? "01 00 00 00" |
E0000000000000000000000000000000
|
0x200 | Read crypto-challenge header |
200838A25A344F818ABB6456694D4E8D
|
0 | Enter crypto mode1 with HOST-RANDOM "0838A25A344F818ABB6456694D4E8D" |
7EE41FDF12C01C157CC899910673A0CF
|
0x40 | Encrypted crypto mode1 command, reads CART-RANDOM |
263C8230EC15FAE3CE79365BD850F4BD
|
0x0 | Encrypted mode1 command, enters crypto mode2 with (HOST-RANDOM, CART-RANDOM) |
B6FDA6F37FFA29E18831D0B217DFBDBE
|
0x4 | Encrypted mode2 command, possibly read card id? |
7B97F7DF07240AA9870E1C974336FA8A
|
0x4 | Encrypted mode2 command |
Manufacturers
- Macronix (MX)
- Uses package: LGA, TSOP-48
- Uses card id: 0xC2
- Renesas
- Uses package: LGA, TSOP-48
- Uses card id: 0x23
- SanDisk?
- Uses package: ??
- Uses card id: 0x45 ?