TSEC: Difference between revisions
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=== | === TSEC_BAR0_CTL === | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! Bits | ! Bits | ||
| Line 2,707: | Line 2,707: | ||
|- | |- | ||
| 0 | | 0 | ||
| | | TSEC_BAR0_CTL_READ | ||
|- | |- | ||
| 1 | | 1 | ||
| | | TSEC_BAR0_CTL_WRITE | ||
|- | |- | ||
| 4-7 | | 4-7 | ||
| | | TSEC_BAR0_CTL_BYTE_MASK | ||
|- | |- | ||
| 12-13 | | 12-13 | ||
| | | TSEC_BAR0_CTL_STATUS | ||
0: Idle | 0: Idle | ||
1: Busy | 1: Busy | ||
| Line 2,723: | Line 2,723: | ||
|- | |- | ||
| 31 | | 31 | ||
| | | TSEC_BAR0_CTL_INIT | ||
|} | |} | ||
A DMA read/write operation requires bits | A BAR0 DMA read/write operation requires bits TSEC_BAR0_CTL_INIT and TSEC_BAR0_CTL_READ/TSEC_BAR0_CTL_WRITE to be set in TSEC_BAR0_CTL. | ||
During the transfer, | During the transfer, TSEC_BAR0_CTL_STATUS is set to "Busy". | ||
Accessing an invalid address sets | Accessing an invalid address sets TSEC_BAR0_CTL_STATUS to "Error". | ||
=== | === TSEC_BAR0_ADDR === | ||
Takes the address for DMA transfers between TSEC and HOST1X (master and clients). | Takes the address for DMA transfers between TSEC and HOST1X (master and clients). | ||
=== | === TSEC_BAR0_DATA === | ||
Takes the data for DMA transfers between TSEC and HOST1X (master and clients). | Takes the data for DMA transfers between TSEC and HOST1X (master and clients). | ||
=== | === TSEC_BAR0_TIMEOUT === | ||
Takes the timeout value for DMA transfers between TSEC and HOST1X (master and clients). | |||
=== TSEC_TEGRA_CTL === | === TSEC_TEGRA_CTL === | ||